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GET /api/patches/954064/?format=api
{ "id": 954064, "url": "http://patchwork.ozlabs.org/api/patches/954064/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1533574847-19294-38-git-send-email-aleksandar.markovic@rt-rk.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1533574847-19294-38-git-send-email-aleksandar.markovic@rt-rk.com>", "list_archive_url": null, "date": "2018-08-06T17:00:04", "name": "[v7,37/80] target/mips: Add emulation of nanoMIPS 32-bit branch instructions", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "57e8680a56a42a719e5559c9ebe6ec83acb1e304", "submitter": { "id": 68635, "url": "http://patchwork.ozlabs.org/api/people/68635/?format=api", "name": "Aleksandar Markovic", "email": "aleksandar.markovic@rt-rk.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1533574847-19294-38-git-send-email-aleksandar.markovic@rt-rk.com/mbox/", "series": [ { "id": 59520, "url": "http://patchwork.ozlabs.org/api/series/59520/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=59520", "date": "2018-08-06T16:59:27", "name": "Add nanoMIPS support to QEMU", "version": 7, "mbox": "http://patchwork.ozlabs.org/series/59520/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/954064/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/954064/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=none (p=none dis=none) header.from=rt-rk.com" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 41klW52bCqz9rvt\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 7 Aug 2018 03:48:33 +1000 (AEST)", "from localhost ([::1]:35424 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1fmjcN-00027d-29\n\tfor incoming@patchwork.ozlabs.org; Mon, 06 Aug 2018 13:48:31 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:33001)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <aleksandar.markovic@rt-rk.com>) id 1fmj6c-0006kM-K3\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:15:44 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <aleksandar.markovic@rt-rk.com>) id 1fmj6a-0007R9-SP\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:15:42 -0400", "from mx2.rt-rk.com ([89.216.37.149]:53929 helo=mail.rt-rk.com)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <aleksandar.markovic@rt-rk.com>)\n\tid 1fmj6a-0007OZ-1a\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:15:40 -0400", "from localhost (localhost [127.0.0.1])\n\tby mail.rt-rk.com (Postfix) with ESMTP id 3DE071A20AF;\n\tMon, 6 Aug 2018 19:15:38 +0200 (CEST)", "from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local\n\t[10.10.13.43])\n\tby mail.rt-rk.com (Postfix) with ESMTPSA id 0F8FA1A2036;\n\tMon, 6 Aug 2018 19:15:38 +0200 (CEST)" ], "X-Virus-Scanned": "amavisd-new at rt-rk.com", "From": "Aleksandar Markovic <aleksandar.markovic@rt-rk.com>", "To": "qemu-devel@nongnu.org", "Date": "Mon, 6 Aug 2018 19:00:04 +0200", "Message-Id": "<1533574847-19294-38-git-send-email-aleksandar.markovic@rt-rk.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1533574847-19294-1-git-send-email-aleksandar.markovic@rt-rk.com>", "References": "<1533574847-19294-1-git-send-email-aleksandar.markovic@rt-rk.com>", "X-detected-operating-system": "by eggs.gnu.org: GNU/Linux 3.x [fuzzy]", "X-Received-From": "89.216.37.149", "Subject": "[Qemu-devel] [PATCH v7 37/80] target/mips: Add emulation of\n\tnanoMIPS 32-bit branch instructions", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, thuth@redhat.com, pburton@wavecomp.com,\n\tsmarkovic@wavecomp.com, riku.voipio@iki.fi,\n\trichard.henderson@linaro.org, laurent@vivier.eu,\n\tarmbru@redhat.com, arikalo@wavecomp.com,\n\tphilippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com,\n\tpjovanovic@wavecomp.com, aurelien@aurel32.net", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Yongbok Kim <yongbok.kim@mips.com>\n\nAdd emulation of various flavors of nanoMIPS 32-bit branch\ninstructions.\n\nReviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>\nSigned-off-by: Yongbok Kim <yongbok.kim@mips.com>\nSigned-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>\nSigned-off-by: Stefan Markovic <smarkovic@wavecomp.com>\n---\n target/mips/translate.c | 262 ++++++++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 262 insertions(+)", "diff": "diff --git a/target/mips/translate.c b/target/mips/translate.c\nindex 945dd73..c1f80e7 100644\n--- a/target/mips/translate.c\n+++ b/target/mips/translate.c\n@@ -17013,6 +17013,155 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)\n }\n }\n \n+/* Immediate Value Compact Branches */\n+static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc,\n+ int rt, int32_t imm, int32_t offset)\n+{\n+ TCGCond cond;\n+ int bcond_compute = 0;\n+ TCGv t0 = tcg_temp_new();\n+ TCGv t1 = tcg_temp_new();\n+\n+ if (ctx->hflags & MIPS_HFLAG_BMASK) {\n+#ifdef MIPS_DEBUG_DISAS\n+ LOG_DISAS(\"Branch in delay / forbidden slot at PC 0x\" TARGET_FMT_lx\n+ \"\\n\", ctx->base.pc_next);\n+#endif\n+ generate_exception_end(ctx, EXCP_RI);\n+ goto out;\n+ }\n+\n+ gen_load_gpr(t0, rt);\n+ tcg_gen_movi_tl(t1, imm);\n+ ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);\n+\n+ /* Load needed operands and calculate btarget */\n+ switch (opc) {\n+ case NM_BEQIC:\n+ if (rt == 0 && imm == 0) {\n+ /* Unconditional branch */\n+ } else if (rt == 0 && imm != 0) {\n+ /* Treat as NOP */\n+ goto out;\n+ } else {\n+ bcond_compute = 1;\n+ cond = TCG_COND_EQ;\n+ }\n+ break;\n+ case NM_BBEQZC:\n+ case NM_BBNEZC:\n+ if (imm >= 32 && !(ctx->hflags & MIPS_HFLAG_64)) {\n+ generate_exception_end(ctx, EXCP_RI);\n+ goto out;\n+ } else if (rt == 0 && opc == NM_BBEQZC) {\n+ /* Unconditional branch */\n+ } else if (rt == 0 && opc == NM_BBNEZC) {\n+ /* Treat as NOP */\n+ goto out;\n+ } else {\n+ tcg_gen_shri_tl(t0, t0, imm);\n+ tcg_gen_andi_tl(t0, t0, 1);\n+ tcg_gen_movi_tl(t1, 0);\n+ bcond_compute = 1;\n+ if (opc == NM_BBEQZC) {\n+ cond = TCG_COND_EQ;\n+ } else {\n+ cond = TCG_COND_NE;\n+ }\n+ }\n+ break;\n+ case NM_BNEIC:\n+ if (rt == 0 && imm == 0) {\n+ /* Treat as NOP */\n+ goto out;\n+ } else if (rt == 0 && imm != 0) {\n+ /* Unconditional branch */\n+ } else {\n+ bcond_compute = 1;\n+ cond = TCG_COND_NE;\n+ }\n+ break;\n+ case NM_BGEIC:\n+ if (rt == 0 && imm == 0) {\n+ /* Unconditional branch */\n+ } else {\n+ bcond_compute = 1;\n+ cond = TCG_COND_GE;\n+ }\n+ break;\n+ case NM_BLTIC:\n+ bcond_compute = 1;\n+ cond = TCG_COND_LT;\n+ break;\n+ case NM_BGEIUC:\n+ if (rt == 0 && imm == 0) {\n+ /* Unconditional branch */\n+ } else {\n+ bcond_compute = 1;\n+ cond = TCG_COND_GEU;\n+ }\n+ break;\n+ case NM_BLTIUC:\n+ bcond_compute = 1;\n+ cond = TCG_COND_LTU;\n+ break;\n+ default:\n+ MIPS_INVAL(\"Immediate Value Compact branch\");\n+ generate_exception_end(ctx, EXCP_RI);\n+ goto out;\n+ }\n+\n+ if (bcond_compute == 0) {\n+ /* Uncoditional compact branch */\n+ ctx->hflags |= MIPS_HFLAG_B;\n+ /* Generating branch here as compact branches don't have delay slot */\n+ gen_branch(ctx, 4);\n+ } else {\n+ /* Conditional compact branch */\n+ TCGLabel *fs = gen_new_label();\n+ save_cpu_state(ctx, 0);\n+\n+ tcg_gen_brcond_tl(tcg_invert_cond(cond), t0, t1, fs);\n+\n+ /* Generating branch here as compact branches don't have delay slot */\n+ gen_goto_tb(ctx, 1, ctx->btarget);\n+ gen_set_label(fs);\n+\n+ ctx->hflags |= MIPS_HFLAG_FBNSLOT;\n+ }\n+\n+out:\n+ tcg_temp_free(t0);\n+ tcg_temp_free(t1);\n+}\n+\n+/* P.BALRSC type nanoMIPS R6 branches: BALRSC and BRSC */\n+static void gen_compute_nanomips_pbalrsc_branch(DisasContext *ctx, int rs,\n+ int rt)\n+{\n+ TCGv t0 = tcg_temp_new();\n+ TCGv t1 = tcg_temp_new();\n+\n+ /* load rs */\n+ gen_load_gpr(t0, rs);\n+\n+ /* link */\n+ if (rt != 0) {\n+ tcg_gen_movi_tl(cpu_gpr[rt], ctx->base.pc_next + 4);\n+ }\n+\n+ /* calculate btarget */\n+ tcg_gen_shli_tl(t0, t0, 1);\n+ tcg_gen_movi_tl(t1, ctx->base.pc_next + 4);\n+ gen_op_addr_add(ctx, btarget, t1, t0);\n+\n+ ctx->hflags |= MIPS_HFLAG_BR;\n+ /* Generating branch here as compact branches don't have delay slot */\n+ gen_branch(ctx, 4);\n+\n+ tcg_temp_free(t0);\n+ tcg_temp_free(t1);\n+}\n \n static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt)\n {\n@@ -18079,16 +18228,129 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)\n }\n break;\n case NM_MOVE_BALC:\n+ {\n+ TCGv t0 = tcg_temp_new();\n+ int32_t s = sextract32(ctx->opcode, 0, 1) << 21 |\n+ extract32(ctx->opcode, 1, 20) << 1;\n+ rd = (extract32(ctx->opcode, 24, 1)) == 0 ? 4 : 5;\n+ rt = decode_gpr_gpr4_zero(extract32(ctx->opcode, 25, 1) << 3 |\n+ extract32(ctx->opcode, 21, 3));\n+ gen_load_gpr(t0, rt);\n+ tcg_gen_mov_tl(cpu_gpr[rd], t0);\n+ gen_compute_branch(ctx, OPC_BGEZAL, 4, 0, 0, s, 0);\n+ tcg_temp_free(t0);\n+ }\n break;\n case NM_P_BAL:\n+ {\n+ int32_t s = sextract32(ctx->opcode, 0, 1) << 25 |\n+ extract32(ctx->opcode, 1, 24) << 1;\n+\n+ if ((extract32(ctx->opcode, 25, 1)) == 0) {\n+ /* BC */\n+ gen_compute_branch(ctx, OPC_BEQ, 4, 0, 0, s, 0);\n+ } else {\n+ /* BALC */\n+ gen_compute_branch(ctx, OPC_BGEZAL, 4, 0, 0, s, 0);\n+ }\n+ }\n break;\n case NM_P_J:\n+ switch (extract32(ctx->opcode, 12, 4)) {\n+ case NM_JALRC:\n+ case NM_JALRC_HB:\n+ gen_compute_branch(ctx, OPC_JALR, 4, rs, rt, 0, 0);\n+ break;\n+ case NM_P_BALRSC:\n+ gen_compute_nanomips_pbalrsc_branch(ctx, rs, rt);\n+ break;\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n break;\n case NM_P_BR1:\n+ {\n+ int32_t s = sextract32(ctx->opcode, 0, 1) << 14 |\n+ extract32(ctx->opcode, 1, 13) << 1;\n+ switch (extract32(ctx->opcode, 14, 2)) {\n+ case NM_BEQC:\n+ gen_compute_branch(ctx, OPC_BEQ, 4, rs, rt, s, 0);\n+ break;\n+ case NM_P_BR3A:\n+ s = sextract32(ctx->opcode, 0, 1) << 14 |\n+ extract32(ctx->opcode, 1, 13) << 1;\n+ check_cp1_enabled(ctx);\n+ switch (extract32(ctx->opcode, 16, 5)) {\n+ case NM_BC1EQZC:\n+ gen_compute_branch1_r6(ctx, OPC_BC1EQZ, rt, s, 0);\n+ break;\n+ case NM_BC1NEZC:\n+ gen_compute_branch1_r6(ctx, OPC_BC1NEZ, rt, s, 0);\n+ break;\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n+ break;\n+ case NM_BGEC:\n+ if (rs == rt) {\n+ gen_compute_compact_branch(ctx, OPC_BC, rs, rt, s);\n+ } else {\n+ gen_compute_compact_branch(ctx, OPC_BGEC, rs, rt, s);\n+ }\n+ break;\n+ case NM_BGEUC:\n+ if (rs == rt || rt == 0) {\n+ gen_compute_compact_branch(ctx, OPC_BC, 0, 0, s);\n+ } else if (rs == 0) {\n+ gen_compute_compact_branch(ctx, OPC_BEQZC, rt, 0, s);\n+ } else {\n+ gen_compute_compact_branch(ctx, OPC_BGEUC, rs, rt, s);\n+ }\n+ break;\n+ }\n+ }\n break;\n case NM_P_BR2:\n+ {\n+ int32_t s = sextract32(ctx->opcode, 0, 1) << 14 |\n+ extract32(ctx->opcode, 1, 13) << 1;\n+ switch (extract32(ctx->opcode, 14, 2)) {\n+ case NM_BNEC:\n+ gen_compute_branch(ctx, OPC_BNE, 4, rs, rt, s, 0);\n+ break;\n+ case NM_BLTC:\n+ if (rs != 0 && rt != 0 && rs == rt) {\n+ /* NOP */\n+ ctx->hflags |= MIPS_HFLAG_FBNSLOT;\n+ } else {\n+ gen_compute_compact_branch(ctx, OPC_BLTC, rs, rt, s);\n+ }\n+ break;\n+ case NM_BLTUC:\n+ if (rs == 0 || rs == rt) {\n+ /* NOP */\n+ ctx->hflags |= MIPS_HFLAG_FBNSLOT;\n+ } else {\n+ gen_compute_compact_branch(ctx, OPC_BLTUC, rs, rt, s);\n+ }\n+ break;\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n+ }\n break;\n case NM_P_BRI:\n+ {\n+ int32_t s = sextract32(ctx->opcode, 0, 1) << 11 |\n+ extract32(ctx->opcode, 1, 10) << 1;\n+ uint32_t u = extract32(ctx->opcode, 11, 7);\n+\n+ gen_compute_imm_branch(ctx, extract32(ctx->opcode, 18, 3),\n+ rt, u, s);\n+ }\n break;\n default:\n generate_exception_end(ctx, EXCP_RI);\n", "prefixes": [ "v7", "37/80" ] }