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GET /api/patches/954060/?format=api
{ "id": 954060, "url": "http://patchwork.ozlabs.org/api/patches/954060/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1533574847-19294-62-git-send-email-aleksandar.markovic@rt-rk.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1533574847-19294-62-git-send-email-aleksandar.markovic@rt-rk.com>", "list_archive_url": null, "date": "2018-08-06T17:00:28", "name": "[v7,61/80] target/mips: Add definition of nanoMIPS I7200 CPU", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "367ff37bc66dbcb3f93203532967bf5811326e2c", "submitter": { "id": 68635, "url": "http://patchwork.ozlabs.org/api/people/68635/?format=api", "name": "Aleksandar Markovic", "email": "aleksandar.markovic@rt-rk.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1533574847-19294-62-git-send-email-aleksandar.markovic@rt-rk.com/mbox/", "series": [ { "id": 59520, "url": "http://patchwork.ozlabs.org/api/series/59520/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=59520", "date": "2018-08-06T16:59:27", "name": "Add nanoMIPS support to QEMU", "version": 7, "mbox": "http://patchwork.ozlabs.org/series/59520/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/954060/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/954060/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=none (p=none dis=none) header.from=rt-rk.com" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 41klTF1g1fz9rvt\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 7 Aug 2018 03:46:57 +1000 (AEST)", "from localhost ([::1]:35417 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1fmjao-0000It-RP\n\tfor incoming@patchwork.ozlabs.org; Mon, 06 Aug 2018 13:46:54 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:41641)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <aleksandar.markovic@rt-rk.com>) id 1fmjGc-0007ku-Lm\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:26:03 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <aleksandar.markovic@rt-rk.com>) id 1fmjGb-0002Gw-LD\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:26:02 -0400", "from mx2.rt-rk.com ([89.216.37.149]:45948 helo=mail.rt-rk.com)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <aleksandar.markovic@rt-rk.com>)\n\tid 1fmjGb-0002FT-9X\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:26:01 -0400", "from localhost (localhost [127.0.0.1])\n\tby mail.rt-rk.com (Postfix) with ESMTP id 0DDAE1A2176;\n\tMon, 6 Aug 2018 19:26:00 +0200 (CEST)", "from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local\n\t[10.10.13.43])\n\tby mail.rt-rk.com (Postfix) with ESMTPSA id DE8DA1A2036;\n\tMon, 6 Aug 2018 19:25:59 +0200 (CEST)" ], "X-Virus-Scanned": "amavisd-new at rt-rk.com", "From": "Aleksandar Markovic <aleksandar.markovic@rt-rk.com>", "To": "qemu-devel@nongnu.org", "Date": "Mon, 6 Aug 2018 19:00:28 +0200", "Message-Id": "<1533574847-19294-62-git-send-email-aleksandar.markovic@rt-rk.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1533574847-19294-1-git-send-email-aleksandar.markovic@rt-rk.com>", "References": "<1533574847-19294-1-git-send-email-aleksandar.markovic@rt-rk.com>", "X-detected-operating-system": "by eggs.gnu.org: GNU/Linux 3.x [fuzzy]", "X-Received-From": "89.216.37.149", "Subject": "[Qemu-devel] [PATCH v7 61/80] target/mips: Add definition of\n\tnanoMIPS I7200 CPU", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, thuth@redhat.com, pburton@wavecomp.com,\n\tsmarkovic@wavecomp.com, riku.voipio@iki.fi,\n\trichard.henderson@linaro.org, laurent@vivier.eu,\n\tarmbru@redhat.com, arikalo@wavecomp.com,\n\tphilippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com,\n\tpjovanovic@wavecomp.com, aurelien@aurel32.net", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Stefan Markovic <smarkovic@wavecomp.com>\n\nAdd definition of the first nanoMIPS processor in QEMU.\n\nSigned-off-by: Yongbok Kim <yongbok.kim@mips.com>\nSigned-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>\nSigned-off-by: Stefan Markovic <smarkovic@wavecomp.com>\n---\n target/mips/translate_init.inc.c | 39 +++++++++++++++++++++++++++++++++++++++\n 1 file changed, 39 insertions(+)", "diff": "diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.inc.c\nindex c7ba6ee..b3320b9 100644\n--- a/target/mips/translate_init.inc.c\n+++ b/target/mips/translate_init.inc.c\n@@ -449,6 +449,45 @@ const mips_def_t mips_defs[] =\n .insn_flags = CPU_MIPS32R6 | ASE_MICROMIPS,\n .mmu_type = MMU_TYPE_R4000,\n },\n+ {\n+ .name = \"I7200\",\n+ .CP0_PRid = 0x00010000,\n+ .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (0x2 << CP0C0_AR) |\n+ (MMU_TYPE_R4000 << CP0C0_MT),\n+ .CP0_Config1 = (1U << CP0C1_M) | (15 << CP0C1_MMU) | (2 << CP0C1_IS) |\n+ (4 << CP0C1_IL) | (3 << CP0C1_IA) | (2 << CP0C1_DS) |\n+ (4 << CP0C1_DL) | (3 << CP0C1_DA) | (1 << CP0C1_PC) |\n+ (1 << CP0C1_EP),\n+ .CP0_Config2 = MIPS_CONFIG2,\n+ .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_CMGCR) |\n+ (1 << CP0C3_BI) | (1 << CP0C3_SC) | (3 << CP0C3_MMAR) |\n+ (1 << CP0C3_ISA_ON_EXC) | (1 << CP0C3_ISA) |\n+ (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) |\n+ (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) |\n+ (1 << CP0C3_CTXTC) | (1 << CP0C3_VInt) |\n+ (1 << CP0C3_CDMM) | (1 << CP0C3_MT) | (1 << CP0C3_TL),\n+ .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) |\n+ (2 << CP0C4_IE) | (1U << CP0C4_M),\n+ .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_MVH) | (1 << CP0C5_LLB),\n+ .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) |\n+ (1 << CP0C5_UFE),\n+ .CP0_LLAddr_rw_bitmask = 0,\n+ .CP0_LLAddr_shift = 0,\n+ .SYNCI_Step = 32,\n+ .CCRes = 2,\n+ .CP0_Status_rw_bitmask = 0x3158FF1F,\n+ .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |\n+ (1U << CP0PG_RIE),\n+ .CP0_PageGrain_rw_bitmask = 0,\n+ .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |\n+ (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |\n+ (1 << FCR0_S) | (0x02 << FCR0_PRID) | (0x0 << FCR0_REV),\n+ .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),\n+ .SEGBITS = 32,\n+ .PABITS = 32,\n+ .insn_flags = CPU_NANOMIPS32 | ASE_DSP | ASE_DSPR2 | ASE_MT,\n+ .mmu_type = MMU_TYPE_R4000,\n+ },\n #if defined(TARGET_MIPS64)\n {\n .name = \"R4000\",\n", "prefixes": [ "v7", "61/80" ] }