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GET /api/patches/954056/?format=api
{ "id": 954056, "url": "http://patchwork.ozlabs.org/api/patches/954056/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1533574847-19294-34-git-send-email-aleksandar.markovic@rt-rk.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1533574847-19294-34-git-send-email-aleksandar.markovic@rt-rk.com>", "list_archive_url": null, "date": "2018-08-06T17:00:00", "name": "[v7,33/80] target/mips: Implement emulation of nanoMIPS ROTX instruction", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "7d1f09f9df6d66905f9345fcafd5e5ca141c1e42", "submitter": { "id": 68635, "url": "http://patchwork.ozlabs.org/api/people/68635/?format=api", "name": "Aleksandar Markovic", "email": "aleksandar.markovic@rt-rk.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1533574847-19294-34-git-send-email-aleksandar.markovic@rt-rk.com/mbox/", "series": [ { "id": 59520, "url": "http://patchwork.ozlabs.org/api/series/59520/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=59520", "date": "2018-08-06T16:59:27", "name": "Add nanoMIPS support to QEMU", "version": 7, "mbox": "http://patchwork.ozlabs.org/series/59520/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/954056/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/954056/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=none (p=none dis=none) header.from=rt-rk.com" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 41klRW0NVZz9rvt\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 7 Aug 2018 03:45:27 +1000 (AEST)", "from localhost ([::1]:35407 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1fmjZM-0007Th-M1\n\tfor incoming@patchwork.ozlabs.org; Mon, 06 Aug 2018 13:45:24 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:59993)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <aleksandar.markovic@rt-rk.com>) id 1fmj57-0004le-M0\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:14:11 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <aleksandar.markovic@rt-rk.com>) id 1fmj54-00066q-TV\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:14:09 -0400", "from mx2.rt-rk.com ([89.216.37.149]:49522 helo=mail.rt-rk.com)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <aleksandar.markovic@rt-rk.com>)\n\tid 1fmj54-00065C-GU\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:14:06 -0400", "from localhost (localhost [127.0.0.1])\n\tby mail.rt-rk.com (Postfix) with ESMTP id 39F1F1A209A;\n\tMon, 6 Aug 2018 19:14:05 +0200 (CEST)", "from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local\n\t[10.10.13.43])\n\tby mail.rt-rk.com (Postfix) with ESMTPSA id 159B91A2036;\n\tMon, 6 Aug 2018 19:14:05 +0200 (CEST)" ], "X-Virus-Scanned": "amavisd-new at rt-rk.com", "From": "Aleksandar Markovic <aleksandar.markovic@rt-rk.com>", "To": "qemu-devel@nongnu.org", "Date": "Mon, 6 Aug 2018 19:00:00 +0200", "Message-Id": "<1533574847-19294-34-git-send-email-aleksandar.markovic@rt-rk.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1533574847-19294-1-git-send-email-aleksandar.markovic@rt-rk.com>", "References": "<1533574847-19294-1-git-send-email-aleksandar.markovic@rt-rk.com>", "X-detected-operating-system": "by eggs.gnu.org: GNU/Linux 3.x [fuzzy]", "X-Received-From": "89.216.37.149", "Subject": "[Qemu-devel] [PATCH v7 33/80] target/mips: Implement emulation of\n\tnanoMIPS ROTX instruction", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, thuth@redhat.com, pburton@wavecomp.com,\n\tsmarkovic@wavecomp.com, riku.voipio@iki.fi,\n\trichard.henderson@linaro.org, laurent@vivier.eu,\n\tarmbru@redhat.com, arikalo@wavecomp.com,\n\tphilippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com,\n\tpjovanovic@wavecomp.com, aurelien@aurel32.net", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Matthew Fortune <matthew.fortune@mips.com>\n\nAdded a helper for ROTX based on the pseudocode from the\narchitecture spec. This instraction was not present in previous\nMIPS instruction sets.\n\nSigned-off-by: Yongbok Kim <yongbok.kim@mips.com>\nSigned-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>\nSigned-off-by: Stefan Markovic <smarkovic@wavecomp.com>\nReviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\n---\n target/mips/helper.h | 2 ++\n target/mips/op_helper.c | 94 +++++++++++++++++++++++++++++++++++++++++++++++++\n target/mips/translate.c | 15 ++++++++\n 3 files changed, 111 insertions(+)", "diff": "diff --git a/target/mips/helper.h b/target/mips/helper.h\nindex 5f49234..b2a780a 100644\n--- a/target/mips/helper.h\n+++ b/target/mips/helper.h\n@@ -40,6 +40,8 @@ DEF_HELPER_FLAGS_1(bitswap, TCG_CALL_NO_RWG_SE, tl, tl)\n DEF_HELPER_FLAGS_1(dbitswap, TCG_CALL_NO_RWG_SE, tl, tl)\n #endif\n \n+DEF_HELPER_FLAGS_4(rotx, TCG_CALL_NO_RWG_SE, tl, tl, i32, i32, i32)\n+\n #ifndef CONFIG_USER_ONLY\n /* CP0 helpers */\n DEF_HELPER_1(mfc0_mvpcontrol, tl, env)\ndiff --git a/target/mips/op_helper.c b/target/mips/op_helper.c\nindex 0b2663b..b3eef9f 100644\n--- a/target/mips/op_helper.c\n+++ b/target/mips/op_helper.c\n@@ -249,6 +249,100 @@ target_ulong helper_bitswap(target_ulong rt)\n return (int32_t)bitswap(rt);\n }\n \n+target_ulong helper_rotx(target_ulong rs, uint32_t shift, uint32_t shiftx,\n+ uint32_t stripe)\n+{\n+ int i;\n+ uint64_t tmp0 = ((uint64_t)rs) << 32 | ((uint64_t)rs & 0xffffffff);\n+ uint64_t tmp1 = tmp0;\n+ for (i = 0; i <= 46; i++) {\n+ int s;\n+ if (i & 0x8) {\n+ s = shift;\n+ } else {\n+ s = shiftx;\n+ }\n+\n+ if (stripe != 0 && !(i & 0x4)) {\n+ s = ~s;\n+ }\n+ if (s & 0x10) {\n+ if (tmp0 & (1LL << (i + 16))) {\n+ tmp1 |= 1LL << i;\n+ } else {\n+ tmp1 &= ~(1LL << i);\n+ }\n+ }\n+ }\n+\n+ uint64_t tmp2 = tmp1;\n+ for (i = 0; i <= 38; i++) {\n+ int s;\n+ if (i & 0x4) {\n+ s = shift;\n+ } else {\n+ s = shiftx;\n+ }\n+\n+ if (s & 0x8) {\n+ if (tmp1 & (1LL << (i + 8))) {\n+ tmp2 |= 1LL << i;\n+ } else {\n+ tmp2 &= ~(1LL << i);\n+ }\n+ }\n+ }\n+\n+ uint64_t tmp3 = tmp2;\n+ for (i = 0; i <= 34; i++) {\n+ int s;\n+ if (i & 0x2) {\n+ s = shift;\n+ } else {\n+ s = shiftx;\n+ }\n+ if (s & 0x4) {\n+ if (tmp2 & (1LL << (i + 4))) {\n+ tmp3 |= 1LL << i;\n+ } else {\n+ tmp3 &= ~(1LL << i);\n+ }\n+ }\n+ }\n+\n+ uint64_t tmp4 = tmp3;\n+ for (i = 0; i <= 32; i++) {\n+ int s;\n+ if (i & 0x1) {\n+ s = shift;\n+ } else {\n+ s = shiftx;\n+ }\n+ if (s & 0x2) {\n+ if (tmp3 & (1LL << (i + 2))) {\n+ tmp4 |= 1LL << i;\n+ } else {\n+ tmp4 &= ~(1LL << i);\n+ }\n+ }\n+ }\n+\n+ uint64_t tmp5 = tmp4;\n+ for (i = 0; i <= 31; i++) {\n+ int s;\n+ s = shift;\n+ if (s & 0x1) {\n+ if (tmp4 & (1LL << (i + 1))) {\n+ tmp5 |= 1LL << i;\n+ } else {\n+ tmp5 &= ~(1LL << i);\n+ }\n+ }\n+ }\n+\n+ return (int64_t)(int32_t)(uint32_t)tmp5;\n+}\n+\n #ifndef CONFIG_USER_ONLY\n \n static inline hwaddr do_translate_address(CPUMIPSState *env,\ndiff --git a/target/mips/translate.c b/target/mips/translate.c\nindex 657e9c0..c171bb8 100644\n--- a/target/mips/translate.c\n+++ b/target/mips/translate.c\n@@ -17621,6 +17621,21 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)\n }\n break;\n case NM_P_ROTX:\n+ if (rt != 0) {\n+ TCGv t0 = tcg_temp_new();\n+ TCGv_i32 shift = tcg_const_i32(extract32(ctx->opcode, 0, 5));\n+ TCGv_i32 shiftx = tcg_const_i32(extract32(ctx->opcode, 7, 4)\n+ << 1);\n+ TCGv_i32 stripe = tcg_const_i32(extract32(ctx->opcode, 6, 1));\n+\n+ gen_load_gpr(t0, rs);\n+ gen_helper_rotx(cpu_gpr[rt], t0, shift, shiftx, stripe);\n+ tcg_temp_free(t0);\n+\n+ tcg_temp_free_i32(shift);\n+ tcg_temp_free_i32(shiftx);\n+ tcg_temp_free_i32(stripe);\n+ }\n break;\n case NM_P_INS:\n switch (((ctx->opcode >> 10) & 2) |\n", "prefixes": [ "v7", "33/80" ] }