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GET /api/patches/954045/?format=api
{ "id": 954045, "url": "http://patchwork.ozlabs.org/api/patches/954045/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1533574847-19294-31-git-send-email-aleksandar.markovic@rt-rk.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1533574847-19294-31-git-send-email-aleksandar.markovic@rt-rk.com>", "list_archive_url": null, "date": "2018-08-06T16:59:57", "name": "[v7,30/80] target/mips: Add emulation of misc nanoMIPS instructions (pool32a0)", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "eed9bfc9d55421459101d9b0bfa5a5782532e639", "submitter": { "id": 68635, "url": "http://patchwork.ozlabs.org/api/people/68635/?format=api", "name": "Aleksandar Markovic", "email": "aleksandar.markovic@rt-rk.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1533574847-19294-31-git-send-email-aleksandar.markovic@rt-rk.com/mbox/", "series": [ { "id": 59520, "url": "http://patchwork.ozlabs.org/api/series/59520/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=59520", "date": "2018-08-06T16:59:27", "name": "Add nanoMIPS support to QEMU", "version": 7, "mbox": "http://patchwork.ozlabs.org/series/59520/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/954045/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/954045/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=none (p=none dis=none) header.from=rt-rk.com" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 41klKG3XtTz9ryt\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 7 Aug 2018 03:40:02 +1000 (AEST)", "from localhost ([::1]:35376 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1fmjU8-0002n4-3y\n\tfor incoming@patchwork.ozlabs.org; Mon, 06 Aug 2018 13:40:00 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:58898)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <aleksandar.markovic@rt-rk.com>) id 1fmj44-0003nV-HO\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:13:05 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <aleksandar.markovic@rt-rk.com>) id 1fmj43-00055b-15\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:13:04 -0400", "from mx2.rt-rk.com ([89.216.37.149]:48965 helo=mail.rt-rk.com)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <aleksandar.markovic@rt-rk.com>)\n\tid 1fmj42-00053e-K9\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:13:02 -0400", "from localhost (localhost [127.0.0.1])\n\tby mail.rt-rk.com (Postfix) with ESMTP id 7155F1A209A;\n\tMon, 6 Aug 2018 19:13:01 +0200 (CEST)", "from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local\n\t[10.10.13.43])\n\tby mail.rt-rk.com (Postfix) with ESMTPSA id 4CA191A2036;\n\tMon, 6 Aug 2018 19:13:01 +0200 (CEST)" ], "X-Virus-Scanned": "amavisd-new at rt-rk.com", "From": "Aleksandar Markovic <aleksandar.markovic@rt-rk.com>", "To": "qemu-devel@nongnu.org", "Date": "Mon, 6 Aug 2018 18:59:57 +0200", "Message-Id": "<1533574847-19294-31-git-send-email-aleksandar.markovic@rt-rk.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1533574847-19294-1-git-send-email-aleksandar.markovic@rt-rk.com>", "References": "<1533574847-19294-1-git-send-email-aleksandar.markovic@rt-rk.com>", "X-detected-operating-system": "by eggs.gnu.org: GNU/Linux 3.x [fuzzy]", "X-Received-From": "89.216.37.149", "Subject": "[Qemu-devel] [PATCH v7 30/80] target/mips: Add emulation of misc\n\tnanoMIPS instructions (pool32a0)", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, thuth@redhat.com, pburton@wavecomp.com,\n\tsmarkovic@wavecomp.com, riku.voipio@iki.fi,\n\trichard.henderson@linaro.org, laurent@vivier.eu,\n\tarmbru@redhat.com, arikalo@wavecomp.com,\n\tphilippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com,\n\tpjovanovic@wavecomp.com, aurelien@aurel32.net", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Yongbok Kim <yongbok.kim@mips.com>\n\nAdd emulation of nanoMIPS instructions that are situated in pool32a0.\n\nReviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>\nSigned-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>\nSigned-off-by: Stefan Markovic <smarkovic@wavecomp.com>\n---\n target/mips/translate.c | 185 ++++++++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 185 insertions(+)", "diff": "diff --git a/target/mips/translate.c b/target/mips/translate.c\nindex 072e124..6ef5e2e 100644\n--- a/target/mips/translate.c\n+++ b/target/mips/translate.c\n@@ -16670,6 +16670,181 @@ static void gen_pool16c_nanomips_insn(DisasContext *ctx)\n }\n }\n \n+static void gen_pool32a0_nanomips_insn(DisasContext *ctx)\n+{\n+ int rt = extract32(ctx->opcode, 21, 5);\n+ int rs = extract32(ctx->opcode, 16, 5);\n+ int rd = extract32(ctx->opcode, 11, 5);\n+\n+ switch (extract32(ctx->opcode, 3, 7)) {\n+ case NM_P_TRAP:\n+ switch (extract32(ctx->opcode, 10, 1)) {\n+ case NM_TEQ:\n+ gen_trap(ctx, OPC_TEQ, rs, rt, -1);\n+ break;\n+ case NM_TNE:\n+ gen_trap(ctx, OPC_TNE, rs, rt, -1);\n+ break;\n+ }\n+ break;\n+ case NM_RDHWR:\n+ gen_rdhwr(ctx, rt, rs, extract32(ctx->opcode, 11, 3));\n+ break;\n+ case NM_SEB:\n+ gen_bshfl(ctx, OPC_SEB, rs, rt);\n+ break;\n+ case NM_SEH:\n+ gen_bshfl(ctx, OPC_SEH, rs, rt);\n+ break;\n+ case NM_SLLV:\n+ gen_shift(ctx, OPC_SLLV, rd, rt, rs);\n+ break;\n+ case NM_SRLV:\n+ gen_shift(ctx, OPC_SRLV, rd, rt, rs);\n+ break;\n+ case NM_SRAV:\n+ gen_shift(ctx, OPC_SRAV, rd, rt, rs);\n+ break;\n+ case NM_ROTRV:\n+ gen_shift(ctx, OPC_ROTRV, rd, rt, rs);\n+ break;\n+ case NM_ADD:\n+ gen_arith(ctx, OPC_ADD, rd, rs, rt);\n+ break;\n+ case NM_ADDU:\n+ gen_arith(ctx, OPC_ADDU, rd, rs, rt);\n+ break;\n+ case NM_SUB:\n+ gen_arith(ctx, OPC_SUB, rd, rs, rt);\n+ break;\n+ case NM_SUBU:\n+ gen_arith(ctx, OPC_SUBU, rd, rs, rt);\n+ break;\n+ case NM_P_CMOVE:\n+ switch (extract32(ctx->opcode, 10, 1)) {\n+ case NM_MOVZ:\n+ gen_cond_move(ctx, OPC_MOVZ, rd, rs, rt);\n+ break;\n+ case NM_MOVN:\n+ gen_cond_move(ctx, OPC_MOVN, rd, rs, rt);\n+ break;\n+ }\n+ break;\n+ case NM_AND:\n+ gen_logic(ctx, OPC_AND, rd, rs, rt);\n+ break;\n+ case NM_OR:\n+ gen_logic(ctx, OPC_OR, rd, rs, rt);\n+ break;\n+ case NM_NOR:\n+ gen_logic(ctx, OPC_NOR, rd, rs, rt);\n+ break;\n+ case NM_XOR:\n+ gen_logic(ctx, OPC_XOR, rd, rs, rt);\n+ break;\n+ case NM_SLT:\n+ gen_slt(ctx, OPC_SLT, rd, rs, rt);\n+ break;\n+ case NM_P_SLTU:\n+ if (rd == 0) {\n+ /* P_DVP */\n+#ifndef CONFIG_USER_ONLY\n+ TCGv t0 = tcg_temp_new();\n+ switch (extract32(ctx->opcode, 10, 1)) {\n+ case NM_DVP:\n+ if (ctx->vp) {\n+ check_cp0_enabled(ctx);\n+ gen_helper_dvp(t0, cpu_env);\n+ gen_store_gpr(t0, rt);\n+ }\n+ break;\n+ case NM_EVP:\n+ if (ctx->vp) {\n+ check_cp0_enabled(ctx);\n+ gen_helper_evp(t0, cpu_env);\n+ gen_store_gpr(t0, rt);\n+ }\n+ break;\n+ }\n+ tcg_temp_free(t0);\n+#endif\n+ } else {\n+ gen_slt(ctx, OPC_SLTU, rd, rs, rt);\n+ }\n+ break;\n+ case NM_SOV:\n+ {\n+ TCGv t0 = tcg_temp_new();\n+ TCGv t1 = tcg_temp_new();\n+ TCGv t2 = tcg_temp_new();\n+\n+ gen_load_gpr(t1, rs);\n+ gen_load_gpr(t2, rt);\n+ tcg_gen_add_tl(t0, t1, t2);\n+ tcg_gen_ext32s_tl(t0, t0);\n+ tcg_gen_xor_tl(t1, t1, t2);\n+ tcg_gen_xor_tl(t2, t0, t2);\n+ tcg_gen_andc_tl(t1, t2, t1);\n+\n+ /* operands of same sign, result different sign */\n+ tcg_gen_setcondi_tl(TCG_COND_LT, t0, t1, 0);\n+ gen_store_gpr(t0, rd);\n+\n+ tcg_temp_free(t0);\n+ tcg_temp_free(t1);\n+ tcg_temp_free(t2);\n+ }\n+ break;\n+ case NM_MUL:\n+ gen_r6_muldiv(ctx, R6_OPC_MUL, rd, rs, rt);\n+ break;\n+ case NM_MUH:\n+ gen_r6_muldiv(ctx, R6_OPC_MUH, rd, rs, rt);\n+ break;\n+ case NM_MULU:\n+ gen_r6_muldiv(ctx, R6_OPC_MULU, rd, rs, rt);\n+ break;\n+ case NM_MUHU:\n+ gen_r6_muldiv(ctx, R6_OPC_MUHU, rd, rs, rt);\n+ break;\n+ case NM_DIV:\n+ gen_r6_muldiv(ctx, R6_OPC_DIV, rd, rs, rt);\n+ break;\n+ case NM_MOD:\n+ gen_r6_muldiv(ctx, R6_OPC_MOD, rd, rs, rt);\n+ break;\n+ case NM_DIVU:\n+ gen_r6_muldiv(ctx, R6_OPC_DIVU, rd, rs, rt);\n+ break;\n+ case NM_MODU:\n+ gen_r6_muldiv(ctx, R6_OPC_MODU, rd, rs, rt);\n+ break;\n+#ifndef CONFIG_USER_ONLY\n+ case NM_MFC0:\n+ check_cp0_enabled(ctx);\n+ if (rt == 0) {\n+ /* Treat as NOP. */\n+ break;\n+ }\n+ gen_mfc0(ctx, cpu_gpr[rt], rs, extract32(ctx->opcode, 11, 3));\n+ break;\n+ case NM_MTC0:\n+ check_cp0_enabled(ctx);\n+ {\n+ TCGv t0 = tcg_temp_new();\n+\n+ gen_load_gpr(t0, rt);\n+ gen_mtc0(ctx, t0, rs, extract32(ctx->opcode, 11, 3));\n+ tcg_temp_free(t0);\n+ }\n+ break;\n+#endif\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n+}\n+\n static void gen_pool32f_nanomips_insn(DisasContext *ctx)\n {\n int rt, rs, rd;\n@@ -17034,6 +17209,16 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)\n }\n break;\n case NM_POOL32A:\n+ switch (ctx->opcode & 0x07) {\n+ case NM_POOL32A0:\n+ gen_pool32a0_nanomips_insn(ctx);\n+ break;\n+ case NM_POOL32A7:\n+ break;\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n break;\n case NM_P_GP_W:\n switch (ctx->opcode & 0x03) {\n", "prefixes": [ "v7", "30/80" ] }