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GET /api/patches/954039/?format=api
{ "id": 954039, "url": "http://patchwork.ozlabs.org/api/patches/954039/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1533574847-19294-27-git-send-email-aleksandar.markovic@rt-rk.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1533574847-19294-27-git-send-email-aleksandar.markovic@rt-rk.com>", "list_archive_url": null, "date": "2018-08-06T16:59:53", "name": "[v7,26/80] target/mips: Add emulation of some common nanoMIPS 32-bit instructions", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "d226ddbdf540633e234d5d0183219bd998fe9fb7", "submitter": { "id": 68635, "url": "http://patchwork.ozlabs.org/api/people/68635/?format=api", "name": "Aleksandar Markovic", "email": "aleksandar.markovic@rt-rk.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1533574847-19294-27-git-send-email-aleksandar.markovic@rt-rk.com/mbox/", "series": [ { "id": 59520, "url": "http://patchwork.ozlabs.org/api/series/59520/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=59520", "date": "2018-08-06T16:59:27", "name": "Add nanoMIPS support to QEMU", "version": 7, "mbox": "http://patchwork.ozlabs.org/series/59520/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/954039/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/954039/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=none (p=none dis=none) header.from=rt-rk.com" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 41klFy3Z9Mz9s0R\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 7 Aug 2018 03:37:10 +1000 (AEST)", "from localhost ([::1]:35360 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1fmjRL-0000OU-PE\n\tfor incoming@patchwork.ozlabs.org; Mon, 06 Aug 2018 13:37:07 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:57659)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <aleksandar.markovic@rt-rk.com>) id 1fmj2K-0002EE-0f\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:11:17 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <aleksandar.markovic@rt-rk.com>) id 1fmj2H-0003gE-8L\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:11:15 -0400", "from mx2.rt-rk.com ([89.216.37.149]:47362 helo=mail.rt-rk.com)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <aleksandar.markovic@rt-rk.com>)\n\tid 1fmj2G-0003eS-ST\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:11:13 -0400", "from localhost (localhost [127.0.0.1])\n\tby mail.rt-rk.com (Postfix) with ESMTP id A9A4A1A212C;\n\tMon, 6 Aug 2018 19:11:11 +0200 (CEST)", "from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local\n\t[10.10.13.43])\n\tby mail.rt-rk.com (Postfix) with ESMTPSA id 81AF31A20DD;\n\tMon, 6 Aug 2018 19:11:11 +0200 (CEST)" ], "X-Virus-Scanned": "amavisd-new at rt-rk.com", "From": "Aleksandar Markovic <aleksandar.markovic@rt-rk.com>", "To": "qemu-devel@nongnu.org", "Date": "Mon, 6 Aug 2018 18:59:53 +0200", "Message-Id": "<1533574847-19294-27-git-send-email-aleksandar.markovic@rt-rk.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1533574847-19294-1-git-send-email-aleksandar.markovic@rt-rk.com>", "References": "<1533574847-19294-1-git-send-email-aleksandar.markovic@rt-rk.com>", "X-detected-operating-system": "by eggs.gnu.org: GNU/Linux 3.x [fuzzy]", "X-Received-From": "89.216.37.149", "Subject": "[Qemu-devel] [PATCH v7 26/80] target/mips: Add emulation of some\n\tcommon nanoMIPS 32-bit instructions", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, thuth@redhat.com, pburton@wavecomp.com,\n\tsmarkovic@wavecomp.com, riku.voipio@iki.fi,\n\trichard.henderson@linaro.org, laurent@vivier.eu,\n\tarmbru@redhat.com, arikalo@wavecomp.com,\n\tphilippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com,\n\tpjovanovic@wavecomp.com, aurelien@aurel32.net", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Yongbok Kim <yongbok.kim@mips.com>\n\nAdd emulation of SIGRIE, SYSCALL, BREAK, SDBBP, ADDIU, ADDIUPC,\nADDIUGP.W, LWGP, SWGP, ORI, XORI, ANDI, and other instructions.\n\nReviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>\nSigned-off-by: Yongbok Kim <yongbok.kim@mips.com>\nSigned-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>\nSigned-off-by: Stefan Markovic <smarkovic@wavecomp.com>\n---\n target/mips/translate.c | 267 +++++++++++++++++++++++++++++++++++++++++++++++-\n 1 file changed, 266 insertions(+), 1 deletion(-)", "diff": "diff --git a/target/mips/translate.c b/target/mips/translate.c\nindex a688af4..587d19a 100644\n--- a/target/mips/translate.c\n+++ b/target/mips/translate.c\n@@ -16670,6 +16670,271 @@ static void gen_pool16c_nanomips_insn(DisasContext *ctx)\n }\n }\n \n+static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)\n+{\n+ uint16_t insn;\n+ uint32_t op;\n+ int rt, rs;\n+ int offset;\n+ int imm;\n+\n+ insn = cpu_lduw_code(env, ctx->base.pc_next + 2);\n+ ctx->opcode = (ctx->opcode << 16) | insn;\n+\n+ rt = extract32(ctx->opcode, 21, 5);\n+ rs = extract32(ctx->opcode, 16, 5);\n+\n+ op = extract32(ctx->opcode, 26, 6);\n+ switch (op) {\n+ case NM_P_ADDIU:\n+ if (rt == 0) {\n+ /* P.RI */\n+ switch (extract32(ctx->opcode, 19, 2)) {\n+ case NM_SIGRIE:\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ case NM_P_SYSCALL:\n+ if ((extract32(ctx->opcode, 18, 1)) == NM_SYSCALL) {\n+ generate_exception_end(ctx, EXCP_SYSCALL);\n+ } else {\n+ generate_exception_end(ctx, EXCP_RI);\n+ }\n+ break;\n+ case NM_BREAK:\n+ generate_exception_end(ctx, EXCP_BREAK);\n+ break;\n+ case NM_SDBBP:\n+ if (is_uhi(extract32(ctx->opcode, 0, 19))) {\n+ gen_helper_do_semihosting(cpu_env);\n+ } else {\n+ if (ctx->hflags & MIPS_HFLAG_SBRI) {\n+ generate_exception_end(ctx, EXCP_RI);\n+ } else {\n+ generate_exception_end(ctx, EXCP_DBp);\n+ }\n+ }\n+ break;\n+ }\n+ } else {\n+ imm = extract32(ctx->opcode, 0, 16);\n+ if (rs != 0) {\n+ tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], imm);\n+ tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);\n+ } else {\n+ tcg_gen_movi_tl(cpu_gpr[rt], imm);\n+ }\n+ }\n+ break;\n+ case NM_ADDIUPC:\n+ if (rt != 0) {\n+ offset = sextract32(ctx->opcode, 0, 1) << 21 |\n+ extract32(ctx->opcode, 1, 20) << 1;\n+ target_long addr = addr_add(ctx, ctx->base.pc_next + 4, offset);\n+ tcg_gen_movi_tl(cpu_gpr[rt], addr);\n+ }\n+ break;\n+ case NM_POOL32A:\n+ break;\n+ case NM_P_GP_W:\n+ switch (ctx->opcode & 0x03) {\n+ case NM_ADDIUGP_W:\n+ if (rt != 0) {\n+ offset = extract32(ctx->opcode, 0, 21);\n+ gen_op_addr_addi(ctx, cpu_gpr[rt], cpu_gpr[28], offset);\n+ }\n+ break;\n+ case NM_LWGP:\n+ gen_ld(ctx, OPC_LW, rt, 28, extract32(ctx->opcode, 2, 19) << 2);\n+ break;\n+ case NM_SWGP:\n+ gen_st(ctx, OPC_SW, rt, 28, extract32(ctx->opcode, 2, 19) << 2);\n+ break;\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n+ break;\n+ case NM_P48I:\n+ return 6;\n+ case NM_P_U12:\n+ switch (extract32(ctx->opcode, 12, 4)) {\n+ case NM_ORI:\n+ gen_logic_imm(ctx, OPC_ORI, rt, rs, extract32(ctx->opcode, 0, 12));\n+ break;\n+ case NM_XORI:\n+ gen_logic_imm(ctx, OPC_XORI, rt, rs, extract32(ctx->opcode, 0, 12));\n+ break;\n+ case NM_ANDI:\n+ gen_logic_imm(ctx, OPC_ANDI, rt, rs, extract32(ctx->opcode, 0, 12));\n+ break;\n+ case NM_P_SR:\n+ switch (extract32(ctx->opcode, 20, 1)) {\n+ case NM_PP_SR:\n+ switch (ctx->opcode & 3) {\n+ case NM_SAVE:\n+ gen_save(ctx, rt, extract32(ctx->opcode, 16, 4),\n+ extract32(ctx->opcode, 2, 1),\n+ extract32(ctx->opcode, 3, 9) << 3);\n+ break;\n+ case NM_RESTORE:\n+ case NM_RESTORE_JRC:\n+ gen_restore(ctx, rt, extract32(ctx->opcode, 16, 4),\n+ extract32(ctx->opcode, 2, 1),\n+ extract32(ctx->opcode, 3, 9) << 3);\n+ if ((ctx->opcode & 3) == NM_RESTORE_JRC) {\n+ gen_compute_branch(ctx, OPC_JR, 2, 31, 0, 0, 0);\n+ }\n+ break;\n+ }\n+ break;\n+ case NM_P_SR_F:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n+ break;\n+ case NM_SLTI:\n+ gen_slt_imm(ctx, OPC_SLTI, rt, rs, extract32(ctx->opcode, 0, 12));\n+ break;\n+ case NM_SLTIU:\n+ gen_slt_imm(ctx, OPC_SLTIU, rt, rs, extract32(ctx->opcode, 0, 12));\n+ break;\n+ case NM_SEQI:\n+ {\n+ TCGv t0 = tcg_temp_new();\n+\n+ imm = extract32(ctx->opcode, 0, 12);\n+ gen_load_gpr(t0, rs);\n+ tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, imm);\n+ gen_store_gpr(t0, rt);\n+\n+ tcg_temp_free(t0);\n+ }\n+ break;\n+ case NM_ADDIUNEG:\n+ imm = (int16_t) extract32(ctx->opcode, 0, 12);\n+ gen_arith_imm(ctx, OPC_ADDIU, rt, rs, -imm);\n+ break;\n+ case NM_P_SHIFT:\n+ {\n+ int shift = extract32(ctx->opcode, 0, 5);\n+ switch (extract32(ctx->opcode, 5, 4)) {\n+ case NM_P_SLL:\n+ if (rt == 0 && shift == 0) {\n+ /* NOP */\n+ } else if (rt == 0 && shift == 3) {\n+ /* EHB treat as NOP */\n+ } else if (rt == 0 && shift == 5) {\n+ /* PAUSE */\n+ if (ctx->hflags & MIPS_HFLAG_BMASK) {\n+ generate_exception_end(ctx, EXCP_RI);\n+ }\n+ } else if (rt == 0 && shift == 6) {\n+ /* SYNC */\n+ gen_sync(extract32(ctx->opcode, 16, 5));\n+ } else {\n+ /* SLL */\n+ gen_shift_imm(ctx, OPC_SLL, rt, rs,\n+ extract32(ctx->opcode, 0, 5));\n+ }\n+ break;\n+ case NM_SRL:\n+ gen_shift_imm(ctx, OPC_SRL, rt, rs,\n+ extract32(ctx->opcode, 0, 5));\n+ break;\n+ case NM_SRA:\n+ gen_shift_imm(ctx, OPC_SRA, rt, rs,\n+ extract32(ctx->opcode, 0, 5));\n+ break;\n+ case NM_ROTR:\n+ gen_shift_imm(ctx, OPC_ROTR, rt, rs,\n+ extract32(ctx->opcode, 0, 5));\n+ break;\n+ }\n+ }\n+ break;\n+ case NM_P_ROTX:\n+ break;\n+ case NM_P_INS:\n+ switch (((ctx->opcode >> 10) & 2) |\n+ (extract32(ctx->opcode, 5, 1))) {\n+ case NM_INS:\n+ gen_bitops(ctx, OPC_INS, rt, rs, extract32(ctx->opcode, 0, 5),\n+ extract32(ctx->opcode, 6, 5));\n+ break;\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n+ break;\n+ case NM_P_EXT:\n+ switch (((ctx->opcode >> 10) & 2) |\n+ (extract32(ctx->opcode, 5, 1))) {\n+ case NM_EXT:\n+ gen_bitops(ctx, OPC_EXT, rt, rs, extract32(ctx->opcode, 0, 5),\n+ extract32(ctx->opcode, 6, 5));\n+ break;\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n+ break;\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n+ break;\n+ case NM_POOL32F:\n+ break;\n+ case NM_POOL32S:\n+ break;\n+ case NM_P_LUI:\n+ switch (extract32(ctx->opcode, 1, 1)) {\n+ case NM_LUI:\n+ if (rt != 0) {\n+ tcg_gen_movi_tl(cpu_gpr[rt],\n+ sextract32(ctx->opcode, 0, 1) << 31 |\n+ extract32(ctx->opcode, 2, 10) << 21 |\n+ extract32(ctx->opcode, 12, 9) << 12);\n+ }\n+ break;\n+ case NM_ALUIPC:\n+ if (rt != 0) {\n+ offset = sextract32(ctx->opcode, 0, 1) << 31 |\n+ extract32(ctx->opcode, 2, 10) << 21 |\n+ extract32(ctx->opcode, 12, 9) << 12;\n+ target_long addr;\n+ addr = ~0xFFF & addr_add(ctx, ctx->base.pc_next + 4, offset);\n+ tcg_gen_movi_tl(cpu_gpr[rt], addr);\n+ }\n+ break;\n+ }\n+ break;\n+ case NM_P_GP_BH:\n+ break;\n+ case NM_P_LS_U12:\n+ break;\n+ case NM_P_LS_S9:\n+ break;\n+ case NM_MOVE_BALC:\n+ break;\n+ case NM_P_BAL:\n+ break;\n+ case NM_P_J:\n+ break;\n+ case NM_P_BR1:\n+ break;\n+ case NM_P_BR2:\n+ break;\n+ case NM_P_BRI:\n+ break;\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n+ return 4;\n+}\n+\n static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)\n {\n uint32_t op;\n@@ -16989,7 +17254,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)\n case NM_MOVEPREV:\n break;\n default:\n- break;\n+ return decode_nanomips_32_48_opc(env, ctx);\n }\n \n return 2;\n", "prefixes": [ "v7", "26/80" ] }