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GET /api/patches/954029/?format=api
{ "id": 954029, "url": "http://patchwork.ozlabs.org/api/patches/954029/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1533574847-19294-43-git-send-email-aleksandar.markovic@rt-rk.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1533574847-19294-43-git-send-email-aleksandar.markovic@rt-rk.com>", "list_archive_url": null, "date": "2018-08-06T17:00:09", "name": "[v7,42/80] target/mips: Add emulation of DSP ASE for nanoMIPS - part 4", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "60834e3ff8f9ba7991eadbae0454e30ab850b7bb", "submitter": { "id": 68635, "url": "http://patchwork.ozlabs.org/api/people/68635/?format=api", "name": "Aleksandar Markovic", "email": "aleksandar.markovic@rt-rk.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1533574847-19294-43-git-send-email-aleksandar.markovic@rt-rk.com/mbox/", "series": [ { "id": 59520, "url": "http://patchwork.ozlabs.org/api/series/59520/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=59520", "date": "2018-08-06T16:59:27", "name": "Add nanoMIPS support to QEMU", "version": 7, "mbox": "http://patchwork.ozlabs.org/series/59520/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/954029/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/954029/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=none (p=none dis=none) header.from=rt-rk.com" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 41kl3l27lMz9ryt\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 7 Aug 2018 03:28:19 +1000 (AEST)", "from localhost ([::1]:35309 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1fmjIm-0000ls-Td\n\tfor incoming@patchwork.ozlabs.org; Mon, 06 Aug 2018 13:28:16 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:34983)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <aleksandar.markovic@rt-rk.com>) id 1fmj93-000099-1E\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:18:14 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <aleksandar.markovic@rt-rk.com>) id 1fmj91-0001cy-BR\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:18:12 -0400", "from mx2.rt-rk.com ([89.216.37.149]:58499 helo=mail.rt-rk.com)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <aleksandar.markovic@rt-rk.com>)\n\tid 1fmj90-0001YE-V3\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:18:11 -0400", "from localhost (localhost [127.0.0.1])\n\tby mail.rt-rk.com (Postfix) with ESMTP id B4CFA1A20AF;\n\tMon, 6 Aug 2018 19:18:09 +0200 (CEST)", "from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local\n\t[10.10.13.43])\n\tby mail.rt-rk.com (Postfix) with ESMTPSA id 8A1D41A2036;\n\tMon, 6 Aug 2018 19:18:09 +0200 (CEST)" ], "X-Virus-Scanned": "amavisd-new at rt-rk.com", "From": "Aleksandar Markovic <aleksandar.markovic@rt-rk.com>", "To": "qemu-devel@nongnu.org", "Date": "Mon, 6 Aug 2018 19:00:09 +0200", "Message-Id": "<1533574847-19294-43-git-send-email-aleksandar.markovic@rt-rk.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1533574847-19294-1-git-send-email-aleksandar.markovic@rt-rk.com>", "References": "<1533574847-19294-1-git-send-email-aleksandar.markovic@rt-rk.com>", "X-detected-operating-system": "by eggs.gnu.org: GNU/Linux 3.x [fuzzy]", "X-Received-From": "89.216.37.149", "Subject": "[Qemu-devel] [PATCH v7 42/80] target/mips: Add emulation of DSP ASE\n\tfor nanoMIPS - part 4", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, thuth@redhat.com, pburton@wavecomp.com,\n\tsmarkovic@wavecomp.com, riku.voipio@iki.fi,\n\trichard.henderson@linaro.org, laurent@vivier.eu,\n\tarmbru@redhat.com, arikalo@wavecomp.com,\n\tphilippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com,\n\tpjovanovic@wavecomp.com, aurelien@aurel32.net", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Stefan Markovic <smarkovic@wavecomp.com>\n\nAdd emulation of DSP ASE instructions for nanoMIPS - part 4.\n\nSigned-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>\nSigned-off-by: Stefan Markovic <smarkovic@wavecomp.com>\n---\n target/mips/translate.c | 378 ++++++++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 378 insertions(+)", "diff": "diff --git a/target/mips/translate.c b/target/mips/translate.c\nindex 8c33d14..9c8d1f4 100644\n--- a/target/mips/translate.c\n+++ b/target/mips/translate.c\n@@ -17202,6 +17202,380 @@ static void gen_pool32axf_1_nanomips_insn(DisasContext *ctx, uint32_t opc,\n tcg_temp_free(v0_t);\n }\n \n+static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc,\n+ TCGv v0, TCGv v1, int rd)\n+{\n+ TCGv_i32 t0;\n+\n+ t0 = tcg_temp_new_i32();\n+\n+ tcg_gen_movi_i32(t0, rd >> 3);\n+\n+ switch (opc) {\n+ case NM_POOL32AXF_2_0_7:\n+ switch (extract32(ctx->opcode, 9, 3)) {\n+ case NM_DPA_W_PH:\n+ check_dspr2(ctx);\n+ gen_helper_dpa_w_ph(t0, v1, v0, cpu_env);\n+ break;\n+ case NM_DPAQ_S_W_PH:\n+ check_dsp(ctx);\n+ gen_helper_dpaq_s_w_ph(t0, v1, v0, cpu_env);\n+ break;\n+ case NM_DPS_W_PH:\n+ check_dspr2(ctx);\n+ gen_helper_dps_w_ph(t0, v1, v0, cpu_env);\n+ break;\n+ case NM_DPSQ_S_W_PH:\n+ check_dsp(ctx);\n+ gen_helper_dpsq_s_w_ph(t0, v1, v0, cpu_env);\n+ break;\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n+ break;\n+ case NM_POOL32AXF_2_8_15:\n+ switch (extract32(ctx->opcode, 9, 3)) {\n+ case NM_DPAX_W_PH:\n+ check_dspr2(ctx);\n+ gen_helper_dpax_w_ph(t0, v0, v1, cpu_env);\n+ break;\n+ case NM_DPAQ_SA_L_W:\n+ check_dsp(ctx);\n+ gen_helper_dpaq_sa_l_w(t0, v0, v1, cpu_env);\n+ break;\n+ case NM_DPSX_W_PH:\n+ check_dspr2(ctx);\n+ gen_helper_dpsx_w_ph(t0, v0, v1, cpu_env);\n+ break;\n+ case NM_DPSQ_SA_L_W:\n+ check_dsp(ctx);\n+ gen_helper_dpsq_sa_l_w(t0, v0, v1, cpu_env);\n+ break;\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n+ break;\n+ case NM_POOL32AXF_2_16_23:\n+ switch (extract32(ctx->opcode, 9, 3)) {\n+ case NM_DPAU_H_QBL:\n+ check_dsp(ctx);\n+ gen_helper_dpau_h_qbl(t0, v0, v1, cpu_env);\n+ break;\n+ case NM_DPAQX_S_W_PH:\n+ check_dspr2(ctx);\n+ gen_helper_dpaqx_s_w_ph(t0, v0, v1, cpu_env);\n+ break;\n+ case NM_DPSU_H_QBL:\n+ check_dsp(ctx);\n+ gen_helper_dpsu_h_qbl(t0, v0, v1, cpu_env);\n+ break;\n+ case NM_DPSQX_S_W_PH:\n+ check_dspr2(ctx);\n+ gen_helper_dpsqx_s_w_ph(t0, v0, v1, cpu_env);\n+ break;\n+ case NM_MULSA_W_PH:\n+ check_dspr2(ctx);\n+ gen_helper_mulsa_w_ph(t0, v0, v1, cpu_env);\n+ break;\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n+ break;\n+ case NM_POOL32AXF_2_24_31:\n+ switch (extract32(ctx->opcode, 9, 3)) {\n+ case NM_DPAU_H_QBR:\n+ check_dsp(ctx);\n+ gen_helper_dpau_h_qbr(t0, v1, v0, cpu_env);\n+ break;\n+ case NM_DPAQX_SA_W_PH:\n+ check_dspr2(ctx);\n+ gen_helper_dpaqx_sa_w_ph(t0, v1, v0, cpu_env);\n+ break;\n+ case NM_DPSU_H_QBR:\n+ check_dsp(ctx);\n+ gen_helper_dpsu_h_qbr(t0, v1, v0, cpu_env);\n+ break;\n+ case NM_DPSQX_SA_W_PH:\n+ check_dspr2(ctx);\n+ gen_helper_dpsqx_sa_w_ph(t0, v1, v0, cpu_env);\n+ break;\n+ case NM_MULSAQ_S_W_PH:\n+ check_dsp(ctx);\n+ gen_helper_mulsaq_s_w_ph(t0, v1, v0, cpu_env);\n+ break;\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n+ break;\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n+\n+ tcg_temp_free_i32(t0);\n+}\n+\n+static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,\n+ int rt, int rs, int rd)\n+{\n+ int ret = rt;\n+\n+ TCGv t0;\n+ TCGv t1;\n+\n+ TCGv v0_t;\n+ TCGv v1_t;\n+\n+ t0 = tcg_temp_new();\n+ t1 = tcg_temp_new();\n+\n+ v0_t = tcg_temp_new();\n+ v1_t = tcg_temp_new();\n+\n+ gen_load_gpr(v0_t, rt);\n+ gen_load_gpr(v1_t, rs);\n+\n+ switch (opc) {\n+ case NM_POOL32AXF_2_0_7:\n+ switch (extract32(ctx->opcode, 9, 3)) {\n+ case NM_DPA_W_PH:\n+ case NM_DPAQ_S_W_PH:\n+ case NM_DPS_W_PH:\n+ case NM_DPSQ_S_W_PH:\n+ gen_pool32axf_2_multiply(ctx, opc, v0_t, v1_t, rd);\n+ break;\n+ case NM_BALIGN:\n+ check_dspr2(ctx);\n+ if (rt != 0) {\n+ gen_load_gpr(t0, rs);\n+ rd &= 3;\n+ if (rd != 0 && rd != 2) {\n+ tcg_gen_shli_tl(cpu_gpr[ret], cpu_gpr[ret], 8 * rd);\n+ tcg_gen_ext32u_tl(t0, t0);\n+ tcg_gen_shri_tl(t0, t0, 8 * (4 - rd));\n+ tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);\n+ }\n+ tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]);\n+ }\n+ break;\n+ case NM_MADD:\n+ {\n+ int acc = extract32(ctx->opcode, 14, 2);\n+\n+ gen_load_gpr(t0, rt);\n+ gen_load_gpr(t1, rs);\n+ TCGv_i64 t2 = tcg_temp_new_i64();\n+ TCGv_i64 t3 = tcg_temp_new_i64();\n+\n+ check_dsp(ctx);\n+ tcg_gen_ext_tl_i64(t2, t0);\n+ tcg_gen_ext_tl_i64(t3, t1);\n+ tcg_gen_mul_i64(t2, t2, t3);\n+ tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);\n+ tcg_gen_add_i64(t2, t2, t3);\n+ tcg_temp_free_i64(t3);\n+ gen_move_low32(cpu_LO[acc], t2);\n+ gen_move_high32(cpu_HI[acc], t2);\n+ tcg_temp_free_i64(t2);\n+ }\n+ break;\n+ case NM_MULT:\n+ {\n+ int acc = extract32(ctx->opcode, 14, 2);\n+\n+ gen_load_gpr(t0, rs);\n+ gen_load_gpr(t1, rt);\n+\n+ TCGv_i32 t2 = tcg_temp_new_i32();\n+ TCGv_i32 t3 = tcg_temp_new_i32();\n+ check_dsp(ctx);\n+ tcg_gen_trunc_tl_i32(t2, t0);\n+ tcg_gen_trunc_tl_i32(t3, t1);\n+ tcg_gen_muls2_i32(t2, t3, t2, t3);\n+ tcg_gen_ext_i32_tl(cpu_LO[acc], t2);\n+ tcg_gen_ext_i32_tl(cpu_HI[acc], t3);\n+ tcg_temp_free_i32(t2);\n+ tcg_temp_free_i32(t3);\n+ }\n+ break;\n+ case NM_EXTRV_W:\n+ check_dsp(ctx);\n+ gen_load_gpr(v1_t, rs);\n+ tcg_gen_movi_tl(t0, rd >> 3);\n+ gen_helper_extr_w(t0, t0, v1_t, cpu_env);\n+ gen_store_gpr(t0, ret);\n+ break;\n+ }\n+ break;\n+ case NM_POOL32AXF_2_8_15:\n+ switch (extract32(ctx->opcode, 9, 3)) {\n+ case NM_DPAX_W_PH:\n+ case NM_DPAQ_SA_L_W:\n+ case NM_DPSX_W_PH:\n+ case NM_DPSQ_SA_L_W:\n+ gen_pool32axf_2_multiply(ctx, opc, v0_t, v1_t, rd);\n+ break;\n+ case NM_MADDU:\n+ {\n+ int acc = extract32(ctx->opcode, 14, 2);\n+\n+ TCGv_i64 t2 = tcg_temp_new_i64();\n+ TCGv_i64 t3 = tcg_temp_new_i64();\n+\n+ gen_load_gpr(t0, rs);\n+ gen_load_gpr(t1, rt);\n+\n+ check_dsp(ctx);\n+ tcg_gen_ext32u_tl(t0, t0);\n+ tcg_gen_ext32u_tl(t1, t1);\n+ tcg_gen_extu_tl_i64(t2, t0);\n+ tcg_gen_extu_tl_i64(t3, t1);\n+ tcg_gen_mul_i64(t2, t2, t3);\n+ tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);\n+ tcg_gen_add_i64(t2, t2, t3);\n+ tcg_temp_free_i64(t3);\n+ gen_move_low32(cpu_LO[acc], t2);\n+ gen_move_high32(cpu_HI[acc], t2);\n+ tcg_temp_free_i64(t2);\n+ }\n+ break;\n+ case NM_MULTU:\n+ {\n+ int acc = extract32(ctx->opcode, 14, 2);\n+\n+ TCGv_i32 t2 = tcg_temp_new_i32();\n+ TCGv_i32 t3 = tcg_temp_new_i32();\n+\n+ gen_load_gpr(t0, rs);\n+ gen_load_gpr(t1, rt);\n+\n+ check_dsp(ctx);\n+ tcg_gen_trunc_tl_i32(t2, t0);\n+ tcg_gen_trunc_tl_i32(t3, t1);\n+ tcg_gen_mulu2_i32(t2, t3, t2, t3);\n+ tcg_gen_ext_i32_tl(cpu_LO[acc], t2);\n+ tcg_gen_ext_i32_tl(cpu_HI[acc], t3);\n+ tcg_temp_free_i32(t2);\n+ tcg_temp_free_i32(t3);\n+ }\n+ break;\n+ case NM_EXTRV_R_W:\n+ check_dsp(ctx);\n+ tcg_gen_movi_tl(t0, rd >> 3);\n+ gen_helper_extr_r_w(t0, t0, v1_t, cpu_env);\n+ gen_store_gpr(t0, ret);\n+ break;\n+ }\n+ break;\n+ case NM_POOL32AXF_2_16_23:\n+ switch (extract32(ctx->opcode, 9, 3)) {\n+ case NM_DPAU_H_QBL:\n+ case NM_DPAQX_S_W_PH:\n+ case NM_DPSU_H_QBL:\n+ case NM_DPSQX_S_W_PH:\n+ case NM_MULSA_W_PH:\n+ gen_pool32axf_2_multiply(ctx, opc, v0_t, v1_t, rd);\n+ break;\n+ case NM_EXTPV:\n+ check_dsp(ctx);\n+ tcg_gen_movi_tl(t0, rd >> 3);\n+ gen_helper_extp(t0, t0, v1_t, cpu_env);\n+ gen_store_gpr(t0, ret);\n+ break;\n+ case NM_MSUB:\n+ {\n+ int acc = extract32(ctx->opcode, 14, 2);\n+\n+ TCGv_i64 t2 = tcg_temp_new_i64();\n+ TCGv_i64 t3 = tcg_temp_new_i64();\n+\n+ gen_load_gpr(t0, rs);\n+ gen_load_gpr(t1, rt);\n+\n+ check_dsp(ctx);\n+ tcg_gen_ext_tl_i64(t2, t0);\n+ tcg_gen_ext_tl_i64(t3, t1);\n+ tcg_gen_mul_i64(t2, t2, t3);\n+ tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);\n+ tcg_gen_sub_i64(t2, t3, t2);\n+ tcg_temp_free_i64(t3);\n+ gen_move_low32(cpu_LO[acc], t2);\n+ gen_move_high32(cpu_HI[acc], t2);\n+ tcg_temp_free_i64(t2);\n+ }\n+ break;\n+ case NM_EXTRV_RS_W:\n+ check_dsp(ctx);\n+ tcg_gen_movi_tl(t0, rd >> 3);\n+ gen_helper_extr_rs_w(t0, t0, v1_t, cpu_env);\n+ gen_store_gpr(t0, ret);\n+ break;\n+ }\n+ break;\n+ case NM_POOL32AXF_2_24_31:\n+ switch (extract32(ctx->opcode, 9, 3)) {\n+ case NM_DPAU_H_QBR:\n+ case NM_DPAQX_SA_W_PH:\n+ case NM_DPSU_H_QBR:\n+ case NM_DPSQX_SA_W_PH:\n+ case NM_MULSAQ_S_W_PH:\n+ gen_pool32axf_2_multiply(ctx, opc, v0_t, v1_t, rd);\n+ break;\n+ case NM_EXTPDPV:\n+ check_dsp(ctx);\n+ tcg_gen_movi_tl(t0, rd >> 3);\n+ gen_helper_extpdp(t0, t0, v1_t, cpu_env);\n+ gen_store_gpr(t0, ret);\n+ break;\n+ case NM_MSUBU:\n+ {\n+ int acc = extract32(ctx->opcode, 14, 2);\n+\n+ TCGv_i64 t2 = tcg_temp_new_i64();\n+ TCGv_i64 t3 = tcg_temp_new_i64();\n+\n+ gen_load_gpr(t0, rs);\n+ gen_load_gpr(t1, rt);\n+\n+ check_dsp(ctx);\n+ tcg_gen_ext32u_tl(t0, t0);\n+ tcg_gen_ext32u_tl(t1, t1);\n+ tcg_gen_extu_tl_i64(t2, t0);\n+ tcg_gen_extu_tl_i64(t3, t1);\n+ tcg_gen_mul_i64(t2, t2, t3);\n+ tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);\n+ tcg_gen_sub_i64(t2, t3, t2);\n+ tcg_temp_free_i64(t3);\n+ gen_move_low32(cpu_LO[acc], t2);\n+ gen_move_high32(cpu_HI[acc], t2);\n+ tcg_temp_free_i64(t2);\n+ }\n+ break;\n+ case NM_EXTRV_S_H:\n+ check_dsp(ctx);\n+ tcg_gen_movi_tl(t0, rd >> 3);\n+ gen_helper_extr_s_h(t0, t0, v0_t, cpu_env);\n+ gen_store_gpr(t0, ret);\n+ break;\n+ }\n+ break;\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n+\n+ tcg_temp_free(t0);\n+ tcg_temp_free(t1);\n+\n+ tcg_temp_free(v0_t);\n+ tcg_temp_free(v1_t);\n+}\n+\n \n static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)\n {\n@@ -17217,6 +17591,10 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)\n }\n break;\n case NM_POOL32AXF_2:\n+ {\n+ int32_t op1 = (ctx->opcode >> 12) & 0x03;\n+ gen_pool32axf_2_nanomips_insn(ctx, op1, rt, rs, rd);\n+ }\n break;\n case NM_POOL32AXF_4:\n break;\n", "prefixes": [ "v7", "42/80" ] }