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GET /api/patches/954027/?format=api
{ "id": 954027, "url": "http://patchwork.ozlabs.org/api/patches/954027/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1533574847-19294-30-git-send-email-aleksandar.markovic@rt-rk.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1533574847-19294-30-git-send-email-aleksandar.markovic@rt-rk.com>", "list_archive_url": null, "date": "2018-08-06T16:59:56", "name": "[v7,29/80] target/mips: Add emulation of nanoMIPS FP instructions", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "e6976ce0ddfeb5a8f1a4e598c117f536611d05cd", "submitter": { "id": 68635, "url": "http://patchwork.ozlabs.org/api/people/68635/?format=api", "name": "Aleksandar Markovic", "email": "aleksandar.markovic@rt-rk.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1533574847-19294-30-git-send-email-aleksandar.markovic@rt-rk.com/mbox/", "series": [ { "id": 59520, "url": "http://patchwork.ozlabs.org/api/series/59520/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=59520", "date": "2018-08-06T16:59:27", "name": "Add nanoMIPS support to QEMU", "version": 7, "mbox": "http://patchwork.ozlabs.org/series/59520/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/954027/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/954027/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=none (p=none dis=none) header.from=rt-rk.com" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 41kl114qhSz9ryt\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 7 Aug 2018 03:25:57 +1000 (AEST)", "from localhost ([::1]:35293 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1fmjGV-0006fW-C0\n\tfor incoming@patchwork.ozlabs.org; Mon, 06 Aug 2018 13:25:55 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:58502)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <aleksandar.markovic@rt-rk.com>) id 1fmj3b-0003Nh-Su\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:12:37 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <aleksandar.markovic@rt-rk.com>) id 1fmj3Z-0004g1-2s\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:12:35 -0400", "from mx2.rt-rk.com ([89.216.37.149]:48794 helo=mail.rt-rk.com)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <aleksandar.markovic@rt-rk.com>)\n\tid 1fmj3Y-0004eg-M2\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:12:32 -0400", "from localhost (localhost [127.0.0.1])\n\tby mail.rt-rk.com (Postfix) with ESMTP id 7283C1A20DD;\n\tMon, 6 Aug 2018 19:12:31 +0200 (CEST)", "from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local\n\t[10.10.13.43])\n\tby mail.rt-rk.com (Postfix) with ESMTPSA id 4AB661A20C6;\n\tMon, 6 Aug 2018 19:12:31 +0200 (CEST)" ], "X-Virus-Scanned": "amavisd-new at rt-rk.com", "From": "Aleksandar Markovic <aleksandar.markovic@rt-rk.com>", "To": "qemu-devel@nongnu.org", "Date": "Mon, 6 Aug 2018 18:59:56 +0200", "Message-Id": "<1533574847-19294-30-git-send-email-aleksandar.markovic@rt-rk.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1533574847-19294-1-git-send-email-aleksandar.markovic@rt-rk.com>", "References": "<1533574847-19294-1-git-send-email-aleksandar.markovic@rt-rk.com>", "X-detected-operating-system": "by eggs.gnu.org: GNU/Linux 3.x [fuzzy]", "X-Received-From": "89.216.37.149", "Subject": "[Qemu-devel] [PATCH v7 29/80] target/mips: Add emulation of\n\tnanoMIPS FP instructions", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, thuth@redhat.com, pburton@wavecomp.com,\n\tsmarkovic@wavecomp.com, riku.voipio@iki.fi,\n\trichard.henderson@linaro.org, laurent@vivier.eu,\n\tarmbru@redhat.com, arikalo@wavecomp.com,\n\tphilippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com,\n\tpjovanovic@wavecomp.com, aurelien@aurel32.net", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Yongbok Kim <yongbok.kim@mips.com>\n\nAdd emulation of basic floating point arithmetic for nanoMIPS.\n\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nReviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>\nSigned-off-by: Yongbok Kim <yongbok.kim@mips.com>\nSigned-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>\nSigned-off-by: Stefan Markovic <smarkovic@wavecomp.com>\n---\n target/mips/translate.c | 300 ++++++++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 300 insertions(+)", "diff": "diff --git a/target/mips/translate.c b/target/mips/translate.c\nindex 845b988..072e124 100644\n--- a/target/mips/translate.c\n+++ b/target/mips/translate.c\n@@ -16670,6 +16670,305 @@ static void gen_pool16c_nanomips_insn(DisasContext *ctx)\n }\n }\n \n+static void gen_pool32f_nanomips_insn(DisasContext *ctx)\n+{\n+ int rt, rs, rd;\n+\n+ rt = extract32(ctx->opcode, 21, 5);\n+ rs = extract32(ctx->opcode, 16, 5);\n+ rd = extract32(ctx->opcode, 11, 5);\n+\n+ if (!(ctx->CP0_Config1 & (1 << CP0C1_FP))) {\n+ generate_exception_end(ctx, EXCP_RI);\n+ return;\n+ }\n+ check_cp1_enabled(ctx);\n+ switch (extract32(ctx->opcode, 0, 3)) {\n+ case NM_POOL32F_0:\n+ switch (extract32(ctx->opcode, 3, 7)) {\n+ case NM_RINT_S:\n+ gen_farith(ctx, OPC_RINT_S, 0, rt, rs, 0);\n+ break;\n+ case NM_RINT_D:\n+ gen_farith(ctx, OPC_RINT_D, 0, rt, rs, 0);\n+ break;\n+ case NM_CLASS_S:\n+ gen_farith(ctx, OPC_CLASS_S, 0, rt, rs, 0);\n+ break;\n+ case NM_CLASS_D:\n+ gen_farith(ctx, OPC_CLASS_D, 0, rt, rs, 0);\n+ break;\n+ case NM_ADD_S:\n+ gen_farith(ctx, OPC_ADD_S, rt, rs, rd, 0);\n+ break;\n+ case NM_ADD_D:\n+ gen_farith(ctx, OPC_ADD_D, rt, rs, rd, 0);\n+ break;\n+ case NM_SUB_S:\n+ gen_farith(ctx, OPC_SUB_S, rt, rs, rd, 0);\n+ break;\n+ case NM_SUB_D:\n+ gen_farith(ctx, OPC_SUB_D, rt, rs, rd, 0);\n+ break;\n+ case NM_MUL_S:\n+ gen_farith(ctx, OPC_MUL_S, rt, rs, rd, 0);\n+ break;\n+ case NM_MUL_D:\n+ gen_farith(ctx, OPC_MUL_D, rt, rs, rd, 0);\n+ break;\n+ case NM_DIV_S:\n+ gen_farith(ctx, OPC_DIV_S, rt, rs, rd, 0);\n+ break;\n+ case NM_DIV_D:\n+ gen_farith(ctx, OPC_DIV_D, rt, rs, rd, 0);\n+ break;\n+ case NM_SELEQZ_S:\n+ gen_sel_s(ctx, OPC_SELEQZ_S, rd, rt, rs);\n+ break;\n+ case NM_SELEQZ_D:\n+ gen_sel_d(ctx, OPC_SELEQZ_D, rd, rt, rs);\n+ break;\n+ case NM_SELNEZ_S:\n+ gen_sel_s(ctx, OPC_SELNEZ_S, rd, rt, rs);\n+ break;\n+ case NM_SELNEZ_D:\n+ gen_sel_d(ctx, OPC_SELNEZ_D, rd, rt, rs);\n+ break;\n+ case NM_SEL_S:\n+ gen_sel_s(ctx, OPC_SEL_S, rd, rt, rs);\n+ break;\n+ case NM_SEL_D:\n+ gen_sel_d(ctx, OPC_SEL_D, rd, rt, rs);\n+ break;\n+ case NM_MADDF_S:\n+ gen_farith(ctx, OPC_MADDF_S, rt, rs, rd, 0);\n+ break;\n+ case NM_MADDF_D:\n+ gen_farith(ctx, OPC_MADDF_D, rt, rs, rd, 0);\n+ break;\n+ case NM_MSUBF_S:\n+ gen_farith(ctx, OPC_MSUBF_S, rt, rs, rd, 0);\n+ break;\n+ case NM_MSUBF_D:\n+ gen_farith(ctx, OPC_MSUBF_D, rt, rs, rd, 0);\n+ break;\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n+ break;\n+ case NM_POOL32F_3:\n+ switch (extract32(ctx->opcode, 3, 3)) {\n+ case NM_MIN_FMT:\n+ switch (extract32(ctx->opcode, 9, 1)) {\n+ case FMT_SDPS_S:\n+ gen_farith(ctx, OPC_MIN_S, rt, rs, rd, 0);\n+ break;\n+ case FMT_SDPS_D:\n+ gen_farith(ctx, OPC_MIN_D, rt, rs, rd, 0);\n+ break;\n+ }\n+ break;\n+ case NM_MAX_FMT:\n+ switch (extract32(ctx->opcode, 9, 1)) {\n+ case FMT_SDPS_S:\n+ gen_farith(ctx, OPC_MAX_S, rt, rs, rd, 0);\n+ break;\n+ case FMT_SDPS_D:\n+ gen_farith(ctx, OPC_MAX_D, rt, rs, rd, 0);\n+ break;\n+ }\n+ break;\n+ case NM_MINA_FMT:\n+ switch (extract32(ctx->opcode, 9, 1)) {\n+ case FMT_SDPS_S:\n+ gen_farith(ctx, OPC_MINA_S, rt, rs, rd, 0);\n+ break;\n+ case FMT_SDPS_D:\n+ gen_farith(ctx, OPC_MINA_D, rt, rs, rd, 0);\n+ break;\n+ }\n+ break;\n+ case NM_MAXA_FMT:\n+ switch (extract32(ctx->opcode, 9, 1)) {\n+ case FMT_SDPS_S:\n+ gen_farith(ctx, OPC_MAXA_S, rt, rs, rd, 0);\n+ break;\n+ case FMT_SDPS_D:\n+ gen_farith(ctx, OPC_MAXA_D, rt, rs, rd, 0);\n+ break;\n+ }\n+ break;\n+ case NM_POOL32FXF:\n+ switch (extract32(ctx->opcode, 6, 8)) {\n+ case NM_CFC1:\n+ gen_cp1(ctx, OPC_CFC1, rt, rs);\n+ break;\n+ case NM_CTC1:\n+ gen_cp1(ctx, OPC_CTC1, rt, rs);\n+ break;\n+ case NM_MFC1:\n+ gen_cp1(ctx, OPC_MFC1, rt, rs);\n+ break;\n+ case NM_MTC1:\n+ gen_cp1(ctx, OPC_MTC1, rt, rs);\n+ break;\n+ case NM_MFHC1:\n+ gen_cp1(ctx, OPC_MFHC1, rt, rs);\n+ break;\n+ case NM_MTHC1:\n+ gen_cp1(ctx, OPC_MTHC1, rt, rs);\n+ break;\n+ case NM_CVT_S_PL:\n+ gen_farith(ctx, OPC_CVT_S_PL, -1, rs, rt, 0);\n+ break;\n+ case NM_CVT_S_PU:\n+ gen_farith(ctx, OPC_CVT_S_PU, -1, rs, rt, 0);\n+ break;\n+ default:\n+ switch (extract32(ctx->opcode, 6, 9)) {\n+ case NM_CVT_L_S:\n+ gen_farith(ctx, OPC_CVT_L_S, -1, rs, rt, 0);\n+ break;\n+ case NM_CVT_L_D:\n+ gen_farith(ctx, OPC_CVT_L_D, -1, rs, rt, 0);\n+ break;\n+ case NM_CVT_W_S:\n+ gen_farith(ctx, OPC_CVT_W_S, -1, rs, rt, 0);\n+ break;\n+ case NM_CVT_W_D:\n+ gen_farith(ctx, OPC_CVT_W_D, -1, rs, rt, 0);\n+ break;\n+ case NM_RSQRT_S:\n+ gen_farith(ctx, OPC_RSQRT_S, -1, rs, rt, 0);\n+ break;\n+ case NM_RSQRT_D:\n+ gen_farith(ctx, OPC_RSQRT_D, -1, rs, rt, 0);\n+ break;\n+ case NM_SQRT_S:\n+ gen_farith(ctx, OPC_SQRT_S, -1, rs, rt, 0);\n+ break;\n+ case NM_SQRT_D:\n+ gen_farith(ctx, OPC_SQRT_D, -1, rs, rt, 0);\n+ break;\n+ case NM_RECIP_S:\n+ gen_farith(ctx, OPC_RECIP_S, -1, rs, rt, 0);\n+ break;\n+ case NM_RECIP_D:\n+ gen_farith(ctx, OPC_RECIP_D, -1, rs, rt, 0);\n+ break;\n+ case NM_FLOOR_L_S:\n+ gen_farith(ctx, OPC_FLOOR_L_S, -1, rs, rt, 0);\n+ break;\n+ case NM_FLOOR_L_D:\n+ gen_farith(ctx, OPC_FLOOR_L_D, -1, rs, rt, 0);\n+ break;\n+ case NM_FLOOR_W_S:\n+ gen_farith(ctx, OPC_FLOOR_W_S, -1, rs, rt, 0);\n+ break;\n+ case NM_FLOOR_W_D:\n+ gen_farith(ctx, OPC_FLOOR_W_D, -1, rs, rt, 0);\n+ break;\n+ case NM_CEIL_L_S:\n+ gen_farith(ctx, OPC_CEIL_L_S, -1, rs, rt, 0);\n+ break;\n+ case NM_CEIL_L_D:\n+ gen_farith(ctx, OPC_CEIL_L_D, -1, rs, rt, 0);\n+ break;\n+ case NM_CEIL_W_S:\n+ gen_farith(ctx, OPC_CEIL_W_S, -1, rs, rt, 0);\n+ break;\n+ case NM_CEIL_W_D:\n+ gen_farith(ctx, OPC_CEIL_W_D, -1, rs, rt, 0);\n+ break;\n+ case NM_TRUNC_L_S:\n+ gen_farith(ctx, OPC_TRUNC_L_S, -1, rs, rt, 0);\n+ break;\n+ case NM_TRUNC_L_D:\n+ gen_farith(ctx, OPC_TRUNC_L_D, -1, rs, rt, 0);\n+ break;\n+ case NM_TRUNC_W_S:\n+ gen_farith(ctx, OPC_TRUNC_W_S, -1, rs, rt, 0);\n+ break;\n+ case NM_TRUNC_W_D:\n+ gen_farith(ctx, OPC_TRUNC_W_D, -1, rs, rt, 0);\n+ break;\n+ case NM_ROUND_L_S:\n+ gen_farith(ctx, OPC_ROUND_L_S, -1, rs, rt, 0);\n+ break;\n+ case NM_ROUND_L_D:\n+ gen_farith(ctx, OPC_ROUND_L_D, -1, rs, rt, 0);\n+ break;\n+ case NM_ROUND_W_S:\n+ gen_farith(ctx, OPC_ROUND_W_S, -1, rs, rt, 0);\n+ break;\n+ case NM_ROUND_W_D:\n+ gen_farith(ctx, OPC_ROUND_W_D, -1, rs, rt, 0);\n+ break;\n+ case NM_MOV_S:\n+ gen_farith(ctx, OPC_MOV_S, -1, rs, rt, 0);\n+ break;\n+ case NM_MOV_D:\n+ gen_farith(ctx, OPC_MOV_D, -1, rs, rt, 0);\n+ break;\n+ case NM_ABS_S:\n+ gen_farith(ctx, OPC_ABS_S, -1, rs, rt, 0);\n+ break;\n+ case NM_ABS_D:\n+ gen_farith(ctx, OPC_ABS_D, -1, rs, rt, 0);\n+ break;\n+ case NM_NEG_S:\n+ gen_farith(ctx, OPC_NEG_S, -1, rs, rt, 0);\n+ break;\n+ case NM_NEG_D:\n+ gen_farith(ctx, OPC_NEG_D, -1, rs, rt, 0);\n+ break;\n+ case NM_CVT_D_S:\n+ gen_farith(ctx, OPC_CVT_D_S, -1, rs, rt, 0);\n+ break;\n+ case NM_CVT_D_W:\n+ gen_farith(ctx, OPC_CVT_D_W, -1, rs, rt, 0);\n+ break;\n+ case NM_CVT_D_L:\n+ gen_farith(ctx, OPC_CVT_D_L, -1, rs, rt, 0);\n+ break;\n+ case NM_CVT_S_D:\n+ gen_farith(ctx, OPC_CVT_S_D, -1, rs, rt, 0);\n+ break;\n+ case NM_CVT_S_W:\n+ gen_farith(ctx, OPC_CVT_S_W, -1, rs, rt, 0);\n+ break;\n+ case NM_CVT_S_L:\n+ gen_farith(ctx, OPC_CVT_S_L, -1, rs, rt, 0);\n+ break;\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n+ break;\n+ }\n+ break;\n+ }\n+ break;\n+ case NM_POOL32F_5:\n+ switch (extract32(ctx->opcode, 3, 3)) {\n+ case NM_CMP_CONDN_S:\n+ gen_r6_cmp_s(ctx, extract32(ctx->opcode, 6, 5), rt, rs, rd);\n+ break;\n+ case NM_CMP_CONDN_D:\n+ gen_r6_cmp_d(ctx, extract32(ctx->opcode, 6, 5), rt, rs, rd);\n+ break;\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n+ break;\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n+}\n+\n static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)\n {\n uint16_t insn;\n@@ -16949,6 +17248,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)\n }\n break;\n case NM_POOL32F:\n+ gen_pool32f_nanomips_insn(ctx);\n break;\n case NM_POOL32S:\n break;\n", "prefixes": [ "v7", "29/80" ] }