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GET /api/patches/954025/?format=api
{ "id": 954025, "url": "http://patchwork.ozlabs.org/api/patches/954025/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1533574847-19294-39-git-send-email-aleksandar.markovic@rt-rk.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1533574847-19294-39-git-send-email-aleksandar.markovic@rt-rk.com>", "list_archive_url": null, "date": "2018-08-06T17:00:05", "name": "[v7,38/80] target/mips: Implement MT ASE support for nanoMIPS", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "9ae68f5ca7bbdaf1bb6bc84a2e856450443cd0af", "submitter": { "id": 68635, "url": "http://patchwork.ozlabs.org/api/people/68635/?format=api", "name": "Aleksandar Markovic", "email": "aleksandar.markovic@rt-rk.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1533574847-19294-39-git-send-email-aleksandar.markovic@rt-rk.com/mbox/", "series": [ { "id": 59520, "url": "http://patchwork.ozlabs.org/api/series/59520/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=59520", "date": "2018-08-06T16:59:27", "name": "Add nanoMIPS support to QEMU", "version": 7, "mbox": "http://patchwork.ozlabs.org/series/59520/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/954025/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/954025/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=none (p=none dis=none) header.from=rt-rk.com" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 41kkzK5Vx7z9ryt\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 7 Aug 2018 03:24:29 +1000 (AEST)", "from localhost ([::1]:35284 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1fmjF5-0005BR-9b\n\tfor incoming@patchwork.ozlabs.org; Mon, 06 Aug 2018 13:24:27 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:33649)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <aleksandar.markovic@rt-rk.com>) id 1fmj79-00079f-Aw\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:16:16 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <aleksandar.markovic@rt-rk.com>) id 1fmj75-0007ym-2P\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:16:15 -0400", "from mx2.rt-rk.com ([89.216.37.149]:54203 helo=mail.rt-rk.com)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <aleksandar.markovic@rt-rk.com>)\n\tid 1fmj74-0007xb-NE\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:16:11 -0400", "from localhost (localhost [127.0.0.1])\n\tby mail.rt-rk.com (Postfix) with ESMTP id 7AA7E1A20B7;\n\tMon, 6 Aug 2018 19:16:09 +0200 (CEST)", "from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local\n\t[10.10.13.43])\n\tby mail.rt-rk.com (Postfix) with ESMTPSA id 57DAA1A2036;\n\tMon, 6 Aug 2018 19:16:09 +0200 (CEST)" ], "X-Virus-Scanned": "amavisd-new at rt-rk.com", "From": "Aleksandar Markovic <aleksandar.markovic@rt-rk.com>", "To": "qemu-devel@nongnu.org", "Date": "Mon, 6 Aug 2018 19:00:05 +0200", "Message-Id": "<1533574847-19294-39-git-send-email-aleksandar.markovic@rt-rk.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1533574847-19294-1-git-send-email-aleksandar.markovic@rt-rk.com>", "References": "<1533574847-19294-1-git-send-email-aleksandar.markovic@rt-rk.com>", "X-detected-operating-system": "by eggs.gnu.org: GNU/Linux 3.x [fuzzy]", "X-Received-From": "89.216.37.149", "Subject": "[Qemu-devel] [PATCH v7 38/80] target/mips: Implement MT ASE support\n\tfor nanoMIPS", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, thuth@redhat.com, pburton@wavecomp.com,\n\tsmarkovic@wavecomp.com, riku.voipio@iki.fi,\n\trichard.henderson@linaro.org, laurent@vivier.eu,\n\tarmbru@redhat.com, arikalo@wavecomp.com,\n\tphilippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com,\n\tpjovanovic@wavecomp.com, aurelien@aurel32.net", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Stefan Markovic <smarkovic@wavecomp.com>\n\nAdd emulation of MT ASE instructions for nanoMIPS.\n\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nSigned-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>\nSigned-off-by: Stefan Markovic <smarkovic@wavecomp.com>\n---\n target/mips/translate.c | 85 +++++++++++++++++++++++++++++++++++++++++++++++--\n 1 file changed, 83 insertions(+), 2 deletions(-)", "diff": "diff --git a/target/mips/translate.c b/target/mips/translate.c\nindex c1f80e7..441431d 100644\n--- a/target/mips/translate.c\n+++ b/target/mips/translate.c\n@@ -16757,7 +16757,7 @@ static void gen_pool16c_nanomips_insn(DisasContext *ctx)\n }\n }\n \n-static void gen_pool32a0_nanomips_insn(DisasContext *ctx)\n+static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)\n {\n int rt = extract32(ctx->opcode, 21, 5);\n int rs = extract32(ctx->opcode, 16, 5);\n@@ -16925,6 +16925,87 @@ static void gen_pool32a0_nanomips_insn(DisasContext *ctx)\n tcg_temp_free(t0);\n }\n break;\n+ case NM_D_E_MT_VPE:\n+ {\n+ uint8_t sc = extract32(ctx->opcode, 10, 1);\n+ TCGv t0 = tcg_temp_new();\n+\n+ switch (sc) {\n+ case 0:\n+ if (rs == 1) {\n+ /* DMT */\n+ check_insn(ctx, ASE_MT);\n+ gen_helper_dmt(t0);\n+ gen_store_gpr(t0, rt);\n+ } else if (rs == 0) {\n+ /* DVPE */\n+ check_insn(ctx, ASE_MT);\n+ gen_helper_dvpe(t0, cpu_env);\n+ gen_store_gpr(t0, rt);\n+ } else {\n+ generate_exception_end(ctx, EXCP_RI);\n+ }\n+ break;\n+ case 1:\n+ if (rs == 1) {\n+ /* EMT */\n+ check_insn(ctx, ASE_MT);\n+ gen_helper_emt(t0);\n+ gen_store_gpr(t0, rt);\n+ } else if (rs == 0) {\n+ /* EVPE */\n+ check_insn(ctx, ASE_MT);\n+ gen_helper_evpe(t0, cpu_env);\n+ gen_store_gpr(t0, rt);\n+ } else {\n+ generate_exception_end(ctx, EXCP_RI);\n+ }\n+ break;\n+ }\n+\n+ tcg_temp_free(t0);\n+ }\n+ break;\n+ case NM_FORK:\n+ check_insn(ctx, ASE_MT);\n+ {\n+ TCGv t0 = tcg_temp_new();\n+ TCGv t1 = tcg_temp_new();\n+\n+ gen_load_gpr(t0, rt);\n+ gen_load_gpr(t1, rs);\n+ gen_helper_fork(t0, t1);\n+ tcg_temp_free(t0);\n+ tcg_temp_free(t1);\n+ }\n+ break;\n+ case NM_MFTR:\n+ case NM_MFHTR:\n+ check_insn(ctx, ASE_MT);\n+ if (rd == 0) {\n+ /* Treat as NOP. */\n+ return;\n+ }\n+ gen_mftr(env, ctx, rs, rt, extract32(ctx->opcode, 10, 1),\n+ extract32(ctx->opcode, 11, 5), extract32(ctx->opcode, 3, 1));\n+ break;\n+ case NM_MTTR:\n+ case NM_MTHTR:\n+ check_insn(ctx, ASE_MT);\n+ gen_mttr(env, ctx, rs, rt, extract32(ctx->opcode, 10, 1),\n+ extract32(ctx->opcode, 11, 5), extract32(ctx->opcode, 3, 1));\n+ break;\n+ case NM_YIELD:\n+ check_insn(ctx, ASE_MT);\n+ {\n+ TCGv t0 = tcg_temp_new();\n+\n+ gen_load_gpr(t0, rs);\n+ gen_helper_yield(t0, cpu_env, t0);\n+ gen_store_gpr(t0, rt);\n+ tcg_temp_free(t0);\n+ }\n+ break;\n #endif\n default:\n generate_exception_end(ctx, EXCP_RI);\n@@ -17648,7 +17729,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)\n case NM_POOL32A:\n switch (ctx->opcode & 0x07) {\n case NM_POOL32A0:\n- gen_pool32a0_nanomips_insn(ctx);\n+ gen_pool32a0_nanomips_insn(env, ctx);\n break;\n case NM_POOL32A7:\n switch (extract32(ctx->opcode, 3, 3)) {\n", "prefixes": [ "v7", "38/80" ] }