Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/954024/?format=api
{ "id": 954024, "url": "http://patchwork.ozlabs.org/api/patches/954024/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1533574847-19294-35-git-send-email-aleksandar.markovic@rt-rk.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1533574847-19294-35-git-send-email-aleksandar.markovic@rt-rk.com>", "list_archive_url": null, "date": "2018-08-06T17:00:01", "name": "[v7,34/80] target/mips: Implement emulation of nanoMIPS EXTW instruction", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "6c21beab278a3beda57fa323e1c291cce2c83aab", "submitter": { "id": 68635, "url": "http://patchwork.ozlabs.org/api/people/68635/?format=api", "name": "Aleksandar Markovic", "email": "aleksandar.markovic@rt-rk.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1533574847-19294-35-git-send-email-aleksandar.markovic@rt-rk.com/mbox/", "series": [ { "id": 59520, "url": "http://patchwork.ozlabs.org/api/series/59520/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=59520", "date": "2018-08-06T16:59:27", "name": "Add nanoMIPS support to QEMU", "version": 7, "mbox": "http://patchwork.ozlabs.org/series/59520/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/954024/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/954024/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=none (p=none dis=none) header.from=rt-rk.com" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 41kkz34tmCz9s0R\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 7 Aug 2018 03:24:15 +1000 (AEST)", "from localhost ([::1]:35282 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1fmjEr-0004xx-A6\n\tfor incoming@patchwork.ozlabs.org; Mon, 06 Aug 2018 13:24:13 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:60341)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <aleksandar.markovic@rt-rk.com>) id 1fmj5W-00058e-Dt\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:14:35 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <aleksandar.markovic@rt-rk.com>) id 1fmj5V-0006Tr-97\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:14:34 -0400", "from mx2.rt-rk.com ([89.216.37.149]:49556 helo=mail.rt-rk.com)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <aleksandar.markovic@rt-rk.com>)\n\tid 1fmj5U-0006TJ-Tb\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:14:33 -0400", "from localhost (localhost [127.0.0.1])\n\tby mail.rt-rk.com (Postfix) with ESMTP id BAC811A209A;\n\tMon, 6 Aug 2018 19:14:31 +0200 (CEST)", "from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local\n\t[10.10.13.43])\n\tby mail.rt-rk.com (Postfix) with ESMTPSA id 8CBDC1A2036;\n\tMon, 6 Aug 2018 19:14:31 +0200 (CEST)" ], "X-Virus-Scanned": "amavisd-new at rt-rk.com", "From": "Aleksandar Markovic <aleksandar.markovic@rt-rk.com>", "To": "qemu-devel@nongnu.org", "Date": "Mon, 6 Aug 2018 19:00:01 +0200", "Message-Id": "<1533574847-19294-35-git-send-email-aleksandar.markovic@rt-rk.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1533574847-19294-1-git-send-email-aleksandar.markovic@rt-rk.com>", "References": "<1533574847-19294-1-git-send-email-aleksandar.markovic@rt-rk.com>", "X-detected-operating-system": "by eggs.gnu.org: GNU/Linux 3.x [fuzzy]", "X-Received-From": "89.216.37.149", "Subject": "[Qemu-devel] [PATCH v7 34/80] target/mips: Implement emulation of\n\tnanoMIPS EXTW instruction", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, thuth@redhat.com, pburton@wavecomp.com,\n\tsmarkovic@wavecomp.com, riku.voipio@iki.fi,\n\trichard.henderson@linaro.org, laurent@vivier.eu,\n\tarmbru@redhat.com, arikalo@wavecomp.com,\n\tphilippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com,\n\tpjovanovic@wavecomp.com, aurelien@aurel32.net", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: James Hogan <james.hogan@mips.com>\n\nImplement emulation of nanoMIPS EXTW instruction. EXTW instruction\nis similar to the MIPS r6 ALIGN instruction, except that it counts\nthe other way and in bits instead of bytes. We therefore generalise\ngen_align() function into a new gen_align_bits() function (which\ncounts in bits instead of bytes and optimises when bits = size of\nthe word), and implement gen_align() and a new gen_ext() based on\nthat. Since we need to know the word size to check for when the\nnumber of bits == the word size, the opc argument is replaced with\na wordsz argument (either 32 or 64).\n\nSigned-off-by: James Hogan <james.hogan@mips.com>\nSigned-off-by: Yongbok Kim <yongbok.kim@mips.com>\nSigned-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>\nSigned-off-by: Stefan Markovic <smarkovic@wavecomp.com>\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\n---\n target/mips/translate.c | 53 +++++++++++++++++++++++++++++++++----------------\n 1 file changed, 36 insertions(+), 17 deletions(-)", "diff": "diff --git a/target/mips/translate.c b/target/mips/translate.c\nindex c171bb8..715798c 100644\n--- a/target/mips/translate.c\n+++ b/target/mips/translate.c\n@@ -4735,8 +4735,8 @@ static void gen_lsa(DisasContext *ctx, int opc, int rd, int rs, int rt,\n return;\n }\n \n-static void gen_align(DisasContext *ctx, int opc, int rd, int rs, int rt,\n- int bp)\n+static void gen_align_bits(DisasContext *ctx, int wordsz, int rd, int rs,\n+ int rt, int bits)\n {\n TCGv t0;\n if (rd == 0) {\n@@ -4744,35 +4744,40 @@ static void gen_align(DisasContext *ctx, int opc, int rd, int rs, int rt,\n return;\n }\n t0 = tcg_temp_new();\n- gen_load_gpr(t0, rt);\n- if (bp == 0) {\n- switch (opc) {\n- case OPC_ALIGN:\n+ if (bits == 0 || bits == wordsz) {\n+ if (bits == 0) {\n+ gen_load_gpr(t0, rt);\n+ } else {\n+ gen_load_gpr(t0, rs);\n+ }\n+ switch (wordsz) {\n+ case 32:\n tcg_gen_ext32s_tl(cpu_gpr[rd], t0);\n break;\n #if defined(TARGET_MIPS64)\n- case OPC_DALIGN:\n+ case 64:\n tcg_gen_mov_tl(cpu_gpr[rd], t0);\n break;\n #endif\n }\n } else {\n TCGv t1 = tcg_temp_new();\n+ gen_load_gpr(t0, rt);\n gen_load_gpr(t1, rs);\n- switch (opc) {\n- case OPC_ALIGN:\n+ switch (wordsz) {\n+ case 32:\n {\n TCGv_i64 t2 = tcg_temp_new_i64();\n tcg_gen_concat_tl_i64(t2, t1, t0);\n- tcg_gen_shri_i64(t2, t2, 8 * (4 - bp));\n+ tcg_gen_shri_i64(t2, t2, 32 - bits);\n gen_move_low32(cpu_gpr[rd], t2);\n tcg_temp_free_i64(t2);\n }\n break;\n #if defined(TARGET_MIPS64)\n- case OPC_DALIGN:\n- tcg_gen_shli_tl(t0, t0, 8 * bp);\n- tcg_gen_shri_tl(t1, t1, 8 * (8 - bp));\n+ case 64:\n+ tcg_gen_shli_tl(t0, t0, bits);\n+ tcg_gen_shri_tl(t1, t1, 64 - bits);\n tcg_gen_or_tl(cpu_gpr[rd], t1, t0);\n break;\n #endif\n@@ -4783,6 +4788,18 @@ static void gen_align(DisasContext *ctx, int opc, int rd, int rs, int rt,\n tcg_temp_free(t0);\n }\n \n+static void gen_align(DisasContext *ctx, int wordsz, int rd, int rs, int rt,\n+ int bp)\n+{\n+ gen_align_bits(ctx, wordsz, rd, rs, rt, bp * 8);\n+}\n+\n+static void gen_ext(DisasContext *ctx, int wordsz, int rd, int rs, int rt,\n+ int shift)\n+{\n+ gen_align_bits(ctx, wordsz, rd, rs, rt, wordsz - shift);\n+}\n+\n static void gen_bitswap(DisasContext *ctx, int opc, int rd, int rt)\n {\n TCGv t0;\n@@ -14245,8 +14262,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)\n break;\n case ALIGN:\n check_insn(ctx, ISA_MIPS32R6);\n- gen_align(ctx, OPC_ALIGN, rd, rs, rt,\n- extract32(ctx->opcode, 9, 2));\n+ gen_align(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 9, 2));\n break;\n case EXT:\n gen_bitops(ctx, OPC_EXT, rt, rs, rr, rd);\n@@ -17426,6 +17442,9 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)\n gen_lsa(ctx, OPC_LSA, rd, rs, rt,\n extract32(ctx->opcode, 9, 2) - 1);\n break;\n+ case NM_EXTW:\n+ gen_ext(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 6, 5));\n+ break;\n case NM_POOL32AXF:\n gen_pool32axf_nanomips_insn(env, ctx);\n break;\n@@ -20275,7 +20294,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)\n switch (op2) {\n case OPC_ALIGN:\n case OPC_ALIGN_END:\n- gen_align(ctx, OPC_ALIGN, rd, rs, rt, sa & 3);\n+ gen_align(ctx, 32, rd, rs, rt, sa & 3);\n break;\n case OPC_BITSWAP:\n gen_bitswap(ctx, op2, rd, rt);\n@@ -20301,7 +20320,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)\n switch (op2) {\n case OPC_DALIGN:\n case OPC_DALIGN_END:\n- gen_align(ctx, OPC_DALIGN, rd, rs, rt, sa & 7);\n+ gen_align(ctx, 64, rd, rs, rt, sa & 7);\n break;\n case OPC_DBITSWAP:\n gen_bitswap(ctx, op2, rd, rt);\n", "prefixes": [ "v7", "34/80" ] }