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GET /api/patches/954022/?format=api
{ "id": 954022, "url": "http://patchwork.ozlabs.org/api/patches/954022/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1533574847-19294-17-git-send-email-aleksandar.markovic@rt-rk.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1533574847-19294-17-git-send-email-aleksandar.markovic@rt-rk.com>", "list_archive_url": null, "date": "2018-08-06T16:59:43", "name": "[v7,16/80] target/mips: Add nanoMIPS DSP ASE opcodes", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "a08a87b7cded97668f297966fc95716b758da32b", "submitter": { "id": 68635, "url": "http://patchwork.ozlabs.org/api/people/68635/?format=api", "name": "Aleksandar Markovic", "email": "aleksandar.markovic@rt-rk.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1533574847-19294-17-git-send-email-aleksandar.markovic@rt-rk.com/mbox/", "series": [ { "id": 59520, "url": "http://patchwork.ozlabs.org/api/series/59520/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=59520", "date": "2018-08-06T16:59:27", "name": "Add nanoMIPS support to QEMU", "version": 7, "mbox": "http://patchwork.ozlabs.org/series/59520/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/954022/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/954022/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=none (p=none dis=none) header.from=rt-rk.com" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 41kkwx1SmSz9s3q\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 7 Aug 2018 03:22:25 +1000 (AEST)", "from localhost ([::1]:35272 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1fmjD4-0003Cr-SR\n\tfor incoming@patchwork.ozlabs.org; Mon, 06 Aug 2018 13:22:22 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:54313)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <aleksandar.markovic@rt-rk.com>) id 1fmiyb-0006p0-EB\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:07:26 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <aleksandar.markovic@rt-rk.com>) id 1fmiyY-0007fw-LP\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:07:25 -0400", "from mx2.rt-rk.com ([89.216.37.149]:46477 helo=mail.rt-rk.com)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <aleksandar.markovic@rt-rk.com>)\n\tid 1fmiyY-0007eA-2t\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:07:22 -0400", "from localhost (localhost [127.0.0.1])\n\tby mail.rt-rk.com (Postfix) with ESMTP id 40CD01A209A;\n\tMon, 6 Aug 2018 19:07:20 +0200 (CEST)", "from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local\n\t[10.10.13.43])\n\tby mail.rt-rk.com (Postfix) with ESMTPSA id 1AE331A2039;\n\tMon, 6 Aug 2018 19:07:20 +0200 (CEST)" ], "X-Virus-Scanned": "amavisd-new at rt-rk.com", "From": "Aleksandar Markovic <aleksandar.markovic@rt-rk.com>", "To": "qemu-devel@nongnu.org", "Date": "Mon, 6 Aug 2018 18:59:43 +0200", "Message-Id": "<1533574847-19294-17-git-send-email-aleksandar.markovic@rt-rk.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1533574847-19294-1-git-send-email-aleksandar.markovic@rt-rk.com>", "References": "<1533574847-19294-1-git-send-email-aleksandar.markovic@rt-rk.com>", "X-detected-operating-system": "by eggs.gnu.org: GNU/Linux 3.x [fuzzy]", "X-Received-From": "89.216.37.149", "Subject": "[Qemu-devel] [PATCH v7 16/80] target/mips: Add nanoMIPS DSP ASE\n\topcodes", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, thuth@redhat.com, pburton@wavecomp.com,\n\tsmarkovic@wavecomp.com, riku.voipio@iki.fi,\n\trichard.henderson@linaro.org, laurent@vivier.eu,\n\tarmbru@redhat.com, arikalo@wavecomp.com,\n\tphilippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com,\n\tpjovanovic@wavecomp.com, aurelien@aurel32.net", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Stefan Markovic <smarkovic@wavecomp.com>\n\nAdd nanoMIPS opcodes for DSP ASE instruction pools and instructions.\n\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nSigned-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>\nSigned-off-by: Stefan Markovic <smarkovic@wavecomp.com>\n---\n target/mips/translate.c | 215 ++++++++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 215 insertions(+)", "diff": "diff --git a/target/mips/translate.c b/target/mips/translate.c\nindex bbe8b8a..1adf525 100644\n--- a/target/mips/translate.c\n+++ b/target/mips/translate.c\n@@ -15965,6 +15965,79 @@ enum {\n NM_SOV = 0x7a,\n };\n \n+/* POOL32A5 instruction pool */\n+enum {\n+ NM_CMP_EQ_PH = 0x00,\n+ NM_CMP_LT_PH = 0x08,\n+ NM_CMP_LE_PH = 0x10,\n+ NM_CMPGU_EQ_QB = 0x18,\n+ NM_CMPGU_LT_QB = 0x20,\n+ NM_CMPGU_LE_QB = 0x28,\n+ NM_CMPGDU_EQ_QB = 0x30,\n+ NM_CMPGDU_LT_QB = 0x38,\n+ NM_CMPGDU_LE_QB = 0x40,\n+ NM_CMPU_EQ_QB = 0x48,\n+ NM_CMPU_LT_QB = 0x50,\n+ NM_CMPU_LE_QB = 0x58,\n+ NM_ADDQ_S_W = 0x60,\n+ NM_SUBQ_S_W = 0x68,\n+ NM_ADDSC = 0x70,\n+ NM_ADDWC = 0x78,\n+\n+ NM_ADDQ_S_PH = 0x01,\n+ NM_ADDQH_R_PH = 0x09,\n+ NM_ADDQH_R_W = 0x11,\n+ NM_ADDU_S_QB = 0x19,\n+ NM_ADDU_S_PH = 0x21,\n+ NM_ADDUH_R_QB = 0x29,\n+ NM_SHRAV_R_PH = 0x31,\n+ NM_SHRAV_R_QB = 0x39,\n+ NM_SUBQ_S_PH = 0x41,\n+ NM_SUBQH_R_PH = 0x49,\n+ NM_SUBQH_R_W = 0x51,\n+ NM_SUBU_S_QB = 0x59,\n+ NM_SUBU_S_PH = 0x61,\n+ NM_SUBUH_R_QB = 0x69,\n+ NM_SHLLV_S_PH = 0x71,\n+ NM_PRECR_SRA_R_PH_W = 0x79,\n+\n+ NM_MULEU_S_PH_QBL = 0x12,\n+ NM_MULEU_S_PH_QBR = 0x1a,\n+ NM_MULQ_RS_PH = 0x22,\n+ NM_MULQ_S_PH = 0x2a,\n+ NM_MULQ_RS_W = 0x32,\n+ NM_MULQ_S_W = 0x3a,\n+ NM_APPEND = 0x42,\n+ NM_MODSUB = 0x52,\n+ NM_SHRAV_R_W = 0x5a,\n+ NM_SHRLV_PH = 0x62,\n+ NM_SHRLV_QB = 0x6a,\n+ NM_SHLLV_QB = 0x72,\n+ NM_SHLLV_S_W = 0x7a,\n+\n+ NM_SHILO = 0x03,\n+\n+ NM_MULEQ_S_W_PHL = 0x04,\n+ NM_MULEQ_S_W_PHR = 0x0c,\n+\n+ NM_MUL_S_PH = 0x05,\n+ NM_PRECR_QB_PH = 0x0d,\n+ NM_PRECRQ_QB_PH = 0x15,\n+ NM_PRECRQ_PH_W = 0x1d,\n+ NM_PRECRQ_RS_PH_W = 0x25,\n+ NM_PRECRQU_S_QB_PH = 0x2d,\n+ NM_PACKRL_PH = 0x35,\n+ NM_PICK_QB = 0x3d,\n+ NM_PICK_PH = 0x45,\n+\n+ NM_SHRA_R_W = 0x5e,\n+ NM_SHRA_R_PH = 0x66,\n+ NM_SHLL_S_PH = 0x76,\n+ NM_SHLL_S_W = 0x7e,\n+\n+ NM_REPL_PH = 0x07\n+};\n+\n /* POOL32A7 instruction pool */\n enum {\n NM_P_LSX = 0x00,\n@@ -16154,8 +16227,127 @@ enum {\n \n /* POOL32Axf instruction pool */\n enum {\n+ NM_POOL32AXF_1 = 0x01,\n+ NM_POOL32AXF_2 = 0x02,\n NM_POOL32AXF_4 = 0x04,\n NM_POOL32AXF_5 = 0x05,\n+ NM_POOL32AXF_7 = 0x07,\n+};\n+\n+/* POOL32Axf_1 instruction pool */\n+enum {\n+ NM_POOL32AXF_1_0 = 0x00,\n+ NM_POOL32AXF_1_1 = 0x01,\n+ NM_POOL32AXF_1_3 = 0x03,\n+ NM_POOL32AXF_1_4 = 0x04,\n+ NM_POOL32AXF_1_5 = 0x05,\n+ NM_POOL32AXF_1_7 = 0x07,\n+};\n+\n+/* POOL32Axf_2 instruction pool */\n+enum {\n+ NM_POOL32AXF_2_0_7 = 0x00,\n+ NM_POOL32AXF_2_8_15 = 0x01,\n+ NM_POOL32AXF_2_16_23 = 0x02,\n+ NM_POOL32AXF_2_24_31 = 0x03,\n+};\n+\n+/* POOL32Axf_7 instruction pool */\n+enum {\n+ NM_SHRA_R_QB = 0x0,\n+ NM_SHRL_PH = 0x1,\n+ NM_REPL_QB = 0x2,\n+};\n+\n+/* POOL32Axf_1_0 instruction pool */\n+enum {\n+ NM_MFHI = 0x0,\n+ NM_MFLO = 0x1,\n+ NM_MTHI = 0x2,\n+ NM_MTLO = 0x3,\n+};\n+\n+/* POOL32Axf_1_1 instruction pool */\n+enum {\n+ NM_MTHLIP = 0x0,\n+ NM_SHILOV = 0x1,\n+};\n+\n+/* POOL32Axf_1_3 instruction pool */\n+enum {\n+ NM_RDDSP = 0x0,\n+ NM_WRDSP = 0x1,\n+ NM_EXTP = 0x2,\n+ NM_EXTPDP = 0x3,\n+};\n+\n+/* POOL32Axf_1_4 instruction pool */\n+enum {\n+ NM_SHLL_QB = 0x0,\n+ NM_SHRL_QB = 0x1,\n+};\n+\n+/* POOL32Axf_1_5 instruction pool */\n+enum {\n+ NM_MAQ_S_W_PHR = 0x0,\n+ NM_MAQ_S_W_PHL = 0x1,\n+ NM_MAQ_SA_W_PHR = 0x2,\n+ NM_MAQ_SA_W_PHL = 0x3,\n+};\n+\n+/* POOL32Axf_1_7 instruction pool */\n+enum {\n+ NM_EXTR_W = 0x0,\n+ NM_EXTR_R_W = 0x1,\n+ NM_EXTR_RS_W = 0x2,\n+ NM_EXTR_S_H = 0x3,\n+};\n+\n+/* POOL32Axf_2_0_7 instruction pool */\n+enum {\n+ NM_DPA_W_PH = 0x0,\n+ NM_DPAQ_S_W_PH = 0x1,\n+ NM_DPS_W_PH = 0x2,\n+ NM_DPSQ_S_W_PH = 0x3,\n+ NM_BALIGN = 0x4,\n+ NM_MADD = 0x5,\n+ NM_MULT = 0x6,\n+ NM_EXTRV_W = 0x7,\n+};\n+\n+/* POOL32Axf_2_8_15 instruction pool */\n+enum {\n+ NM_DPAX_W_PH = 0x0,\n+ NM_DPAQ_SA_L_W = 0x1,\n+ NM_DPSX_W_PH = 0x2,\n+ NM_DPSQ_SA_L_W = 0x3,\n+ NM_MADDU = 0x5,\n+ NM_MULTU = 0x6,\n+ NM_EXTRV_R_W = 0x7,\n+};\n+\n+/* POOL32Axf_2_16_23 instruction pool */\n+enum {\n+ NM_DPAU_H_QBL = 0x0,\n+ NM_DPAQX_S_W_PH = 0x1,\n+ NM_DPSU_H_QBL = 0x2,\n+ NM_DPSQX_S_W_PH = 0x3,\n+ NM_EXTPV = 0x4,\n+ NM_MSUB = 0x5,\n+ NM_MULSA_W_PH = 0x6,\n+ NM_EXTRV_RS_W = 0x7,\n+};\n+\n+/* POOL32Axf_2_24_31 instruction pool */\n+enum {\n+ NM_DPAU_H_QBR = 0x0,\n+ NM_DPAQX_SA_W_PH = 0x1,\n+ NM_DPSU_H_QBR = 0x2,\n+ NM_DPSQX_SA_W_PH = 0x3,\n+ NM_EXTPDPV = 0x4,\n+ NM_MSUBU = 0x5,\n+ NM_MULSAQ_S_W_PH = 0x6,\n+ NM_EXTRV_S_H = 0x7,\n };\n \n /* POOL32Axf_{4, 5} instruction pool */\n@@ -16176,6 +16368,29 @@ enum {\n NM_WAIT = 0x61,\n NM_DERET = 0x71,\n NM_ERETX = 0x79,\n+\n+ /* nanoMIPS DSP instructions */\n+ NM_ABSQ_S_QB = 0x00,\n+ NM_ABSQ_S_PH = 0x08,\n+ NM_ABSQ_S_W = 0x10,\n+ NM_PRECEQ_W_PHL = 0x28,\n+ NM_PRECEQ_W_PHR = 0x30,\n+ NM_PRECEQU_PH_QBL = 0x38,\n+ NM_PRECEQU_PH_QBR = 0x48,\n+ NM_PRECEU_PH_QBL = 0x58,\n+ NM_PRECEU_PH_QBR = 0x68,\n+ NM_PRECEQU_PH_QBLA = 0x39,\n+ NM_PRECEQU_PH_QBRA = 0x49,\n+ NM_PRECEU_PH_QBLA = 0x59,\n+ NM_PRECEU_PH_QBRA = 0x69,\n+ NM_REPLV_PH = 0x01,\n+ NM_REPLV_QB = 0x09,\n+ NM_BITREV = 0x18,\n+ NM_INSV = 0x20,\n+ NM_RADDU_W_QB = 0x78,\n+\n+ NM_BITSWAP = 0x05,\n+ NM_WSBH = 0x3d,\n };\n \n /* PP.SR instruction pool */\n", "prefixes": [ "v7", "16/80" ] }