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GET /api/patches/954021/?format=api
{ "id": 954021, "url": "http://patchwork.ozlabs.org/api/patches/954021/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1533574847-19294-37-git-send-email-aleksandar.markovic@rt-rk.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1533574847-19294-37-git-send-email-aleksandar.markovic@rt-rk.com>", "list_archive_url": null, "date": "2018-08-06T17:00:03", "name": "[v7,36/80] target/mips: Implement emulation of nanoMIPS LLWP/SCWP pair", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "b23ac9f26a7d6b02469f571259a2900ec51e0490", "submitter": { "id": 68635, "url": "http://patchwork.ozlabs.org/api/people/68635/?format=api", "name": "Aleksandar Markovic", "email": "aleksandar.markovic@rt-rk.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1533574847-19294-37-git-send-email-aleksandar.markovic@rt-rk.com/mbox/", "series": [ { "id": 59520, "url": "http://patchwork.ozlabs.org/api/series/59520/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=59520", "date": "2018-08-06T16:59:27", "name": "Add nanoMIPS support to QEMU", "version": 7, "mbox": "http://patchwork.ozlabs.org/series/59520/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/954021/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/954021/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=none (p=none dis=none) header.from=rt-rk.com" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 41kkvz6rfyz9s0R\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 7 Aug 2018 03:21:35 +1000 (AEST)", "from localhost ([::1]:35269 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1fmjCH-0002WF-IP\n\tfor incoming@patchwork.ozlabs.org; Mon, 06 Aug 2018 13:21:33 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:32929)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <aleksandar.markovic@rt-rk.com>) id 1fmj6Y-0006h6-HA\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:15:40 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <aleksandar.markovic@rt-rk.com>) id 1fmj6T-0007Js-N1\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:15:38 -0400", "from mx2.rt-rk.com ([89.216.37.149]:53605 helo=mail.rt-rk.com)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <aleksandar.markovic@rt-rk.com>)\n\tid 1fmj6S-0007Ho-K6\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:15:33 -0400", "from localhost (localhost [127.0.0.1])\n\tby mail.rt-rk.com (Postfix) with ESMTP id 424841A209A;\n\tMon, 6 Aug 2018 19:15:31 +0200 (CEST)", "from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local\n\t[10.10.13.43])\n\tby mail.rt-rk.com (Postfix) with ESMTPSA id 1D4431A2036;\n\tMon, 6 Aug 2018 19:15:31 +0200 (CEST)" ], "X-Virus-Scanned": "amavisd-new at rt-rk.com", "From": "Aleksandar Markovic <aleksandar.markovic@rt-rk.com>", "To": "qemu-devel@nongnu.org", "Date": "Mon, 6 Aug 2018 19:00:03 +0200", "Message-Id": "<1533574847-19294-37-git-send-email-aleksandar.markovic@rt-rk.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1533574847-19294-1-git-send-email-aleksandar.markovic@rt-rk.com>", "References": "<1533574847-19294-1-git-send-email-aleksandar.markovic@rt-rk.com>", "X-detected-operating-system": "by eggs.gnu.org: GNU/Linux 3.x [fuzzy]", "X-Received-From": "89.216.37.149", "Subject": "[Qemu-devel] [PATCH v7 36/80] target/mips: Implement emulation of\n\tnanoMIPS LLWP/SCWP pair", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, thuth@redhat.com, pburton@wavecomp.com,\n\tsmarkovic@wavecomp.com, riku.voipio@iki.fi,\n\trichard.henderson@linaro.org, laurent@vivier.eu,\n\tarmbru@redhat.com, arikalo@wavecomp.com,\n\tphilippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com,\n\tpjovanovic@wavecomp.com, aurelien@aurel32.net", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Aleksandar Rikalo <arikalo@wavecomp.com>\n\nImplement support for nanoMIPS LLWP/SCWP instruction pair.\n\nSigned-off-by: Dimitrije Nikolic <dnikolic@wavecomp.com>\nSigned-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>\nSigned-off-by: Stefan Markovic <smarkovic@wavecomp.com>\n---\n linux-user/mips/cpu_loop.c | 25 +++++++++++---\n target/mips/cpu.h | 2 ++\n target/mips/translate.c | 84 ++++++++++++++++++++++++++++++++++++++++++++++\n 3 files changed, 106 insertions(+), 5 deletions(-)", "diff": "diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c\nindex 084ad6a..1d3dc9e 100644\n--- a/linux-user/mips/cpu_loop.c\n+++ b/linux-user/mips/cpu_loop.c\n@@ -397,10 +397,13 @@ static int do_store_exclusive(CPUMIPSState *env)\n target_ulong addr;\n target_ulong page_addr;\n target_ulong val;\n+ uint32_t val_wp = 0;\n+ uint32_t llnewval_wp = 0;\n int flags;\n int segv = 0;\n int reg;\n int d;\n+ int wp;\n \n addr = env->lladdr;\n page_addr = addr & TARGET_PAGE_MASK;\n@@ -412,19 +415,31 @@ static int do_store_exclusive(CPUMIPSState *env)\n } else {\n reg = env->llreg & 0x1f;\n d = (env->llreg & 0x20) != 0;\n- if (d) {\n- segv = get_user_s64(val, addr);\n+ wp = (env->llreg & 0x40) != 0;\n+ if (!wp) {\n+ if (d) {\n+ segv = get_user_s64(val, addr);\n+ } else {\n+ segv = get_user_s32(val, addr);\n+ }\n } else {\n segv = get_user_s32(val, addr);\n+ segv |= get_user_s32(val_wp, addr);\n+ llnewval_wp = env->llnewval_wp;\n }\n if (!segv) {\n- if (val != env->llval) {\n+ if (val != env->llval && val_wp == llnewval_wp) {\n env->active_tc.gpr[reg] = 0;\n } else {\n- if (d) {\n- segv = put_user_u64(env->llnewval, addr);\n+ if (!wp) {\n+ if (d) {\n+ segv = put_user_u64(env->llnewval, addr);\n+ } else {\n+ segv = put_user_u32(env->llnewval, addr);\n+ }\n } else {\n segv = put_user_u32(env->llnewval, addr);\n+ segv |= put_user_u32(env->llnewval_wp, addr + 4);\n }\n if (!segv) {\n env->active_tc.gpr[reg] = 1;\ndiff --git a/target/mips/cpu.h b/target/mips/cpu.h\nindex 009202c..28af4d1 100644\n--- a/target/mips/cpu.h\n+++ b/target/mips/cpu.h\n@@ -506,6 +506,8 @@ struct CPUMIPSState {\n uint64_t lladdr;\n target_ulong llval;\n target_ulong llnewval;\n+ uint64_t llval_wp;\n+ uint32_t llnewval_wp;\n target_ulong llreg;\n uint64_t CP0_LLAddr_rw_bitmask;\n int CP0_LLAddr_shift;\ndiff --git a/target/mips/translate.c b/target/mips/translate.c\nindex cf8b748..945dd73 100644\n--- a/target/mips/translate.c\n+++ b/target/mips/translate.c\n@@ -1458,6 +1458,7 @@ typedef struct DisasContext {\n bool mrp;\n bool nan2008;\n bool abs2008;\n+ bool xnp;\n } DisasContext;\n \n #define DISAS_STOP DISAS_TARGET_0\n@@ -2347,6 +2348,31 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,\n tcg_temp_free(t0);\n }\n \n+static void gen_llwp(DisasContext *ctx, uint32_t base, int16_t offset,\n+ uint32_t reg1, uint32_t reg2)\n+{\n+ TCGv taddr = tcg_temp_new();\n+ TCGv_i64 tval = tcg_temp_new_i64();\n+ TCGv tmp1 = tcg_temp_new();\n+ TCGv tmp2 = tcg_temp_new();\n+\n+ gen_base_offset_addr(ctx, taddr, base, offset);\n+ tcg_gen_qemu_ld64(tval, taddr, ctx->mem_idx);\n+#ifdef TARGET_WORDS_BIGENDIAN\n+ tcg_gen_extr_i64_tl(tmp2, tmp1, tval);\n+#else\n+ tcg_gen_extr_i64_tl(tmp1, tmp2, tval);\n+#endif\n+ gen_store_gpr(tmp1, reg1);\n+ tcg_temp_free(tmp1);\n+ gen_store_gpr(tmp2, reg2);\n+ tcg_temp_free(tmp2);\n+ tcg_gen_st_i64(tval, cpu_env, offsetof(CPUMIPSState, llval_wp));\n+ tcg_temp_free_i64(tval);\n+ tcg_gen_st_tl(taddr, cpu_env, offsetof(CPUMIPSState, lladdr));\n+ tcg_temp_free(taddr);\n+}\n+\n /* Store */\n static void gen_st (DisasContext *ctx, uint32_t opc, int rt,\n int base, int offset)\n@@ -2443,6 +2469,51 @@ static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt,\n tcg_temp_free(t0);\n }\n \n+static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset,\n+ uint32_t reg1, uint32_t reg2)\n+{\n+ TCGv taddr = tcg_temp_local_new();\n+ TCGv lladdr = tcg_temp_local_new();\n+ TCGv_i64 tval = tcg_temp_new_i64();\n+ TCGv_i64 llval = tcg_temp_new_i64();\n+ TCGv_i64 val = tcg_temp_new_i64();\n+ TCGv tmp1 = tcg_temp_new();\n+ TCGv tmp2 = tcg_temp_new();\n+ TCGLabel *lab_fail = gen_new_label();\n+ TCGLabel *lab_done = gen_new_label();\n+\n+ gen_base_offset_addr(ctx, taddr, base, offset);\n+\n+ tcg_gen_ld_tl(lladdr, cpu_env, offsetof(CPUMIPSState, lladdr));\n+ tcg_gen_brcond_tl(TCG_COND_NE, taddr, lladdr, lab_fail);\n+\n+ gen_load_gpr(tmp1, reg1);\n+ gen_load_gpr(tmp2, reg2);\n+\n+#ifdef TARGET_WORDS_BIGENDIAN\n+ tcg_gen_concat_tl_i64(tval, tmp2, tmp1);\n+#else\n+ tcg_gen_concat_tl_i64(tval, tmp1, tmp2);\n+#endif\n+\n+ tcg_gen_ld_i64(llval, cpu_env, offsetof(CPUMIPSState, llval_wp));\n+ tcg_gen_atomic_cmpxchg_i64(val, taddr, llval, tval,\n+ ctx->mem_idx, MO_64);\n+ if (reg1 != 0) {\n+ tcg_gen_movi_tl(cpu_gpr[reg1], 1);\n+ }\n+ tcg_gen_brcond_i64(TCG_COND_EQ, val, llval, lab_done);\n+\n+ gen_set_label(lab_fail);\n+\n+ if (reg1 != 0) {\n+ tcg_gen_movi_tl(cpu_gpr[reg1], 0);\n+ }\n+ gen_set_label(lab_done);\n+ tcg_gen_movi_tl(lladdr, -1);\n+ tcg_gen_st_tl(lladdr, cpu_env, offsetof(CPUMIPSState, lladdr));\n+}\n+\n /* Load and store */\n static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,\n TCGv t0)\n@@ -17926,6 +17997,12 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)\n gen_ld(ctx, OPC_LL, rt, rs, s);\n break;\n case NM_LLWP:\n+ if (ctx->xnp) {\n+ generate_exception_end(ctx, EXCP_RI);\n+ } else {\n+ gen_llwp(ctx, rs, 0, rt,\n+ extract32(ctx->opcode, 3, 5));\n+ }\n break;\n }\n break;\n@@ -17935,6 +18012,12 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)\n gen_st_cond(ctx, OPC_SC, rt, rs, s);\n break;\n case NM_SCWP:\n+ if (ctx->xnp) {\n+ generate_exception_end(ctx, EXCP_RI);\n+ } else {\n+ gen_scwp(ctx, rs, 0, rt,\n+ extract32(ctx->opcode, 3, 5));\n+ }\n break;\n }\n break;\n@@ -23123,6 +23206,7 @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)\n ctx->mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1;\n ctx->nan2008 = (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1;\n ctx->abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1;\n+ ctx->xnp = (env->CP0_Config5 >> CP0C5_XNP) & 1;\n restore_cpu_state(env, ctx);\n #ifdef CONFIG_USER_ONLY\n ctx->mem_idx = MIPS_HFLAG_UM;\n", "prefixes": [ "v7", "36/80" ] }