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GET /api/patches/954020/?format=api
{ "id": 954020, "url": "http://patchwork.ozlabs.org/api/patches/954020/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1533574847-19294-33-git-send-email-aleksandar.markovic@rt-rk.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1533574847-19294-33-git-send-email-aleksandar.markovic@rt-rk.com>", "list_archive_url": null, "date": "2018-08-06T16:59:59", "name": "[v7,32/80] target/mips: Add emulation of misc nanoMIPS instructions (p_lsx)", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "6bb4e93cf4c8747b5aa15de67681b253335fea9b", "submitter": { "id": 68635, "url": "http://patchwork.ozlabs.org/api/people/68635/?format=api", "name": "Aleksandar Markovic", "email": "aleksandar.markovic@rt-rk.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1533574847-19294-33-git-send-email-aleksandar.markovic@rt-rk.com/mbox/", "series": [ { "id": 59520, "url": "http://patchwork.ozlabs.org/api/series/59520/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=59520", "date": "2018-08-06T16:59:27", "name": "Add nanoMIPS support to QEMU", "version": 7, "mbox": "http://patchwork.ozlabs.org/series/59520/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/954020/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/954020/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=none (p=none dis=none) header.from=rt-rk.com" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 41kkvk5SD8z9ryt\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 7 Aug 2018 03:21:22 +1000 (AEST)", "from localhost ([::1]:35266 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1fmjC3-0002Mg-J6\n\tfor incoming@patchwork.ozlabs.org; Mon, 06 Aug 2018 13:21:19 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:59567)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <aleksandar.markovic@rt-rk.com>) id 1fmj4j-0004Oq-DC\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:13:46 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <aleksandar.markovic@rt-rk.com>) id 1fmj4i-0005lV-7i\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:13:45 -0400", "from mx2.rt-rk.com ([89.216.37.149]:49414 helo=mail.rt-rk.com)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <aleksandar.markovic@rt-rk.com>)\n\tid 1fmj4h-0005kI-Rk\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:13:44 -0400", "from localhost (localhost [127.0.0.1])\n\tby mail.rt-rk.com (Postfix) with ESMTP id 981AE1A45F4;\n\tMon, 6 Aug 2018 19:13:42 +0200 (CEST)", "from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local\n\t[10.10.13.43])\n\tby mail.rt-rk.com (Postfix) with ESMTPSA id 96AA41A209F;\n\tMon, 6 Aug 2018 19:13:41 +0200 (CEST)" ], "X-Virus-Scanned": "amavisd-new at rt-rk.com", "From": "Aleksandar Markovic <aleksandar.markovic@rt-rk.com>", "To": "qemu-devel@nongnu.org", "Date": "Mon, 6 Aug 2018 18:59:59 +0200", "Message-Id": "<1533574847-19294-33-git-send-email-aleksandar.markovic@rt-rk.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1533574847-19294-1-git-send-email-aleksandar.markovic@rt-rk.com>", "References": "<1533574847-19294-1-git-send-email-aleksandar.markovic@rt-rk.com>", "X-detected-operating-system": "by eggs.gnu.org: GNU/Linux 3.x [fuzzy]", "X-Received-From": "89.216.37.149", "Subject": "[Qemu-devel] [PATCH v7 32/80] target/mips: Add emulation of misc\n\tnanoMIPS instructions (p_lsx)", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, thuth@redhat.com, pburton@wavecomp.com,\n\tsmarkovic@wavecomp.com, riku.voipio@iki.fi,\n\trichard.henderson@linaro.org, laurent@vivier.eu,\n\tarmbru@redhat.com, arikalo@wavecomp.com,\n\tphilippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com,\n\tpjovanovic@wavecomp.com, aurelien@aurel32.net", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Yongbok Kim <yongbok.kim@mips.com>\n\nAdd emulation of nanoMIPS instructions situated in pool p_lsx, and\nemulation of LSA instruction as well.\n\nReviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>\nSigned-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>\nSigned-off-by: Stefan Markovic <smarkovic@wavecomp.com>\n---\n target/mips/translate.c | 132 +++++++++++++++++++++++++++++++++++++++++++++++-\n 1 file changed, 131 insertions(+), 1 deletion(-)", "diff": "diff --git a/target/mips/translate.c b/target/mips/translate.c\nindex 76424c6..657e9c0 100644\n--- a/target/mips/translate.c\n+++ b/target/mips/translate.c\n@@ -16926,6 +16926,125 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)\n }\n }\n \n+\n+static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt)\n+{\n+ TCGv t0, t1;\n+ t0 = tcg_temp_new();\n+ t1 = tcg_temp_new();\n+\n+ gen_load_gpr(t0, rs);\n+ gen_load_gpr(t1, rt);\n+\n+ if ((extract32(ctx->opcode, 6, 1)) == 1) {\n+ /* PP.LSXS instructions require shifting */\n+ switch (extract32(ctx->opcode, 7, 4)) {\n+ case NM_LHXS:\n+ case NM_SHXS:\n+ case NM_LHUXS:\n+ tcg_gen_shli_tl(t0, t0, 1);\n+ break;\n+ case NM_LWXS:\n+ case NM_SWXS:\n+ case NM_LWC1XS:\n+ case NM_SWC1XS:\n+ tcg_gen_shli_tl(t0, t0, 2);\n+ break;\n+ case NM_LDC1XS:\n+ case NM_SDC1XS:\n+ tcg_gen_shli_tl(t0, t0, 3);\n+ break;\n+ }\n+ }\n+ gen_op_addr_add(ctx, t0, t0, t1);\n+\n+ switch (extract32(ctx->opcode, 7, 4)) {\n+ case NM_LBX:\n+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,\n+ MO_SB);\n+ gen_store_gpr(t0, rd);\n+ break;\n+ case NM_LHX:\n+ /*case NM_LHXS:*/\n+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,\n+ MO_TESW);\n+ gen_store_gpr(t0, rd);\n+ break;\n+ case NM_LWX:\n+ /*case NM_LWXS:*/\n+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,\n+ MO_TESL);\n+ gen_store_gpr(t0, rd);\n+ break;\n+ case NM_LBUX:\n+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,\n+ MO_UB);\n+ gen_store_gpr(t0, rd);\n+ break;\n+ case NM_LHUX:\n+ /*case NM_LHUXS:*/\n+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,\n+ MO_TEUW);\n+ gen_store_gpr(t0, rd);\n+ break;\n+ case NM_SBX:\n+ gen_load_gpr(t1, rd);\n+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,\n+ MO_8);\n+ break;\n+ case NM_SHX:\n+ /*case NM_SHXS:*/\n+ gen_load_gpr(t1, rd);\n+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,\n+ MO_TEUW);\n+ break;\n+ case NM_SWX:\n+ /*case NM_SWXS:*/\n+ gen_load_gpr(t1, rd);\n+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,\n+ MO_TEUL);\n+ break;\n+ case NM_LWC1X:\n+ /*case NM_LWC1XS:*/\n+ case NM_LDC1X:\n+ /*case NM_LDC1XS:*/\n+ case NM_SWC1X:\n+ /*case NM_SWC1XS:*/\n+ case NM_SDC1X:\n+ /*case NM_SDC1XS:*/\n+ if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {\n+ check_cp1_enabled(ctx);\n+ switch (extract32(ctx->opcode, 7, 4)) {\n+ case NM_LWC1X:\n+ /*case NM_LWC1XS:*/\n+ gen_flt_ldst(ctx, OPC_LWC1, rd, t0);\n+ break;\n+ case NM_LDC1X:\n+ /*case NM_LDC1XS:*/\n+ gen_flt_ldst(ctx, OPC_LDC1, rd, t0);\n+ break;\n+ case NM_SWC1X:\n+ /*case NM_SWC1XS:*/\n+ gen_flt_ldst(ctx, OPC_SWC1, rd, t0);\n+ break;\n+ case NM_SDC1X:\n+ /*case NM_SDC1XS:*/\n+ gen_flt_ldst(ctx, OPC_SDC1, rd, t0);\n+ break;\n+ }\n+ } else {\n+ generate_exception_err(ctx, EXCP_CpU, 1);\n+ }\n+ break;\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n+\n+ tcg_temp_free(t0);\n+ tcg_temp_free(t1);\n+}\n+\n static void gen_pool32f_nanomips_insn(DisasContext *ctx)\n {\n int rt, rs, rd;\n@@ -17229,7 +17348,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)\n {\n uint16_t insn;\n uint32_t op;\n- int rt, rs;\n+ int rt, rs, rd;\n int offset;\n int imm;\n \n@@ -17238,6 +17357,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)\n \n rt = extract32(ctx->opcode, 21, 5);\n rs = extract32(ctx->opcode, 16, 5);\n+ rd = extract32(ctx->opcode, 11, 5);\n \n op = extract32(ctx->opcode, 26, 6);\n switch (op) {\n@@ -17296,6 +17416,16 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)\n break;\n case NM_POOL32A7:\n switch (extract32(ctx->opcode, 3, 3)) {\n+ case NM_P_LSX:\n+ gen_p_lsx(ctx, rd, rs, rt);\n+ break;\n+ case NM_LSA:\n+ /* In nanoMIPS, the shift field directly encodes the shift\n+ * amount, meaning that the supported shift values are in\n+ * the range 0 to 3 (instead of 1 to 4 in MIPSR6). */\n+ gen_lsa(ctx, OPC_LSA, rd, rs, rt,\n+ extract32(ctx->opcode, 9, 2) - 1);\n+ break;\n case NM_POOL32AXF:\n gen_pool32axf_nanomips_insn(env, ctx);\n break;\n", "prefixes": [ "v7", "32/80" ] }