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GET /api/patches/954019/?format=api
{ "id": 954019, "url": "http://patchwork.ozlabs.org/api/patches/954019/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1533574847-19294-24-git-send-email-aleksandar.markovic@rt-rk.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1533574847-19294-24-git-send-email-aleksandar.markovic@rt-rk.com>", "list_archive_url": null, "date": "2018-08-06T16:59:50", "name": "[v7,23/80] target/mips: Add emulation of nanoMIPS 16-bit load and store instructions", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "8b0e78937fa6c8612c843c0bd00d6251528431e5", "submitter": { "id": 68635, "url": "http://patchwork.ozlabs.org/api/people/68635/?format=api", "name": "Aleksandar Markovic", "email": "aleksandar.markovic@rt-rk.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1533574847-19294-24-git-send-email-aleksandar.markovic@rt-rk.com/mbox/", "series": [ { "id": 59520, "url": "http://patchwork.ozlabs.org/api/series/59520/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=59520", "date": "2018-08-06T16:59:27", "name": "Add nanoMIPS support to QEMU", "version": 7, "mbox": "http://patchwork.ozlabs.org/series/59520/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/954019/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/954019/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=none (p=none dis=none) header.from=rt-rk.com" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 41kktC5ZnZz9ryt\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 7 Aug 2018 03:20:02 +1000 (AEST)", "from localhost ([::1]:35254 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1fmjAm-0000zo-3K\n\tfor incoming@patchwork.ozlabs.org; Mon, 06 Aug 2018 13:20:00 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:56452)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <aleksandar.markovic@rt-rk.com>) id 1fmj1B-00019t-VL\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:10:07 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <aleksandar.markovic@rt-rk.com>) id 1fmj19-0001xi-40\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:10:05 -0400", "from mx2.rt-rk.com ([89.216.37.149]:47124 helo=mail.rt-rk.com)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <aleksandar.markovic@rt-rk.com>)\n\tid 1fmj18-0001uS-Jq\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:10:03 -0400", "from localhost (localhost [127.0.0.1])\n\tby mail.rt-rk.com (Postfix) with ESMTP id 90CA81A209A;\n\tMon, 6 Aug 2018 19:10:00 +0200 (CEST)", "from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local\n\t[10.10.13.43])\n\tby mail.rt-rk.com (Postfix) with ESMTPSA id 6C7311A2039;\n\tMon, 6 Aug 2018 19:10:00 +0200 (CEST)" ], "X-Virus-Scanned": "amavisd-new at rt-rk.com", "From": "Aleksandar Markovic <aleksandar.markovic@rt-rk.com>", "To": "qemu-devel@nongnu.org", "Date": "Mon, 6 Aug 2018 18:59:50 +0200", "Message-Id": "<1533574847-19294-24-git-send-email-aleksandar.markovic@rt-rk.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1533574847-19294-1-git-send-email-aleksandar.markovic@rt-rk.com>", "References": "<1533574847-19294-1-git-send-email-aleksandar.markovic@rt-rk.com>", "X-detected-operating-system": "by eggs.gnu.org: GNU/Linux 3.x [fuzzy]", "X-Received-From": "89.216.37.149", "Subject": "[Qemu-devel] [PATCH v7 23/80] target/mips: Add emulation of\n\tnanoMIPS 16-bit load and store instructions", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, thuth@redhat.com, pburton@wavecomp.com,\n\tsmarkovic@wavecomp.com, riku.voipio@iki.fi,\n\trichard.henderson@linaro.org, laurent@vivier.eu,\n\tarmbru@redhat.com, arikalo@wavecomp.com,\n\tphilippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com,\n\tpjovanovic@wavecomp.com, aurelien@aurel32.net", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Yongbok Kim <yongbok.kim@mips.com>\n\nAdd emulation of LWXS16, LB16, SB16, LBU16, LH16, SH16, LHU16, LW16, LWSP16,\nLW4X4, SW4X4, LWGP16, SWSP16, SW16, and SWGP16 instructions.\n\nSigned-off-by: Yongbok Kim <yongbok.kim@mips.com>\nSigned-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>\nSigned-off-by: Stefan Markovic <smarkovic@wavecomp.com>\n---\n target/mips/translate.c | 81 +++++++++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 81 insertions(+)", "diff": "diff --git a/target/mips/translate.c b/target/mips/translate.c\nindex 7a3d45b..db07cfe 100644\n--- a/target/mips/translate.c\n+++ b/target/mips/translate.c\n@@ -16599,6 +16599,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)\n int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD(ctx->opcode));\n int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS(ctx->opcode));\n int rd = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS1(ctx->opcode));\n+ int offset;\n int imm;\n \n /* make sure instructions are on a halfword boundary */\n@@ -16666,6 +16667,13 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)\n }\n break;\n case NM_P16C:\n+ switch (ctx->opcode & 1) {\n+ case NM_POOL16C_0:\n+ break;\n+ case NM_LWXS16:\n+ gen_ldxs(ctx, rt, rs, rd);\n+ break;\n+ }\n break;\n case NM_P16_A1:\n switch (extract32(ctx->opcode, 6, 1)) {\n@@ -16737,24 +16745,97 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)\n case NM_ANDI16:\n break;\n case NM_P16_LB:\n+ switch (extract32(ctx->opcode, 2, 2)) {\n+ case NM_LB16:\n+ offset = extract32(ctx->opcode, 0, 2);\n+ gen_ld(ctx, OPC_LB, rt, rs, offset);\n+ break;\n+ case NM_SB16:\n+ offset = decode_gpr_gpr3_src_store(\n+ NANOMIPS_EXTRACT_RD(ctx->opcode));\n+ gen_st(ctx, OPC_SB, rt, rs, offset);\n+ break;\n+ case NM_LBU16:\n+ offset = extract32(ctx->opcode, 0, 2);\n+ gen_ld(ctx, OPC_LBU, rt, rs, offset);\n+ break;\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n break;\n case NM_P16_LH:\n+ switch ((extract32(ctx->opcode, 3, 1) << 1) | (ctx->opcode & 1)) {\n+ case NM_LH16:\n+ offset = extract32(ctx->opcode, 1, 2) << 1;\n+ gen_ld(ctx, OPC_LH, rt, rs, offset);\n+ break;\n+ case NM_SH16:\n+ offset = decode_gpr_gpr3_src_store(\n+ NANOMIPS_EXTRACT_RD(ctx->opcode));\n+ gen_st(ctx, OPC_SH, rt, rs, offset);\n+ break;\n+ case NM_LHU16:\n+ offset = extract32(ctx->opcode, 1, 2) << 1;\n+ gen_ld(ctx, OPC_LHU, rt, rs, offset);\n+ break;\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n break;\n case NM_LW16:\n+ offset = extract32(ctx->opcode, 0, 4) << 2;\n+ gen_ld(ctx, OPC_LW, rt, rs, offset);\n break;\n case NM_LWSP16:\n+ rt = NANOMIPS_EXTRACT_RD5(ctx->opcode);\n+ offset = extract32(ctx->opcode, 0, 5) << 2;\n+ gen_ld(ctx, OPC_LW, rt, 29, offset);\n break;\n case NM_LW4X4:\n+ rt = (extract32(ctx->opcode, 9, 1) << 3) |\n+ extract32(ctx->opcode, 5, 3);\n+ rs = (extract32(ctx->opcode, 4, 1) << 3) |\n+ extract32(ctx->opcode, 0, 3);\n+ offset = (extract32(ctx->opcode, 3, 1) << 3) |\n+ (extract32(ctx->opcode, 8, 1) << 2);\n+ rt = decode_gpr_gpr4(rt);\n+ rs = decode_gpr_gpr4(rs);\n+ gen_ld(ctx, OPC_LW, rt, rs, offset);\n break;\n case NM_SW4X4:\n+ rt = (extract32(ctx->opcode, 9, 1) << 3) |\n+ extract32(ctx->opcode, 5, 3);\n+ rs = (extract32(ctx->opcode, 4, 1) << 3) |\n+ extract32(ctx->opcode, 0, 3);\n+ offset = (extract32(ctx->opcode, 3, 1) << 3) |\n+ (extract32(ctx->opcode, 8, 1) << 2);\n+ rt = decode_gpr_gpr4_zero(rt);\n+ rs = decode_gpr_gpr4(rs);\n+ gen_st(ctx, OPC_SW, rt, rs, offset);\n break;\n case NM_LWGP16:\n+ offset = extract32(ctx->opcode, 0, 7) << 2;\n+ gen_ld(ctx, OPC_LW, rt, 28, offset);\n break;\n case NM_SWSP16:\n+ rt = NANOMIPS_EXTRACT_RD5(ctx->opcode);\n+ offset = extract32(ctx->opcode, 0, 5) << 2;\n+ gen_st(ctx, OPC_SW, rt, 29, offset);\n break;\n case NM_SW16:\n+ rt = decode_gpr_gpr3_src_store(\n+ NANOMIPS_EXTRACT_RD(ctx->opcode));\n+ rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS(ctx->opcode));\n+ offset = extract32(ctx->opcode, 0, 4) << 2;\n+ gen_st(ctx, OPC_SW, rt, rs, offset);\n break;\n case NM_SWGP16:\n+ rt = decode_gpr_gpr3_src_store(\n+ NANOMIPS_EXTRACT_RD(ctx->opcode));\n+ offset = extract32(ctx->opcode, 0, 7) << 2;\n+ gen_st(ctx, OPC_SW, rt, 28, offset);\n break;\n case NM_BC16:\n gen_compute_branch(ctx, OPC_BEQ, 2, 0, 0,\n", "prefixes": [ "v7", "23/80" ] }