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GET /api/patches/954017/?format=api
{ "id": 954017, "url": "http://patchwork.ozlabs.org/api/patches/954017/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1533574847-19294-36-git-send-email-aleksandar.markovic@rt-rk.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1533574847-19294-36-git-send-email-aleksandar.markovic@rt-rk.com>", "list_archive_url": null, "date": "2018-08-06T17:00:02", "name": "[v7,35/80] target/mips: Add emulation of nanoMIPS 32-bit load and store instructions", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "fda0eda992124143fa7414d8b809100a282a8cb7", "submitter": { "id": 68635, "url": "http://patchwork.ozlabs.org/api/people/68635/?format=api", "name": "Aleksandar Markovic", "email": "aleksandar.markovic@rt-rk.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1533574847-19294-36-git-send-email-aleksandar.markovic@rt-rk.com/mbox/", "series": [ { "id": 59520, "url": "http://patchwork.ozlabs.org/api/series/59520/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=59520", "date": "2018-08-06T16:59:27", "name": "Add nanoMIPS support to QEMU", "version": 7, "mbox": "http://patchwork.ozlabs.org/series/59520/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/954017/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/954017/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=none (p=none dis=none) header.from=rt-rk.com" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 41kkrL1X5Bz9ryt\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 7 Aug 2018 03:18:26 +1000 (AEST)", "from localhost ([::1]:35247 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1fmj9D-0008AD-NG\n\tfor incoming@patchwork.ozlabs.org; Mon, 06 Aug 2018 13:18:23 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:60748)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <aleksandar.markovic@rt-rk.com>) id 1fmj6A-0006Gl-6F\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:15:15 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <aleksandar.markovic@rt-rk.com>) id 1fmj67-0006pC-Dr\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:15:14 -0400", "from mx2.rt-rk.com ([89.216.37.149]:52853 helo=mail.rt-rk.com)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <aleksandar.markovic@rt-rk.com>)\n\tid 1fmj67-0006nh-1q\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:15:11 -0400", "from localhost (localhost [127.0.0.1])\n\tby mail.rt-rk.com (Postfix) with ESMTP id 8D75D1A209A;\n\tMon, 6 Aug 2018 19:15:09 +0200 (CEST)", "from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local\n\t[10.10.13.43])\n\tby mail.rt-rk.com (Postfix) with ESMTPSA id 64F841A2036;\n\tMon, 6 Aug 2018 19:15:09 +0200 (CEST)" ], "X-Virus-Scanned": "amavisd-new at rt-rk.com", "From": "Aleksandar Markovic <aleksandar.markovic@rt-rk.com>", "To": "qemu-devel@nongnu.org", "Date": "Mon, 6 Aug 2018 19:00:02 +0200", "Message-Id": "<1533574847-19294-36-git-send-email-aleksandar.markovic@rt-rk.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1533574847-19294-1-git-send-email-aleksandar.markovic@rt-rk.com>", "References": "<1533574847-19294-1-git-send-email-aleksandar.markovic@rt-rk.com>", "X-detected-operating-system": "by eggs.gnu.org: GNU/Linux 3.x [fuzzy]", "X-Received-From": "89.216.37.149", "Subject": "[Qemu-devel] [PATCH v7 35/80] target/mips: Add emulation of\n\tnanoMIPS 32-bit load and store instructions", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, thuth@redhat.com, pburton@wavecomp.com,\n\tsmarkovic@wavecomp.com, riku.voipio@iki.fi,\n\trichard.henderson@linaro.org, laurent@vivier.eu,\n\tarmbru@redhat.com, arikalo@wavecomp.com,\n\tphilippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com,\n\tpjovanovic@wavecomp.com, aurelien@aurel32.net", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Yongbok Kim <yongbok.kim@mips.com>\n\nAdd emulation of various nanoMIPS load and store instructions.\n\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nReviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>\nSigned-off-by: Yongbok Kim <yongbok.kim@mips.com>\nSigned-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>\nSigned-off-by: Stefan Markovic <smarkovic@wavecomp.com>\n---\n target/mips/translate.c | 277 ++++++++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 277 insertions(+)", "diff": "diff --git a/target/mips/translate.c b/target/mips/translate.c\nindex 715798c..cf8b748 100644\n--- a/target/mips/translate.c\n+++ b/target/mips/translate.c\n@@ -17713,10 +17713,287 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)\n }\n break;\n case NM_P_GP_BH:\n+ {\n+ uint32_t u = extract32(ctx->opcode, 0, 18);\n+\n+ switch (extract32(ctx->opcode, 18, 3)) {\n+ case NM_LBGP:\n+ gen_ld(ctx, OPC_LB, rt, 28, u);\n+ break;\n+ case NM_SBGP:\n+ gen_st(ctx, OPC_SB, rt, 28, u);\n+ break;\n+ case NM_LBUGP:\n+ gen_ld(ctx, OPC_LBU, rt, 28, u);\n+ break;\n+ case NM_ADDIUGP_B:\n+ if (rt != 0) {\n+ gen_op_addr_addi(ctx, cpu_gpr[rt], cpu_gpr[28], u);\n+ }\n+ break;\n+ case NM_P_GP_LH:\n+ u &= ~1;\n+ switch (ctx->opcode & 1) {\n+ case NM_LHGP:\n+ gen_ld(ctx, OPC_LH, rt, 28, u);\n+ break;\n+ case NM_LHUGP:\n+ gen_ld(ctx, OPC_LHU, rt, 28, u);\n+ break;\n+ }\n+ break;\n+ case NM_P_GP_SH:\n+ u &= ~1;\n+ switch (ctx->opcode & 1) {\n+ case NM_SHGP:\n+ gen_st(ctx, OPC_SH, rt, 28, u);\n+ break;\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n+ break;\n+ case NM_P_GP_CP1:\n+ u &= ~0x3;\n+ switch (ctx->opcode & 0x3) {\n+ case NM_LWC1GP:\n+ gen_cop1_ldst(ctx, OPC_LWC1, rt, 28, u);\n+ break;\n+ case NM_LDC1GP:\n+ gen_cop1_ldst(ctx, OPC_LDC1, rt, 28, u);\n+ break;\n+ case NM_SWC1GP:\n+ gen_cop1_ldst(ctx, OPC_SWC1, rt, 28, u);\n+ break;\n+ case NM_SDC1GP:\n+ gen_cop1_ldst(ctx, OPC_SDC1, rt, 28, u);\n+ break;\n+ }\n+ break;\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n+ }\n break;\n case NM_P_LS_U12:\n+ {\n+ uint32_t u = extract32(ctx->opcode, 0, 12);\n+\n+ switch (extract32(ctx->opcode, 12, 4)) {\n+ case NM_P_PREFU12:\n+ if (rt == 31) {\n+ /* SYNCI */\n+ /* Break the TB to be able to sync copied instructions\n+ immediately */\n+ ctx->base.is_jmp = DISAS_STOP;\n+ } else {\n+ /* PREF */\n+ /* Treat as NOP. */\n+ }\n+ break;\n+ case NM_LB:\n+ gen_ld(ctx, OPC_LB, rt, rs, u);\n+ break;\n+ case NM_LH:\n+ gen_ld(ctx, OPC_LH, rt, rs, u);\n+ break;\n+ case NM_LW:\n+ gen_ld(ctx, OPC_LW, rt, rs, u);\n+ break;\n+ case NM_LBU:\n+ gen_ld(ctx, OPC_LBU, rt, rs, u);\n+ break;\n+ case NM_LHU:\n+ gen_ld(ctx, OPC_LHU, rt, rs, u);\n+ break;\n+ case NM_SB:\n+ gen_st(ctx, OPC_SB, rt, rs, u);\n+ break;\n+ case NM_SH:\n+ gen_st(ctx, OPC_SH, rt, rs, u);\n+ break;\n+ case NM_SW:\n+ gen_st(ctx, OPC_SW, rt, rs, u);\n+ break;\n+ case NM_LWC1:\n+ gen_cop1_ldst(ctx, OPC_LWC1, rt, rs, u);\n+ break;\n+ case NM_LDC1:\n+ gen_cop1_ldst(ctx, OPC_LDC1, rt, rs, u);\n+ break;\n+ case NM_SWC1:\n+ gen_cop1_ldst(ctx, OPC_SWC1, rt, rs, u);\n+ break;\n+ case NM_SDC1:\n+ gen_cop1_ldst(ctx, OPC_SDC1, rt, rs, u);\n+ break;\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n+ }\n break;\n case NM_P_LS_S9:\n+ {\n+ int32_t s = (sextract32(ctx->opcode, 15, 1) << 8) |\n+ extract32(ctx->opcode, 0, 8);\n+\n+ switch (extract32(ctx->opcode, 8, 3)) {\n+ case NM_P_LS_S0:\n+ switch (extract32(ctx->opcode, 11, 4)) {\n+ case NM_LBS9:\n+ gen_ld(ctx, OPC_LB, rt, rs, s);\n+ break;\n+ case NM_LHS9:\n+ gen_ld(ctx, OPC_LH, rt, rs, s);\n+ break;\n+ case NM_LWS9:\n+ gen_ld(ctx, OPC_LW, rt, rs, s);\n+ break;\n+ case NM_LBUS9:\n+ gen_ld(ctx, OPC_LBU, rt, rs, s);\n+ break;\n+ case NM_LHUS9:\n+ gen_ld(ctx, OPC_LHU, rt, rs, s);\n+ break;\n+ case NM_SBS9:\n+ gen_st(ctx, OPC_SB, rt, rs, s);\n+ break;\n+ case NM_SHS9:\n+ gen_st(ctx, OPC_SH, rt, rs, s);\n+ break;\n+ case NM_SWS9:\n+ gen_st(ctx, OPC_SW, rt, rs, s);\n+ break;\n+ case NM_LWC1S9:\n+ gen_cop1_ldst(ctx, OPC_LWC1, rt, rs, s);\n+ break;\n+ case NM_LDC1S9:\n+ gen_cop1_ldst(ctx, OPC_LDC1, rt, rs, s);\n+ break;\n+ case NM_SWC1S9:\n+ gen_cop1_ldst(ctx, OPC_SWC1, rt, rs, s);\n+ break;\n+ case NM_SDC1S9:\n+ gen_cop1_ldst(ctx, OPC_SDC1, rt, rs, s);\n+ break;\n+ case NM_P_PREFS9:\n+ if (rt == 31) {\n+ /* SYNCI */\n+ /* Break the TB to be able to sync copied instructions\n+ immediately */\n+ ctx->base.is_jmp = DISAS_STOP;\n+ } else {\n+ /* PREF */\n+ /* Treat as NOP. */\n+ }\n+ break;\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n+ break;\n+ case NM_P_LS_S1:\n+ switch (extract32(ctx->opcode, 11, 4)) {\n+ case NM_UALH:\n+ case NM_UASH:\n+ {\n+ TCGv t0 = tcg_temp_new();\n+ TCGv t1 = tcg_temp_new();\n+\n+ gen_base_offset_addr(ctx, t0, rs, s);\n+\n+ switch (extract32(ctx->opcode, 11, 4)) {\n+ case NM_UALH:\n+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW |\n+ MO_UNALN);\n+ gen_store_gpr(t0, rt);\n+ break;\n+ case NM_UASH:\n+ gen_load_gpr(t1, rt);\n+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUW |\n+ MO_UNALN);\n+ break;\n+ }\n+ tcg_temp_free(t0);\n+ tcg_temp_free(t1);\n+ }\n+ break;\n+ case NM_P_LL:\n+ switch (ctx->opcode & 0x03) {\n+ case NM_LL:\n+ gen_ld(ctx, OPC_LL, rt, rs, s);\n+ break;\n+ case NM_LLWP:\n+ break;\n+ }\n+ break;\n+ case NM_P_SC:\n+ switch (ctx->opcode & 0x03) {\n+ case NM_SC:\n+ gen_st_cond(ctx, OPC_SC, rt, rs, s);\n+ break;\n+ case NM_SCWP:\n+ break;\n+ }\n+ break;\n+ case NM_CACHE:\n+ check_cp0_enabled(ctx);\n+ if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) {\n+ gen_cache_operation(ctx, rt, rs, s);\n+ }\n+ break;\n+ }\n+ break;\n+ case NM_P_LS_WM:\n+ case NM_P_LS_UAWM:\n+ {\n+ int count = extract32(ctx->opcode, 12, 3);\n+ int counter = 0;\n+\n+ offset = sextract32(ctx->opcode, 15, 1) << 8 |\n+ extract32(ctx->opcode, 0, 8);\n+ TCGv va = tcg_temp_new();\n+ TCGv t1 = tcg_temp_new();\n+ TCGMemOp memop = (extract32(ctx->opcode, 8, 3)) ==\n+ NM_P_LS_UAWM ? MO_UNALN : 0;\n+\n+ count = (count == 0) ? 8 : count;\n+ while (counter != count) {\n+ int this_rt = ((rt + counter) & 0x1f) | (rt & 0x10);\n+ int this_offset = offset + (counter << 2);\n+\n+ gen_base_offset_addr(ctx, va, rs, this_offset);\n+\n+ switch (extract32(ctx->opcode, 11, 1)) {\n+ case NM_LWM:\n+ tcg_gen_qemu_ld_tl(t1, va, ctx->mem_idx,\n+ memop | MO_TESL);\n+ gen_store_gpr(t1, this_rt);\n+ if ((this_rt == rs) &&\n+ (counter != (count - 1))) {\n+ /* UNPREDICTABLE */\n+ }\n+ break;\n+ case NM_SWM:\n+ this_rt = (rt == 0) ? 0 : this_rt;\n+ gen_load_gpr(t1, this_rt);\n+ tcg_gen_qemu_st_tl(t1, va, ctx->mem_idx,\n+ memop | MO_TEUL);\n+ break;\n+ }\n+ counter++;\n+ }\n+ tcg_temp_free(va);\n+ tcg_temp_free(t1);\n+ }\n+ break;\n+ default:\n+ generate_exception_end(ctx, EXCP_RI);\n+ break;\n+ }\n+ }\n break;\n case NM_MOVE_BALC:\n break;\n", "prefixes": [ "v7", "35/80" ] }