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GET /api/patches/954008/?format=api
{ "id": 954008, "url": "http://patchwork.ozlabs.org/api/patches/954008/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1533574847-19294-16-git-send-email-aleksandar.markovic@rt-rk.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1533574847-19294-16-git-send-email-aleksandar.markovic@rt-rk.com>", "list_archive_url": null, "date": "2018-08-06T16:59:42", "name": "[v7,15/80] target/mips: Add nanoMIPS base instruction set opcodes", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "3097b058d0d7f2afae918a6f8d560737ec921dbf", "submitter": { "id": 68635, "url": "http://patchwork.ozlabs.org/api/people/68635/?format=api", "name": "Aleksandar Markovic", "email": "aleksandar.markovic@rt-rk.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1533574847-19294-16-git-send-email-aleksandar.markovic@rt-rk.com/mbox/", "series": [ { "id": 59520, "url": "http://patchwork.ozlabs.org/api/series/59520/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=59520", "date": "2018-08-06T16:59:27", "name": "Add nanoMIPS support to QEMU", "version": 7, "mbox": "http://patchwork.ozlabs.org/series/59520/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/954008/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/954008/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=none (p=none dis=none) header.from=rt-rk.com" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 41kkhB652lz9ryt\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 7 Aug 2018 03:11:22 +1000 (AEST)", "from localhost ([::1]:35213 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1fmj2O-0001ig-Cy\n\tfor incoming@patchwork.ozlabs.org; Mon, 06 Aug 2018 13:11:20 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:54217)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <aleksandar.markovic@rt-rk.com>) id 1fmiyJ-0006YT-0h\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:07:08 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <aleksandar.markovic@rt-rk.com>) id 1fmiyG-0007Lv-5n\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:07:06 -0400", "from mx2.rt-rk.com ([89.216.37.149]:46448 helo=mail.rt-rk.com)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <aleksandar.markovic@rt-rk.com>)\n\tid 1fmiyF-0007L1-KW\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:07:04 -0400", "from localhost (localhost [127.0.0.1])\n\tby mail.rt-rk.com (Postfix) with ESMTP id 5770C1A209F;\n\tMon, 6 Aug 2018 19:07:02 +0200 (CEST)", "from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local\n\t[10.10.13.43])\n\tby mail.rt-rk.com (Postfix) with ESMTPSA id 24C651A209A;\n\tMon, 6 Aug 2018 19:07:02 +0200 (CEST)" ], "X-Virus-Scanned": "amavisd-new at rt-rk.com", "From": "Aleksandar Markovic <aleksandar.markovic@rt-rk.com>", "To": "qemu-devel@nongnu.org", "Date": "Mon, 6 Aug 2018 18:59:42 +0200", "Message-Id": "<1533574847-19294-16-git-send-email-aleksandar.markovic@rt-rk.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1533574847-19294-1-git-send-email-aleksandar.markovic@rt-rk.com>", "References": "<1533574847-19294-1-git-send-email-aleksandar.markovic@rt-rk.com>", "X-detected-operating-system": "by eggs.gnu.org: GNU/Linux 3.x [fuzzy]", "X-Received-From": "89.216.37.149", "Subject": "[Qemu-devel] [PATCH v7 15/80] target/mips: Add nanoMIPS base\n\tinstruction set opcodes", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, thuth@redhat.com, pburton@wavecomp.com,\n\tsmarkovic@wavecomp.com, riku.voipio@iki.fi,\n\trichard.henderson@linaro.org, laurent@vivier.eu,\n\tarmbru@redhat.com, arikalo@wavecomp.com,\n\tphilippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com,\n\tpjovanovic@wavecomp.com, aurelien@aurel32.net", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Yongbok Kim <yongbok.kim@mips.com>\n\nAdd nanoMIPS opcodes. nanoMIPS instruction are organized by so-called\ninstruction pools. Each pool contains a set of opcodes, that in turn\ncan be instruction opcodes or instruction pool opcodes.\n\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nSigned-off-by: Yongbok Kim <yongbok.kim@mips.com>\nSigned-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>\nSigned-off-by: Stefan Markovic <smarkovic@wavecomp.com>\n---\n target/mips/translate.c | 670 ++++++++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 670 insertions(+)", "diff": "diff --git a/target/mips/translate.c b/target/mips/translate.c\nindex bc1f21f..bbe8b8a 100644\n--- a/target/mips/translate.c\n+++ b/target/mips/translate.c\n@@ -15656,6 +15656,676 @@ static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx)\n return 2;\n }\n \n+/*\n+ *\n+ * nanoMIPS opcodes\n+ *\n+ */\n+\n+/* MAJOR, P16, and P32 pools opcodes */\n+enum {\n+ NM_P_ADDIU = 0x00,\n+ NM_ADDIUPC = 0x01,\n+ NM_MOVE_BALC = 0x02,\n+ NM_P16_MV = 0x04,\n+ NM_LW16 = 0x05,\n+ NM_BC16 = 0x06,\n+ NM_P16_SR = 0x07,\n+\n+ NM_POOL32A = 0x08,\n+ NM_P_BAL = 0x0a,\n+ NM_P16_SHIFT = 0x0c,\n+ NM_LWSP16 = 0x0d,\n+ NM_BALC16 = 0x0e,\n+ NM_P16_4X4 = 0x0f,\n+\n+ NM_P_GP_W = 0x10,\n+ NM_P_GP_BH = 0x11,\n+ NM_P_J = 0x12,\n+ NM_P16C = 0x14,\n+ NM_LWGP16 = 0x15,\n+ NM_P16_LB = 0x17,\n+\n+ NM_P48I = 0x18,\n+ NM_P16_A1 = 0x1c,\n+ NM_LW4X4 = 0x1d,\n+ NM_P16_LH = 0x1f,\n+\n+ NM_P_U12 = 0x20,\n+ NM_P_LS_U12 = 0x21,\n+ NM_P_BR1 = 0x22,\n+ NM_P16_A2 = 0x24,\n+ NM_SW16 = 0x25,\n+ NM_BEQZC16 = 0x26,\n+\n+ NM_POOL32F = 0x28,\n+ NM_P_LS_S9 = 0x29,\n+ NM_P_BR2 = 0x2a,\n+\n+ NM_P16_ADDU = 0x2c,\n+ NM_SWSP16 = 0x2d,\n+ NM_BNEZC16 = 0x2e,\n+ NM_MOVEP = 0x2f,\n+\n+ NM_POOL32S = 0x30,\n+ NM_P_BRI = 0x32,\n+ NM_LI16 = 0x34,\n+ NM_SWGP16 = 0x35,\n+ NM_P16_BR = 0x36,\n+\n+ NM_P_LUI = 0x38,\n+ NM_ANDI16 = 0x3c,\n+ NM_SW4X4 = 0x3d,\n+ NM_MOVEPREV = 0x3f,\n+};\n+\n+/* POOL32A instruction pool */\n+enum {\n+ NM_POOL32A0 = 0x00,\n+ NM_SPECIAL2 = 0x01,\n+ NM_COP2_1 = 0x02,\n+ NM_UDI = 0x03,\n+ NM_POOL32A5 = 0x05,\n+ NM_POOL32A7 = 0x07,\n+};\n+\n+/* P.GP.W instruction pool */\n+enum {\n+ NM_ADDIUGP_W = 0x00,\n+ NM_LWGP = 0x02,\n+ NM_SWGP = 0x03,\n+};\n+\n+/* P48I instruction pool */\n+enum {\n+ NM_LI48 = 0x00,\n+ NM_ADDIU48 = 0x01,\n+ NM_ADDIUGP48 = 0x02,\n+ NM_ADDIUPC48 = 0x03,\n+ NM_LWPC48 = 0x0b,\n+ NM_SWPC48 = 0x0f,\n+};\n+\n+/* P.U12 instruction pool */\n+enum {\n+ NM_ORI = 0x00,\n+ NM_XORI = 0x01,\n+ NM_ANDI = 0x02,\n+ NM_P_SR = 0x03,\n+ NM_SLTI = 0x04,\n+ NM_SLTIU = 0x05,\n+ NM_SEQI = 0x06,\n+ NM_ADDIUNEG = 0x08,\n+ NM_P_SHIFT = 0x0c,\n+ NM_P_ROTX = 0x0d,\n+ NM_P_INS = 0x0e,\n+ NM_P_EXT = 0x0f,\n+};\n+\n+/* POOL32F instruction pool */\n+enum {\n+ NM_POOL32F_0 = 0x00,\n+ NM_POOL32F_3 = 0x03,\n+ NM_POOL32F_5 = 0x05,\n+};\n+\n+/* POOL32S instruction pool */\n+enum {\n+ NM_POOL32S_0 = 0x00,\n+ NM_POOL32S_4 = 0x04,\n+};\n+\n+/* P.LUI instruction pool */\n+enum {\n+ NM_LUI = 0x00,\n+ NM_ALUIPC = 0x01,\n+};\n+\n+/* P.GP.BH instruction pool */\n+enum {\n+ NM_LBGP = 0x00,\n+ NM_SBGP = 0x01,\n+ NM_LBUGP = 0x02,\n+ NM_ADDIUGP_B = 0x03,\n+ NM_P_GP_LH = 0x04,\n+ NM_P_GP_SH = 0x05,\n+ NM_P_GP_CP1 = 0x06,\n+};\n+\n+/* P.LS.U12 instruction pool */\n+enum {\n+ NM_LB = 0x00,\n+ NM_SB = 0x01,\n+ NM_LBU = 0x02,\n+ NM_P_PREFU12 = 0x03,\n+ NM_LH = 0x04,\n+ NM_SH = 0x05,\n+ NM_LHU = 0x06,\n+ NM_LWU = 0x07,\n+ NM_LW = 0x08,\n+ NM_SW = 0x09,\n+ NM_LWC1 = 0x0a,\n+ NM_SWC1 = 0x0b,\n+ NM_LDC1 = 0x0e,\n+ NM_SDC1 = 0x0f,\n+};\n+\n+/* P.LS.S9 instruction pool */\n+enum {\n+ NM_P_LS_S0 = 0x00,\n+ NM_P_LS_S1 = 0x01,\n+ NM_P_LS_E0 = 0x02,\n+ NM_P_LS_WM = 0x04,\n+ NM_P_LS_UAWM = 0x05,\n+};\n+\n+/* P.BAL instruction pool */\n+enum {\n+ NM_BC = 0x00,\n+ NM_BALC = 0x01,\n+};\n+\n+/* P.J instruction pool */\n+enum {\n+ NM_JALRC = 0x00,\n+ NM_JALRC_HB = 0x01,\n+ NM_P_BALRSC = 0x08,\n+};\n+\n+/* P.BR1 instruction pool */\n+enum {\n+ NM_BEQC = 0x00,\n+ NM_P_BR3A = 0x01,\n+ NM_BGEC = 0x02,\n+ NM_BGEUC = 0x03,\n+};\n+\n+/* P.BR2 instruction pool */\n+enum {\n+ NM_BNEC = 0x00,\n+ NM_BLTC = 0x02,\n+ NM_BLTUC = 0x03,\n+};\n+\n+/* P.BRI instruction pool */\n+enum {\n+ NM_BEQIC = 0x00,\n+ NM_BBEQZC = 0x01,\n+ NM_BGEIC = 0x02,\n+ NM_BGEIUC = 0x03,\n+ NM_BNEIC = 0x04,\n+ NM_BBNEZC = 0x05,\n+ NM_BLTIC = 0x06,\n+ NM_BLTIUC = 0x07,\n+};\n+\n+/* P16.SHIFT instruction pool */\n+enum {\n+ NM_SLL16 = 0x00,\n+ NM_SRL16 = 0x01,\n+};\n+\n+/* POOL16C instruction pool */\n+enum {\n+ NM_POOL16C_0 = 0x00,\n+ NM_LWXS16 = 0x01,\n+};\n+\n+/* P16.A1 instruction pool */\n+enum {\n+ NM_ADDIUR1SP = 0x01,\n+};\n+\n+/* P16.A2 instruction pool */\n+enum {\n+ NM_ADDIUR2 = 0x00,\n+ NM_P_ADDIURS5 = 0x01,\n+};\n+\n+/* P16.ADDU instruction pool */\n+enum {\n+ NM_ADDU16 = 0x00,\n+ NM_SUBU16 = 0x01,\n+};\n+\n+/* P16.SR instruction pool */\n+enum {\n+ NM_SAVE16 = 0x00,\n+ NM_RESTORE_JRC16 = 0x01,\n+};\n+\n+/* P16.4X4 instruction pool */\n+enum {\n+ NM_ADDU4X4 = 0x00,\n+ NM_MUL4X4 = 0x01,\n+};\n+\n+/* P16.LB instruction pool */\n+enum {\n+ NM_LB16 = 0x00,\n+ NM_SB16 = 0x01,\n+ NM_LBU16 = 0x02,\n+};\n+\n+/* P16.LH instruction pool */\n+enum {\n+ NM_LH16 = 0x00,\n+ NM_SH16 = 0x01,\n+ NM_LHU16 = 0x02,\n+};\n+\n+/* P.RI instruction pool */\n+enum {\n+ NM_SIGRIE = 0x00,\n+ NM_P_SYSCALL = 0x01,\n+ NM_BREAK = 0x02,\n+ NM_SDBBP = 0x03,\n+};\n+\n+/* POOL32A0 instruction pool */\n+enum {\n+ NM_P_TRAP = 0x00,\n+ NM_SEB = 0x01,\n+ NM_SLLV = 0x02,\n+ NM_MUL = 0x03,\n+ NM_MFC0 = 0x06,\n+ NM_MFHC0 = 0x07,\n+ NM_SEH = 0x09,\n+ NM_SRLV = 0x0a,\n+ NM_MUH = 0x0b,\n+ NM_MTC0 = 0x0e,\n+ NM_MTHC0 = 0x0f,\n+ NM_SRAV = 0x12,\n+ NM_MULU = 0x13,\n+ NM_ROTRV = 0x1a,\n+ NM_MUHU = 0x1b,\n+ NM_ADD = 0x22,\n+ NM_DIV = 0x23,\n+ NM_ADDU = 0x2a,\n+ NM_MOD = 0x2b,\n+ NM_SUB = 0x32,\n+ NM_DIVU = 0x33,\n+ NM_RDHWR = 0x38,\n+ NM_SUBU = 0x3a,\n+ NM_MODU = 0x3b,\n+ NM_P_CMOVE = 0x42,\n+ NM_FORK = 0x45,\n+ NM_MFTR = 0x46,\n+ NM_MFHTR = 0x47,\n+ NM_AND = 0x4a,\n+ NM_YIELD = 0x4d,\n+ NM_MTTR = 0x4e,\n+ NM_MTHTR = 0x4f,\n+ NM_OR = 0x52,\n+ NM_D_E_MT_VPE = 0x56,\n+ NM_NOR = 0x5a,\n+ NM_XOR = 0x62,\n+ NM_SLT = 0x6a,\n+ NM_P_SLTU = 0x72,\n+ NM_SOV = 0x7a,\n+};\n+\n+/* POOL32A7 instruction pool */\n+enum {\n+ NM_P_LSX = 0x00,\n+ NM_LSA = 0x01,\n+ NM_EXTW = 0x03,\n+ NM_POOL32AXF = 0x07,\n+};\n+\n+/* P.SR instruction pool */\n+enum {\n+ NM_PP_SR = 0x00,\n+ NM_P_SR_F = 0x01,\n+};\n+\n+/* P.SHIFT instruction pool */\n+enum {\n+ NM_P_SLL = 0x00,\n+ NM_SRL = 0x02,\n+ NM_SRA = 0x04,\n+ NM_ROTR = 0x06,\n+};\n+\n+/* P.ROTX instruction pool */\n+enum {\n+ NM_ROTX = 0x00,\n+};\n+\n+/* P.INS instruction pool */\n+enum {\n+ NM_INS = 0x00,\n+};\n+\n+/* P.EXT instruction pool */\n+enum {\n+ NM_EXT = 0x00,\n+};\n+\n+/* POOL32F_0 (fmt) instruction pool */\n+enum {\n+ NM_RINT_S = 0x04,\n+ NM_RINT_D = 0x44,\n+ NM_ADD_S = 0x06,\n+ NM_SELEQZ_S = 0x07,\n+ NM_SELEQZ_D = 0x47,\n+ NM_CLASS_S = 0x0c,\n+ NM_CLASS_D = 0x4c,\n+ NM_SUB_S = 0x0e,\n+ NM_SELNEZ_S = 0x0f,\n+ NM_SELNEZ_D = 0x4f,\n+ NM_MUL_S = 0x16,\n+ NM_SEL_S = 0x17,\n+ NM_SEL_D = 0x57,\n+ NM_DIV_S = 0x1e,\n+ NM_ADD_D = 0x26,\n+ NM_SUB_D = 0x2e,\n+ NM_MUL_D = 0x36,\n+ NM_MADDF_S = 0x37,\n+ NM_MADDF_D = 0x77,\n+ NM_DIV_D = 0x3e,\n+ NM_MSUBF_S = 0x3f,\n+ NM_MSUBF_D = 0x7f,\n+};\n+\n+/* POOL32F_3 instruction pool */\n+enum {\n+ NM_MIN_FMT = 0x00,\n+ NM_MAX_FMT = 0x01,\n+ NM_MINA_FMT = 0x04,\n+ NM_MAXA_FMT = 0x05,\n+ NM_POOL32FXF = 0x07,\n+};\n+\n+/* POOL32F_5 instruction pool */\n+enum {\n+ NM_CMP_CONDN_S = 0x00,\n+ NM_CMP_CONDN_D = 0x02,\n+};\n+\n+/* P.GP.LH instruction pool */\n+enum {\n+ NM_LHGP = 0x00,\n+ NM_LHUGP = 0x01,\n+};\n+\n+/* P.GP.SH instruction pool */\n+enum {\n+ NM_SHGP = 0x00,\n+};\n+\n+/* P.GP.CP1 instruction pool */\n+enum {\n+ NM_LWC1GP = 0x00,\n+ NM_SWC1GP = 0x01,\n+ NM_LDC1GP = 0x02,\n+ NM_SDC1GP = 0x03,\n+};\n+\n+/* P.LS.S0 instruction pool */\n+enum {\n+ NM_LBS9 = 0x00,\n+ NM_LHS9 = 0x04,\n+ NM_LWS9 = 0x08,\n+ NM_LDS9 = 0x0c,\n+\n+ NM_SBS9 = 0x01,\n+ NM_SHS9 = 0x05,\n+ NM_SWS9 = 0x09,\n+ NM_SDS9 = 0x0d,\n+\n+ NM_LBUS9 = 0x02,\n+ NM_LHUS9 = 0x06,\n+ NM_LWC1S9 = 0x0a,\n+ NM_LDC1S9 = 0x0e,\n+\n+ NM_P_PREFS9 = 0x03,\n+ NM_LWUS9 = 0x07,\n+ NM_SWC1S9 = 0x0b,\n+ NM_SDC1S9 = 0x0f,\n+};\n+\n+/* P.LS.S1 instruction pool */\n+enum {\n+ NM_ASET_ACLR = 0x02,\n+ NM_UALH = 0x04,\n+ NM_UASH = 0x05,\n+ NM_CACHE = 0x07,\n+ NM_P_LL = 0x0a,\n+ NM_P_SC = 0x0b,\n+};\n+\n+/* P.LS.WM instruction pool */\n+enum {\n+ NM_LWM = 0x00,\n+ NM_SWM = 0x01,\n+};\n+\n+/* P.LS.UAWM instruction pool */\n+enum {\n+ NM_UALWM = 0x00,\n+ NM_UASWM = 0x01,\n+};\n+\n+/* P.BR3A instruction pool */\n+enum {\n+ NM_BC1EQZC = 0x00,\n+ NM_BC1NEZC = 0x01,\n+ NM_BC2EQZC = 0x02,\n+ NM_BC2NEZC = 0x03,\n+ NM_BPOSGE32C = 0x04,\n+};\n+\n+/* P16.RI instruction pool */\n+enum {\n+ NM_P16_SYSCALL = 0x01,\n+ NM_BREAK16 = 0x02,\n+ NM_SDBBP16 = 0x03,\n+};\n+\n+/* POOL16C_0 instruction pool */\n+enum {\n+ NM_POOL16C_00 = 0x00,\n+};\n+\n+/* P16.JRC instruction pool */\n+enum {\n+ NM_JRC = 0x00,\n+ NM_JALRC16 = 0x01,\n+};\n+\n+/* P.SYSCALL instruction pool */\n+enum {\n+ NM_SYSCALL = 0x00,\n+ NM_HYPCALL = 0x01,\n+};\n+\n+/* P.TRAP instruction pool */\n+enum {\n+ NM_TEQ = 0x00,\n+ NM_TNE = 0x01,\n+};\n+\n+/* P.CMOVE instruction pool */\n+enum {\n+ NM_MOVZ = 0x00,\n+ NM_MOVN = 0x01,\n+};\n+\n+/* POOL32Axf instruction pool */\n+enum {\n+ NM_POOL32AXF_4 = 0x04,\n+ NM_POOL32AXF_5 = 0x05,\n+};\n+\n+/* POOL32Axf_{4, 5} instruction pool */\n+enum {\n+ NM_CLO = 0x25,\n+ NM_CLZ = 0x2d,\n+\n+ NM_TLBP = 0x01,\n+ NM_TLBR = 0x09,\n+ NM_TLBWI = 0x11,\n+ NM_TLBWR = 0x19,\n+ NM_TLBINV = 0x03,\n+ NM_TLBINVF = 0x0b,\n+ NM_DI = 0x23,\n+ NM_EI = 0x2b,\n+ NM_RDPGPR = 0x70,\n+ NM_WRPGPR = 0x78,\n+ NM_WAIT = 0x61,\n+ NM_DERET = 0x71,\n+ NM_ERETX = 0x79,\n+};\n+\n+/* PP.SR instruction pool */\n+enum {\n+ NM_SAVE = 0x00,\n+ NM_RESTORE = 0x02,\n+ NM_RESTORE_JRC = 0x03,\n+};\n+\n+/* P.SR.F instruction pool */\n+enum {\n+ NM_SAVEF = 0x00,\n+ NM_RESTOREF = 0x01,\n+};\n+\n+/* P16.SYSCALL instruction pool */\n+enum {\n+ NM_SYSCALL16 = 0x00,\n+ NM_HYPCALL16 = 0x01,\n+};\n+\n+/* POOL16C_00 instruction pool */\n+enum {\n+ NM_NOT16 = 0x00,\n+ NM_XOR16 = 0x01,\n+ NM_AND16 = 0x02,\n+ NM_OR16 = 0x03,\n+};\n+\n+/* PP.LSX and PP.LSXS instruction pool */\n+enum {\n+ NM_LBX = 0x00,\n+ NM_LHX = 0x04,\n+ NM_LWX = 0x08,\n+ NM_LDX = 0x0c,\n+\n+ NM_SBX = 0x01,\n+ NM_SHX = 0x05,\n+ NM_SWX = 0x09,\n+ NM_SDX = 0x0d,\n+\n+ NM_LBUX = 0x02,\n+ NM_LHUX = 0x06,\n+ NM_LWC1X = 0x0a,\n+ NM_LDC1X = 0x0e,\n+\n+ NM_LWUX = 0x07,\n+ NM_SWC1X = 0x0b,\n+ NM_SDC1X = 0x0f,\n+\n+ NM_LHXS = 0x04,\n+ NM_LWXS = 0x08,\n+ NM_LDXS = 0x0c,\n+\n+ NM_SHXS = 0x05,\n+ NM_SWXS = 0x09,\n+ NM_SDXS = 0x0d,\n+\n+ NM_LHUXS = 0x06,\n+ NM_LWC1XS = 0x0a,\n+ NM_LDC1XS = 0x0e,\n+\n+ NM_LWUXS = 0x07,\n+ NM_SWC1XS = 0x0b,\n+ NM_SDC1XS = 0x0f,\n+};\n+\n+/* ERETx instruction pool */\n+enum {\n+ NM_ERET = 0x00,\n+ NM_ERETNC = 0x01,\n+};\n+\n+/* POOL32FxF_{0, 1} insturction pool */\n+enum {\n+ NM_CFC1 = 0x40,\n+ NM_CTC1 = 0x60,\n+ NM_MFC1 = 0x80,\n+ NM_MTC1 = 0xa0,\n+ NM_MFHC1 = 0xc0,\n+ NM_MTHC1 = 0xe0,\n+\n+ NM_CVT_S_PL = 0x84,\n+ NM_CVT_S_PU = 0xa4,\n+\n+ NM_CVT_L_S = 0x004,\n+ NM_CVT_L_D = 0x104,\n+ NM_CVT_W_S = 0x024,\n+ NM_CVT_W_D = 0x124,\n+\n+ NM_RSQRT_S = 0x008,\n+ NM_RSQRT_D = 0x108,\n+\n+ NM_SQRT_S = 0x028,\n+ NM_SQRT_D = 0x128,\n+\n+ NM_RECIP_S = 0x048,\n+ NM_RECIP_D = 0x148,\n+\n+ NM_FLOOR_L_S = 0x00c,\n+ NM_FLOOR_L_D = 0x10c,\n+\n+ NM_FLOOR_W_S = 0x02c,\n+ NM_FLOOR_W_D = 0x12c,\n+\n+ NM_CEIL_L_S = 0x04c,\n+ NM_CEIL_L_D = 0x14c,\n+ NM_CEIL_W_S = 0x06c,\n+ NM_CEIL_W_D = 0x16c,\n+ NM_TRUNC_L_S = 0x08c,\n+ NM_TRUNC_L_D = 0x18c,\n+ NM_TRUNC_W_S = 0x0ac,\n+ NM_TRUNC_W_D = 0x1ac,\n+ NM_ROUND_L_S = 0x0cc,\n+ NM_ROUND_L_D = 0x1cc,\n+ NM_ROUND_W_S = 0x0ec,\n+ NM_ROUND_W_D = 0x1ec,\n+\n+ NM_MOV_S = 0x01,\n+ NM_MOV_D = 0x81,\n+ NM_ABS_S = 0x0d,\n+ NM_ABS_D = 0x8d,\n+ NM_NEG_S = 0x2d,\n+ NM_NEG_D = 0xad,\n+ NM_CVT_D_S = 0x04d,\n+ NM_CVT_D_W = 0x0cd,\n+ NM_CVT_D_L = 0x14d,\n+ NM_CVT_S_D = 0x06d,\n+ NM_CVT_S_W = 0x0ed,\n+ NM_CVT_S_L = 0x16d,\n+};\n+\n+/* P.LL instruction pool */\n+enum {\n+ NM_LL = 0x00,\n+ NM_LLWP = 0x01,\n+};\n+\n+/* P.SC instruction pool */\n+enum {\n+ NM_SC = 0x00,\n+ NM_SCWP = 0x01,\n+};\n+\n+/* P.DVP instruction pool */\n+enum {\n+ NM_DVP = 0x00,\n+ NM_EVP = 0x01,\n+};\n+\n /* SmartMIPS extension to MIPS32 */\n \n #if defined(TARGET_MIPS64)\n", "prefixes": [ "v7", "15/80" ] }