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GET /api/patches/953995/?format=api
{ "id": 953995, "url": "http://patchwork.ozlabs.org/api/patches/953995/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1533574847-19294-6-git-send-email-aleksandar.markovic@rt-rk.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1533574847-19294-6-git-send-email-aleksandar.markovic@rt-rk.com>", "list_archive_url": null, "date": "2018-08-06T16:59:32", "name": "[v7,05/80] target/mips: Update some CP0 registers bit definitions", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "ec9baed74bf40bacb0cbc643b2461a55c99c687e", "submitter": { "id": 68635, "url": "http://patchwork.ozlabs.org/api/people/68635/?format=api", "name": "Aleksandar Markovic", "email": "aleksandar.markovic@rt-rk.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1533574847-19294-6-git-send-email-aleksandar.markovic@rt-rk.com/mbox/", "series": [ { "id": 59520, "url": "http://patchwork.ozlabs.org/api/series/59520/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=59520", "date": "2018-08-06T16:59:27", "name": "Add nanoMIPS support to QEMU", "version": 7, "mbox": "http://patchwork.ozlabs.org/series/59520/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/953995/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/953995/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=none (p=none dis=none) header.from=rt-rk.com" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 41kkWb0HdBz9s3q\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 7 Aug 2018 03:03:55 +1000 (AEST)", "from localhost ([::1]:35167 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1fmivA-0002tl-LZ\n\tfor incoming@patchwork.ozlabs.org; Mon, 06 Aug 2018 13:03:52 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:52813)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <aleksandar.markovic@rt-rk.com>) id 1fmiuK-0002s0-HI\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:03:02 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <aleksandar.markovic@rt-rk.com>) id 1fmiuH-0005JI-S9\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:03:00 -0400", "from mx2.rt-rk.com ([89.216.37.149]:42954 helo=mail.rt-rk.com)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <aleksandar.markovic@rt-rk.com>)\n\tid 1fmiuH-0005Iy-GU\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:02:57 -0400", "from localhost (localhost [127.0.0.1])\n\tby mail.rt-rk.com (Postfix) with ESMTP id 3B3D31A20C6;\n\tMon, 6 Aug 2018 19:02:56 +0200 (CEST)", "from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local\n\t[10.10.13.43])\n\tby mail.rt-rk.com (Postfix) with ESMTPSA id 17D301A209A;\n\tMon, 6 Aug 2018 19:02:56 +0200 (CEST)" ], "X-Virus-Scanned": "amavisd-new at rt-rk.com", "From": "Aleksandar Markovic <aleksandar.markovic@rt-rk.com>", "To": "qemu-devel@nongnu.org", "Date": "Mon, 6 Aug 2018 18:59:32 +0200", "Message-Id": "<1533574847-19294-6-git-send-email-aleksandar.markovic@rt-rk.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1533574847-19294-1-git-send-email-aleksandar.markovic@rt-rk.com>", "References": "<1533574847-19294-1-git-send-email-aleksandar.markovic@rt-rk.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "quoted-printable", "X-detected-operating-system": "by eggs.gnu.org: GNU/Linux 3.x [fuzzy]", "X-Received-From": "89.216.37.149", "Subject": "[Qemu-devel] [PATCH v7 05/80] target/mips: Update some CP0\n\tregisters bit definitions", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, thuth@redhat.com, pburton@wavecomp.com,\n\tsmarkovic@wavecomp.com, riku.voipio@iki.fi,\n\trichard.henderson@linaro.org, laurent@vivier.eu,\n\tarmbru@redhat.com, arikalo@wavecomp.com,\n\tphilippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com,\n\tpjovanovic@wavecomp.com, aurelien@aurel32.net", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Aleksandar Markovic <amarkovic@wavecomp.com>\n\nUpdate CP0 registers Config0, Config1, Config2, Config3,\nConfig4, and Config5 bit definitions.\n\nSome of these bits will be utilized by upcoming nanoMIPS changes.\n\nReviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nSigned-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>\n---\n target/mips/cpu.h | 157 ++++++++++++++++++++++++++++++------------------------\n 1 file changed, 88 insertions(+), 69 deletions(-)", "diff": "diff --git a/target/mips/cpu.h b/target/mips/cpu.h\nindex cfe1735..77c638c 100644\n--- a/target/mips/cpu.h\n+++ b/target/mips/cpu.h\n@@ -388,26 +388,27 @@ struct CPUMIPSState {\n target_ulong CP0_CMGCRBase;\n int32_t CP0_Config0;\n #define CP0C0_M 31\n-#define CP0C0_K23 28\n-#define CP0C0_KU 25\n+#define CP0C0_K23 28 /* 30..28 */\n+#define CP0C0_KU 25 /* 27..25 */\n #define CP0C0_MDU 20\n #define CP0C0_MM 18\n #define CP0C0_BM 16\n+#define CP0C0_Impl 16 /* 24..16 */\n #define CP0C0_BE 15\n-#define CP0C0_AT 13\n-#define CP0C0_AR 10\n-#define CP0C0_MT 7\n+#define CP0C0_AT 13 /* 14..13 */\n+#define CP0C0_AR 10 /* 12..10 */\n+#define CP0C0_MT 7 /* 9..7 */\n #define CP0C0_VI 3\n-#define CP0C0_K0 0\n+#define CP0C0_K0 0 /* 2..0 */\n int32_t CP0_Config1;\n #define CP0C1_M 31\n-#define CP0C1_MMU 25\n-#define CP0C1_IS 22\n-#define CP0C1_IL 19\n-#define CP0C1_IA 16\n-#define CP0C1_DS 13\n-#define CP0C1_DL 10\n-#define CP0C1_DA 7\n+#define CP0C1_MMU 25 /* 30..25 */\n+#define CP0C1_IS 22 /* 24..22 */\n+#define CP0C1_IL 19 /* 21..19 */\n+#define CP0C1_IA 16 /* 18..16 */\n+#define CP0C1_DS 13 /* 15..13 */\n+#define CP0C1_DL 10 /* 12..10 */\n+#define CP0C1_DA 7 /* 9..7 */\n #define CP0C1_C2 6\n #define CP0C1_MD 5\n #define CP0C1_PC 4\n@@ -417,67 +418,85 @@ struct CPUMIPSState {\n #define CP0C1_FP 0\n int32_t CP0_Config2;\n #define CP0C2_M 31\n-#define CP0C2_TU 28\n-#define CP0C2_TS 24\n-#define CP0C2_TL 20\n-#define CP0C2_TA 16\n-#define CP0C2_SU 12\n-#define CP0C2_SS 8\n-#define CP0C2_SL 4\n-#define CP0C2_SA 0\n+#define CP0C2_TU 28 /* 30..28 */\n+#define CP0C2_TS 24 /* 27..24 */\n+#define CP0C2_TL 20 /* 23..20 */\n+#define CP0C2_TA 16 /* 19..16 */\n+#define CP0C2_SU 12 /* 15..12 */\n+#define CP0C2_SS 8 /* 11..8 */\n+#define CP0C2_SL 4 /* 7..4 */\n+#define CP0C2_SA 0 /* 3..0 */\n int32_t CP0_Config3;\n-#define CP0C3_M 31\n-#define CP0C3_BPG 30\n-#define CP0C3_CMGCR 29\n-#define CP0C3_MSAP 28\n-#define CP0C3_BP 27\n-#define CP0C3_BI 26\n-#define CP0C3_SC 25\n-#define CP0C3_IPLW 21\n-#define CP0C3_MMAR 18\n-#define CP0C3_MCU 17\n-#define CP0C3_ISA_ON_EXC 16\n-#define CP0C3_ISA 14\n-#define CP0C3_ULRI 13\n-#define CP0C3_RXI 12\n-#define CP0C3_DSP2P 11\n-#define CP0C3_DSPP 10\n-#define CP0C3_LPA 7\n-#define CP0C3_VEIC 6\n-#define CP0C3_VInt 5\n-#define CP0C3_SP 4\n-#define CP0C3_CDMM 3\n-#define CP0C3_MT 2\n-#define CP0C3_SM 1\n-#define CP0C3_TL 0\n+#define CP0C3_M 31\n+#define CP0C3_BPG 30\n+#define CP0C3_CMGCR 29\n+#define CP0C3_MSAP 28\n+#define CP0C3_BP 27\n+#define CP0C3_BI 26\n+#define CP0C3_SC 25\n+#define CP0C3_PW 24\n+#define CP0C3_VZ 23\n+#define CP0C3_IPLV 21 /* 22..21 */\n+#define CP0C3_MMAR 18 /* 20..18 */\n+#define CP0C3_MCU 17\n+#define CP0C3_ISA_ON_EXC 16\n+#define CP0C3_ISA 14 /* 15..14 */\n+#define CP0C3_ULRI 13\n+#define CP0C3_RXI 12\n+#define CP0C3_DSP2P 11\n+#define CP0C3_DSPP 10\n+#define CP0C3_CTXTC 9\n+#define CP0C3_ITL 8\n+#define CP0C3_LPA 7\n+#define CP0C3_VEIC 6\n+#define CP0C3_VInt 5\n+#define CP0C3_SP 4\n+#define CP0C3_CDMM 3\n+#define CP0C3_MT 2\n+#define CP0C3_SM 1\n+#define CP0C3_TL 0\n int32_t CP0_Config4;\n int32_t CP0_Config4_rw_bitmask;\n-#define CP0C4_M 31\n-#define CP0C4_IE 29\n-#define CP0C4_AE 28\n-#define CP0C4_KScrExist 16\n-#define CP0C4_MMUExtDef 14\n-#define CP0C4_FTLBPageSize 8\n-#define CP0C4_FTLBWays 4\n-#define CP0C4_FTLBSets 0\n-#define CP0C4_MMUSizeExt 0\n+#define CP0C4_M 31\n+#define CP0C4_IE 29 /* 30..29 */\n+#define CP0C4_AE 28\n+#define CP0C4_VTLBSizeExt 24 /* 27..24 */\n+#define CP0C4_KScrExist 16\n+#define CP0C4_MMUExtDef 14\n+#define CP0C4_FTLBPageSize 8 /* 12..8 */\n+/* bit layout if MMUExtDef=1 */\n+#define CP0C4_MMUSizeExt 0 /* 7..0 */\n+/* bit layout if MMUExtDef=2 */\n+#define CP0C4_FTLBWays 4 /* 7..4 */\n+#define CP0C4_FTLBSets 0 /* 3..0 */\n int32_t CP0_Config5;\n int32_t CP0_Config5_rw_bitmask;\n-#define CP0C5_M 31\n-#define CP0C5_K 30\n-#define CP0C5_CV 29\n-#define CP0C5_EVA 28\n-#define CP0C5_MSAEn 27\n-#define CP0C5_XNP 13\n-#define CP0C5_UFE 9\n-#define CP0C5_FRE 8\n-#define CP0C5_VP 7\n-#define CP0C5_SBRI 6\n-#define CP0C5_MVH 5\n-#define CP0C5_LLB 4\n-#define CP0C5_MRP 3\n-#define CP0C5_UFR 2\n-#define CP0C5_NFExists 0\n+#define CP0C5_M 31\n+#define CP0C5_K 30\n+#define CP0C5_CV 29\n+#define CP0C5_EVA 28\n+#define CP0C5_MSAEn 27\n+#define CP0C5_PMJ 23 /* 25..23 */\n+#define CP0C5_WR2 22\n+#define CP0C5_NMS 21\n+#define CP0C5_ULS 20\n+#define CP0C5_XPA 19\n+#define CP0C5_CRCP 18\n+#define CP0C5_MI 17\n+#define CP0C5_GI 15 /* 16..15 */\n+#define CP0C5_CA2 14\n+#define CP0C5_XNP 13\n+#define CP0C5_DEC 11\n+#define CP0C5_L2C 10\n+#define CP0C5_UFE 9\n+#define CP0C5_FRE 8\n+#define CP0C5_VP 7\n+#define CP0C5_SBRI 6\n+#define CP0C5_MVH 5\n+#define CP0C5_LLB 4\n+#define CP0C5_MRP 3\n+#define CP0C5_UFR 2\n+#define CP0C5_NFExists 0\n int32_t CP0_Config6;\n int32_t CP0_Config7;\n uint64_t CP0_MAAR[MIPS_MAAR_MAX];\n", "prefixes": [ "v7", "05/80" ] }