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GET /api/patches/953993/?format=api
{ "id": 953993, "url": "http://patchwork.ozlabs.org/api/patches/953993/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1533574847-19294-3-git-send-email-aleksandar.markovic@rt-rk.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1533574847-19294-3-git-send-email-aleksandar.markovic@rt-rk.com>", "list_archive_url": null, "date": "2018-08-06T16:59:29", "name": "[v7,02/80] target/mips: Avoid case statements formulated by ranges", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "42d67964c1aafbf97fe50e2185819e5c4071e634", "submitter": { "id": 68635, "url": "http://patchwork.ozlabs.org/api/people/68635/?format=api", "name": "Aleksandar Markovic", "email": "aleksandar.markovic@rt-rk.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1533574847-19294-3-git-send-email-aleksandar.markovic@rt-rk.com/mbox/", "series": [ { "id": 59520, "url": "http://patchwork.ozlabs.org/api/series/59520/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=59520", "date": "2018-08-06T16:59:27", "name": "Add nanoMIPS support to QEMU", "version": 7, "mbox": "http://patchwork.ozlabs.org/series/59520/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/953993/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/953993/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=none (p=none dis=none) header.from=rt-rk.com" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 41kkV15B7qz9ryt\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 7 Aug 2018 03:02:33 +1000 (AEST)", "from localhost ([::1]:35164 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1fmitp-00027J-AF\n\tfor incoming@patchwork.ozlabs.org; Mon, 06 Aug 2018 13:02:29 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:52130)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <aleksandar.markovic@rt-rk.com>) id 1fmitB-00026J-Ss\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:01:51 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <aleksandar.markovic@rt-rk.com>) id 1fmit9-00042i-7N\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:01:49 -0400", "from mx2.rt-rk.com ([89.216.37.149]:42692 helo=mail.rt-rk.com)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <aleksandar.markovic@rt-rk.com>)\n\tid 1fmit8-00041F-Ky\n\tfor qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:01:47 -0400", "from localhost (localhost [127.0.0.1])\n\tby mail.rt-rk.com (Postfix) with ESMTP id CC7981A20C6;\n\tMon, 6 Aug 2018 19:01:44 +0200 (CEST)", "from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local\n\t[10.10.13.43])\n\tby mail.rt-rk.com (Postfix) with ESMTPSA id A4A8D1A209A;\n\tMon, 6 Aug 2018 19:01:44 +0200 (CEST)" ], "X-Virus-Scanned": "amavisd-new at rt-rk.com", "From": "Aleksandar Markovic <aleksandar.markovic@rt-rk.com>", "To": "qemu-devel@nongnu.org", "Date": "Mon, 6 Aug 2018 18:59:29 +0200", "Message-Id": "<1533574847-19294-3-git-send-email-aleksandar.markovic@rt-rk.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1533574847-19294-1-git-send-email-aleksandar.markovic@rt-rk.com>", "References": "<1533574847-19294-1-git-send-email-aleksandar.markovic@rt-rk.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "quoted-printable", "X-detected-operating-system": "by eggs.gnu.org: GNU/Linux 3.x [fuzzy]", "X-Received-From": "89.216.37.149", "Subject": "[Qemu-devel] [PATCH v7 02/80] target/mips: Avoid case statements\n\tformulated by ranges", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, thuth@redhat.com, pburton@wavecomp.com,\n\tsmarkovic@wavecomp.com, riku.voipio@iki.fi,\n\trichard.henderson@linaro.org, laurent@vivier.eu,\n\tarmbru@redhat.com, arikalo@wavecomp.com,\n\tphilippe.mathieu.daude@gmail.com, amarkovic@wavecomp.com,\n\tpjovanovic@wavecomp.com, aurelien@aurel32.net", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Aleksandar Markovic <amarkovic@wavecomp.com>\n\nRemove \"range style\" case statements to make code analysis easier.\n\nThis is needed also for some upcoming nanoMIPS-related refactorings.\n\nReviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nSigned-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>\n---\n target/mips/translate.c | 249 ++++++++++++++++++++++++++++++++++++++----------\n 1 file changed, 200 insertions(+), 49 deletions(-)", "diff": "diff --git a/target/mips/translate.c b/target/mips/translate.c\nindex 20b43c0..051dda5 100644\n--- a/target/mips/translate.c\n+++ b/target/mips/translate.c\n@@ -5494,7 +5494,14 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)\n break;\n case 18:\n switch (sel) {\n- case 0 ... 7:\n+ case 0:\n+ case 1:\n+ case 2:\n+ case 3:\n+ case 4:\n+ case 5:\n+ case 6:\n+ case 7:\n gen_helper_1e0i(mfc0_watchlo, arg, sel);\n rn = \"WatchLo\";\n break;\n@@ -5504,7 +5511,14 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)\n break;\n case 19:\n switch (sel) {\n- case 0 ...7:\n+ case 0:\n+ case 1:\n+ case 2:\n+ case 3:\n+ case 4:\n+ case 5:\n+ case 6:\n+ case 7:\n gen_helper_1e0i(mfc0_watchhi, arg, sel);\n rn = \"WatchHi\";\n break;\n@@ -5630,7 +5644,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)\n break;\n case 27:\n switch (sel) {\n- case 0 ... 3:\n+ case 0:\n+ case 1:\n+ case 2:\n+ case 3:\n tcg_gen_movi_tl(arg, 0); /* unimplemented */\n rn = \"CacheErr\";\n break;\n@@ -5701,7 +5718,12 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)\n gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE));\n rn = \"DESAVE\";\n break;\n- case 2 ... 7:\n+ case 2:\n+ case 3:\n+ case 4:\n+ case 5:\n+ case 6:\n+ case 7:\n CP0_CHECK(ctx->kscrexist & (1 << sel));\n tcg_gen_ld_tl(arg, cpu_env,\n offsetof(CPUMIPSState, CP0_KScratch[sel-2]));\n@@ -6167,7 +6189,14 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)\n break;\n case 18:\n switch (sel) {\n- case 0 ... 7:\n+ case 0:\n+ case 1:\n+ case 2:\n+ case 3:\n+ case 4:\n+ case 5:\n+ case 6:\n+ case 7:\n gen_helper_0e1i(mtc0_watchlo, arg, sel);\n rn = \"WatchLo\";\n break;\n@@ -6177,7 +6206,14 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)\n break;\n case 19:\n switch (sel) {\n- case 0 ... 7:\n+ case 0:\n+ case 1:\n+ case 2:\n+ case 3:\n+ case 4:\n+ case 5:\n+ case 6:\n+ case 7:\n gen_helper_0e1i(mtc0_watchhi, arg, sel);\n rn = \"WatchHi\";\n break;\n@@ -6315,7 +6351,10 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)\n break;\n case 27:\n switch (sel) {\n- case 0 ... 3:\n+ case 0:\n+ case 1:\n+ case 2:\n+ case 3:\n /* ignored */\n rn = \"CacheErr\";\n break;\n@@ -6381,7 +6420,12 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)\n gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE));\n rn = \"DESAVE\";\n break;\n- case 2 ... 7:\n+ case 2:\n+ case 3:\n+ case 4:\n+ case 5:\n+ case 6:\n+ case 7:\n CP0_CHECK(ctx->kscrexist & (1 << sel));\n tcg_gen_st_tl(arg, cpu_env,\n offsetof(CPUMIPSState, CP0_KScratch[sel-2]));\n@@ -6842,7 +6886,14 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)\n break;\n case 18:\n switch (sel) {\n- case 0 ... 7:\n+ case 0:\n+ case 1:\n+ case 2:\n+ case 3:\n+ case 4:\n+ case 5:\n+ case 6:\n+ case 7:\n gen_helper_1e0i(dmfc0_watchlo, arg, sel);\n rn = \"WatchLo\";\n break;\n@@ -6852,7 +6903,14 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)\n break;\n case 19:\n switch (sel) {\n- case 0 ... 7:\n+ case 0:\n+ case 1:\n+ case 2:\n+ case 3:\n+ case 4:\n+ case 5:\n+ case 6:\n+ case 7:\n gen_helper_1e0i(mfc0_watchhi, arg, sel);\n rn = \"WatchHi\";\n break;\n@@ -6975,7 +7033,10 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)\n case 27:\n switch (sel) {\n /* ignored */\n- case 0 ... 3:\n+ case 0:\n+ case 1:\n+ case 2:\n+ case 3:\n tcg_gen_movi_tl(arg, 0); /* unimplemented */\n rn = \"CacheErr\";\n break;\n@@ -7040,7 +7101,12 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)\n gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE));\n rn = \"DESAVE\";\n break;\n- case 2 ... 7:\n+ case 2:\n+ case 3:\n+ case 4:\n+ case 5:\n+ case 6:\n+ case 7:\n CP0_CHECK(ctx->kscrexist & (1 << sel));\n tcg_gen_ld_tl(arg, cpu_env,\n offsetof(CPUMIPSState, CP0_KScratch[sel-2]));\n@@ -7497,7 +7563,14 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)\n break;\n case 18:\n switch (sel) {\n- case 0 ... 7:\n+ case 0:\n+ case 1:\n+ case 2:\n+ case 3:\n+ case 4:\n+ case 5:\n+ case 6:\n+ case 7:\n gen_helper_0e1i(mtc0_watchlo, arg, sel);\n rn = \"WatchLo\";\n break;\n@@ -7507,7 +7580,14 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)\n break;\n case 19:\n switch (sel) {\n- case 0 ... 7:\n+ case 0:\n+ case 1:\n+ case 2:\n+ case 3:\n+ case 4:\n+ case 5:\n+ case 6:\n+ case 7:\n gen_helper_0e1i(mtc0_watchhi, arg, sel);\n rn = \"WatchHi\";\n break;\n@@ -7641,7 +7721,10 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)\n break;\n case 27:\n switch (sel) {\n- case 0 ... 3:\n+ case 0:\n+ case 1:\n+ case 2:\n+ case 3:\n /* ignored */\n rn = \"CacheErr\";\n break;\n@@ -7707,7 +7790,12 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)\n gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE));\n rn = \"DESAVE\";\n break;\n- case 2 ... 7:\n+ case 2:\n+ case 3:\n+ case 4:\n+ case 5:\n+ case 6:\n+ case 7:\n CP0_CHECK(ctx->kscrexist & (1 << sel));\n tcg_gen_st_tl(arg, cpu_env,\n offsetof(CPUMIPSState, CP0_KScratch[sel-2]));\n@@ -7843,7 +7931,14 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,\n break;\n case 16:\n switch (sel) {\n- case 0 ... 7:\n+ case 0:\n+ case 1:\n+ case 2:\n+ case 3:\n+ case 4:\n+ case 5:\n+ case 6:\n+ case 7:\n gen_helper_mftc0_configx(t0, cpu_env, tcg_const_tl(sel));\n break;\n default:\n@@ -17231,7 +17326,10 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)\n case OPC_LSA:\n gen_lsa(ctx, op1, rd, rs, rt, extract32(ctx->opcode, 6, 2));\n break;\n- case OPC_MULT ... OPC_DIVU:\n+ case OPC_MULT:\n+ case OPC_MULTU:\n+ case OPC_DIV:\n+ case OPC_DIVU:\n op2 = MASK_R6_MULDIV(ctx->opcode);\n switch (op2) {\n case R6_OPC_MUL:\n@@ -17291,7 +17389,11 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)\n generate_exception_end(ctx, EXCP_RI);\n }\n break;\n- case OPC_DMULT ... OPC_DDIVU:\n+ case OPC_DMULT:\n+ case OPC_DMULTU:\n+ case OPC_DDIV:\n+ case OPC_DDIVU:\n+\n op2 = MASK_R6_MULDIV(ctx->opcode);\n switch (op2) {\n case R6_OPC_DMUL:\n@@ -17370,7 +17472,10 @@ static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx)\n gen_muldiv(ctx, op1, 0, rs, rt);\n break;\n #if defined(TARGET_MIPS64)\n- case OPC_DMULT ... OPC_DDIVU:\n+ case OPC_DMULT:\n+ case OPC_DMULTU:\n+ case OPC_DDIV:\n+ case OPC_DDIVU:\n check_insn(ctx, ISA_MIPS3);\n check_mips_64(ctx);\n gen_muldiv(ctx, op1, 0, rs, rt);\n@@ -17437,7 +17542,10 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)\n break;\n }\n break;\n- case OPC_ADD ... OPC_SUBU:\n+ case OPC_ADD:\n+ case OPC_ADDU:\n+ case OPC_SUB:\n+ case OPC_SUBU:\n gen_arith(ctx, op1, rd, rs, rt);\n break;\n case OPC_SLLV: /* Shifts */\n@@ -17473,7 +17581,11 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)\n case OPC_JALR:\n gen_compute_branch(ctx, op1, 4, rs, rd, sa, 4);\n break;\n- case OPC_TGE ... OPC_TEQ: /* Traps */\n+ case OPC_TGE: /* Traps */\n+ case OPC_TGEU:\n+ case OPC_TLT:\n+ case OPC_TLTU:\n+ case OPC_TEQ:\n case OPC_TNE:\n check_insn(ctx, ISA_MIPS2);\n gen_trap(ctx, op1, rs, rt, -1);\n@@ -17549,7 +17661,10 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)\n break;\n }\n break;\n- case OPC_DADD ... OPC_DSUBU:\n+ case OPC_DADD:\n+ case OPC_DADDU:\n+ case OPC_DSUB:\n+ case OPC_DSUBU:\n check_insn(ctx, ISA_MIPS3);\n check_mips_64(ctx);\n gen_arith(ctx, op1, rd, rs, rt);\n@@ -17607,8 +17722,10 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)\n \n op1 = MASK_SPECIAL2(ctx->opcode);\n switch (op1) {\n- case OPC_MADD ... OPC_MADDU: /* Multiply and add/sub */\n- case OPC_MSUB ... OPC_MSUBU:\n+ case OPC_MADD: /* Multiply and add/sub */\n+ case OPC_MADDU:\n+ case OPC_MSUB:\n+ case OPC_MSUBU:\n check_insn(ctx, ISA_MIPS32);\n gen_muldiv(ctx, op1, rd & 3, rs, rt);\n break;\n@@ -17705,7 +17822,8 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)\n }\n op2 = MASK_BSHFL(ctx->opcode);\n switch (op2) {\n- case OPC_ALIGN ... OPC_ALIGN_END:\n+ case OPC_ALIGN:\n+ case OPC_ALIGN_END:\n gen_align(ctx, OPC_ALIGN, rd, rs, rt, sa & 3);\n break;\n case OPC_BITSWAP:\n@@ -17730,7 +17848,8 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)\n }\n op2 = MASK_DBSHFL(ctx->opcode);\n switch (op2) {\n- case OPC_DALIGN ... OPC_DALIGN_END:\n+ case OPC_DALIGN:\n+ case OPC_DALIGN_END:\n gen_align(ctx, OPC_DALIGN, rd, rs, rt, sa & 7);\n break;\n case OPC_DBITSWAP:\n@@ -17759,9 +17878,12 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)\n \n op1 = MASK_SPECIAL3(ctx->opcode);\n switch (op1) {\n- case OPC_DIV_G_2E ... OPC_DIVU_G_2E:\n- case OPC_MOD_G_2E ... OPC_MODU_G_2E:\n- case OPC_MULT_G_2E ... OPC_MULTU_G_2E:\n+ case OPC_DIV_G_2E:\n+ case OPC_DIVU_G_2E:\n+ case OPC_MOD_G_2E:\n+ case OPC_MODU_G_2E:\n+ case OPC_MULT_G_2E:\n+ case OPC_MULTU_G_2E:\n /* OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have\n * the same mask and op1. */\n if ((ctx->insn_flags & ASE_DSPR2) && (op1 == OPC_MULT_G_2E)) {\n@@ -18025,9 +18147,12 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)\n }\n break;\n #if defined(TARGET_MIPS64)\n- case OPC_DDIV_G_2E ... OPC_DDIVU_G_2E:\n- case OPC_DMULT_G_2E ... OPC_DMULTU_G_2E:\n- case OPC_DMOD_G_2E ... OPC_DMODU_G_2E:\n+ case OPC_DDIV_G_2E:\n+ case OPC_DDIVU_G_2E:\n+ case OPC_DMULT_G_2E:\n+ case OPC_DMULTU_G_2E:\n+ case OPC_DMOD_G_2E:\n+ case OPC_DMODU_G_2E:\n check_insn(ctx, INSN_LOONGSON2E);\n gen_loongson_integer(ctx, op1, rd, rs, rt);\n break;\n@@ -18289,18 +18414,25 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)\n */\n if (ctx->eva) {\n switch (op1) {\n- case OPC_LWLE ... OPC_LWRE:\n+ case OPC_LWLE:\n+ case OPC_LWRE:\n check_insn_opc_removed(ctx, ISA_MIPS32R6);\n /* fall through */\n- case OPC_LBUE ... OPC_LHUE:\n- case OPC_LBE ... OPC_LWE:\n+ case OPC_LBUE:\n+ case OPC_LHUE:\n+ case OPC_LBE:\n+ case OPC_LHE:\n+ case OPC_LLE:\n+ case OPC_LWE:\n check_cp0_enabled(ctx);\n gen_ld(ctx, op1, rt, rs, imm);\n return;\n- case OPC_SWLE ... OPC_SWRE:\n+ case OPC_SWLE:\n+ case OPC_SWRE:\n check_insn_opc_removed(ctx, ISA_MIPS32R6);\n /* fall through */\n- case OPC_SBE ... OPC_SHE:\n+ case OPC_SBE:\n+ case OPC_SHE:\n case OPC_SWE:\n check_cp0_enabled(ctx);\n gen_st(ctx, op1, rt, rs, imm);\n@@ -18332,7 +18464,8 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)\n case OPC_BSHFL:\n op2 = MASK_BSHFL(ctx->opcode);\n switch (op2) {\n- case OPC_ALIGN ... OPC_ALIGN_END:\n+ case OPC_ALIGN:\n+ case OPC_ALIGN_END:\n case OPC_BITSWAP:\n check_insn(ctx, ISA_MIPS32R6);\n decode_opc_special3_r6(env, ctx);\n@@ -18344,8 +18477,12 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)\n }\n break;\n #if defined(TARGET_MIPS64)\n- case OPC_DEXTM ... OPC_DEXT:\n- case OPC_DINSM ... OPC_DINS:\n+ case OPC_DEXTM:\n+ case OPC_DEXTU:\n+ case OPC_DEXT:\n+ case OPC_DINSM:\n+ case OPC_DINSU:\n+ case OPC_DINS:\n check_insn(ctx, ISA_MIPS64R2);\n check_mips_64(ctx);\n gen_bitops(ctx, op1, rt, rs, sa, rd);\n@@ -18353,7 +18490,8 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)\n case OPC_DBSHFL:\n op2 = MASK_DBSHFL(ctx->opcode);\n switch (op2) {\n- case OPC_DALIGN ... OPC_DALIGN_END:\n+ case OPC_DALIGN:\n+ case OPC_DALIGN_END:\n case OPC_DBITSWAP:\n check_insn(ctx, ISA_MIPS32R6);\n decode_opc_special3_r6(env, ctx);\n@@ -19584,7 +19722,12 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)\n gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2, 4);\n }\n break;\n- case OPC_TGEI ... OPC_TEQI: /* REGIMM traps */\n+ case OPC_TGEI: /* REGIMM traps */\n+ case OPC_TGEIU:\n+ case OPC_TLTI:\n+ case OPC_TLTIU:\n+ case OPC_TEQI:\n+\n case OPC_TNEI:\n check_insn(ctx, ISA_MIPS2);\n check_insn_opc_removed(ctx, ISA_MIPS32R6);\n@@ -19759,7 +19902,8 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)\n case OPC_XORI:\n gen_logic_imm(ctx, op, rt, rs, imm);\n break;\n- case OPC_J ... OPC_JAL: /* Jump */\n+ case OPC_J: /* Jump */\n+ case OPC_JAL:\n offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2;\n gen_compute_branch(ctx, op, 4, rs, rt, offset, 4);\n break;\n@@ -19826,15 +19970,20 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)\n case OPC_LWR:\n check_insn_opc_removed(ctx, ISA_MIPS32R6);\n /* Fallthrough */\n- case OPC_LB ... OPC_LH:\n- case OPC_LW ... OPC_LHU:\n+ case OPC_LB:\n+ case OPC_LH:\n+ case OPC_LW:\n+ case OPC_LWPC:\n+ case OPC_LBU:\n+ case OPC_LHU:\n gen_ld(ctx, op, rt, rs, imm);\n break;\n case OPC_SWL:\n case OPC_SWR:\n check_insn_opc_removed(ctx, ISA_MIPS32R6);\n /* fall through */\n- case OPC_SB ... OPC_SH:\n+ case OPC_SB:\n+ case OPC_SH:\n case OPC_SW:\n gen_st(ctx, op, rt, rs, imm);\n break;\n@@ -20105,7 +20254,8 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)\n \n #if defined(TARGET_MIPS64)\n /* MIPS64 opcodes */\n- case OPC_LDL ... OPC_LDR:\n+ case OPC_LDL:\n+ case OPC_LDR:\n case OPC_LLD:\n check_insn_opc_removed(ctx, ISA_MIPS32R6);\n /* fall through */\n@@ -20115,7 +20265,8 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)\n check_mips_64(ctx);\n gen_ld(ctx, op, rt, rs, imm);\n break;\n- case OPC_SDL ... OPC_SDR:\n+ case OPC_SDL:\n+ case OPC_SDR:\n check_insn_opc_removed(ctx, ISA_MIPS32R6);\n /* fall through */\n case OPC_SD:\n", "prefixes": [ "v7", "02/80" ] }