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Update a patch.
GET /api/patches/951916/?format=api
{ "id": 951916, "url": "http://patchwork.ozlabs.org/api/patches/951916/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20180801040433.5865-9-anirudh.venkataramanan@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20180801040433.5865-9-anirudh.venkataramanan@intel.com>", "list_archive_url": null, "date": "2018-08-01T04:04:28", "name": "[v2,08/13] ice: Clean up register file", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "2e46c19824cba2b8497bd47d8fc3be59b3c3521b", "submitter": { "id": 73601, "url": "http://patchwork.ozlabs.org/api/people/73601/?format=api", "name": "Anirudh Venkataramanan", "email": "anirudh.venkataramanan@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20180801040433.5865-9-anirudh.venkataramanan@intel.com/mbox/", "series": [ { "id": 58674, "url": "http://patchwork.ozlabs.org/api/series/58674/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=58674", "date": "2018-08-01T04:04:20", "name": "Feature updates for ice", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/58674/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/951916/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/951916/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=osuosl.org\n\t(client-ip=140.211.166.133; helo=hemlock.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=intel.com" ], "Received": [ "from hemlock.osuosl.org (smtp2.osuosl.org [140.211.166.133])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 41gKT96LRXz9ryn\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 1 Aug 2018 14:05:01 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id 37C2487F4F;\n\tWed, 1 Aug 2018 04:05:00 +0000 (UTC)", "from hemlock.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id CDcPawpI4UFn; Wed, 1 Aug 2018 04:04:55 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id 7C4ED87F37;\n\tWed, 1 Aug 2018 04:04:54 +0000 (UTC)", "from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136])\n\tby ash.osuosl.org (Postfix) with ESMTP id A01C31C0BBC\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tWed, 1 Aug 2018 04:04:52 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby silver.osuosl.org (Postfix) with ESMTP id 9CDA425636\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tWed, 1 Aug 2018 04:04:52 +0000 (UTC)", "from silver.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id mhMnff2k6FSJ for <intel-wired-lan@lists.osuosl.org>;\n\tWed, 1 Aug 2018 04:04:51 +0000 (UTC)", "from mga12.intel.com (mga12.intel.com [192.55.52.136])\n\tby silver.osuosl.org (Postfix) with ESMTPS id 4308D25C1B\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tWed, 1 Aug 2018 04:04:51 +0000 (UTC)", "from fmsmga003.fm.intel.com ([10.253.24.29])\n\tby fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t31 Jul 2018 21:04:50 -0700", "from lnahar-mobl.amr.corp.intel.com (HELO\n\tavenkata-mobl4.localdomain) ([10.252.134.1])\n\tby FMSMGA003.fm.intel.com with ESMTP; 31 Jul 2018 21:04:49 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.51,430,1526367600\"; d=\"scan'208\";a=\"69105114\"", "From": "Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Tue, 31 Jul 2018 21:04:28 -0700", "Message-Id": "<20180801040433.5865-9-anirudh.venkataramanan@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20180801040433.5865-1-anirudh.venkataramanan@intel.com>", "References": "<20180801040433.5865-1-anirudh.venkataramanan@intel.com>", "Subject": "[Intel-wired-lan] [PATCH v2 08/13] ice: Clean up register file", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.24", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "This patch cleans up the existing register definitions.\n\n1) Several instances of long defines names used in the BIT() macro\n were replaced to use the actual values they represent. As a\n result some defines for shifts (ending with _S) that were used\n only to create bitmasks were removed completely.\n\n2) Apply more consistent tab spacing.\n\nSigned-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>\n---\n .../net/ethernet/intel/ice/ice_hw_autogen.h | 417 ++++++++----------\n 1 file changed, 188 insertions(+), 229 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/ice/ice_hw_autogen.h b/drivers/net/ethernet/intel/ice/ice_hw_autogen.h\nindex 6076fc87df9d..067ca26a1d94 100644\n--- a/drivers/net/ethernet/intel/ice/ice_hw_autogen.h\n+++ b/drivers/net/ethernet/intel/ice/ice_hw_autogen.h\n@@ -6,251 +6,210 @@\n #ifndef _ICE_HW_AUTOGEN_H_\n #define _ICE_HW_AUTOGEN_H_\n \n-#define QTX_COMM_DBELL(_DBQM)\t\t(0x002C0000 + ((_DBQM) * 4))\n-#define PF_FW_ARQBAH\t\t\t0x00080180\n-#define PF_FW_ARQBAL\t\t\t0x00080080\n-#define PF_FW_ARQH\t\t\t0x00080380\n-#define PF_FW_ARQH_ARQH_S\t\t0\n-#define PF_FW_ARQH_ARQH_M\t\tICE_M(0x3FF, PF_FW_ARQH_ARQH_S)\n-#define PF_FW_ARQLEN\t\t\t0x00080280\n-#define PF_FW_ARQLEN_ARQLEN_S\t\t0\n-#define PF_FW_ARQLEN_ARQLEN_M\t\tICE_M(0x3FF, PF_FW_ARQLEN_ARQLEN_S)\n-#define PF_FW_ARQLEN_ARQVFE_S\t\t28\n-#define PF_FW_ARQLEN_ARQVFE_M\t\tBIT(PF_FW_ARQLEN_ARQVFE_S)\n-#define PF_FW_ARQLEN_ARQOVFL_S\t\t29\n-#define PF_FW_ARQLEN_ARQOVFL_M\t\tBIT(PF_FW_ARQLEN_ARQOVFL_S)\n-#define PF_FW_ARQLEN_ARQCRIT_S\t\t30\n-#define PF_FW_ARQLEN_ARQCRIT_M\t\tBIT(PF_FW_ARQLEN_ARQCRIT_S)\n-#define PF_FW_ARQLEN_ARQENABLE_S\t31\n-#define PF_FW_ARQLEN_ARQENABLE_M\tBIT(PF_FW_ARQLEN_ARQENABLE_S)\n-#define PF_FW_ARQT\t\t\t0x00080480\n-#define PF_FW_ATQBAH\t\t\t0x00080100\n-#define PF_FW_ATQBAL\t\t\t0x00080000\n-#define PF_FW_ATQH\t\t\t0x00080300\n-#define PF_FW_ATQH_ATQH_S\t\t0\n-#define PF_FW_ATQH_ATQH_M\t\tICE_M(0x3FF, PF_FW_ATQH_ATQH_S)\n-#define PF_FW_ATQLEN\t\t\t0x00080200\n-#define PF_FW_ATQLEN_ATQLEN_S\t\t0\n-#define PF_FW_ATQLEN_ATQLEN_M\t\tICE_M(0x3FF, PF_FW_ATQLEN_ATQLEN_S)\n-#define PF_FW_ATQLEN_ATQVFE_S\t\t28\n-#define PF_FW_ATQLEN_ATQVFE_M\t\tBIT(PF_FW_ATQLEN_ATQVFE_S)\n-#define PF_FW_ATQLEN_ATQOVFL_S\t\t29\n-#define PF_FW_ATQLEN_ATQOVFL_M\t\tBIT(PF_FW_ATQLEN_ATQOVFL_S)\n-#define PF_FW_ATQLEN_ATQCRIT_S\t\t30\n-#define PF_FW_ATQLEN_ATQCRIT_M\t\tBIT(PF_FW_ATQLEN_ATQCRIT_S)\n-#define PF_FW_ATQLEN_ATQENABLE_S\t31\n-#define PF_FW_ATQLEN_ATQENABLE_M\tBIT(PF_FW_ATQLEN_ATQENABLE_S)\n-#define PF_FW_ATQT\t\t\t0x00080400\n-\n+#define QTX_COMM_DBELL(_DBQM)\t\t\t(0x002C0000 + ((_DBQM) * 4))\n+#define PF_FW_ARQBAH\t\t\t\t0x00080180\n+#define PF_FW_ARQBAL\t\t\t\t0x00080080\n+#define PF_FW_ARQH\t\t\t\t0x00080380\n+#define PF_FW_ARQH_ARQH_M\t\t\tICE_M(0x3FF, 0)\n+#define PF_FW_ARQLEN\t\t\t\t0x00080280\n+#define PF_FW_ARQLEN_ARQLEN_M\t\t\tICE_M(0x3FF, 0)\n+#define PF_FW_ARQLEN_ARQVFE_M\t\t\tBIT(28)\n+#define PF_FW_ARQLEN_ARQOVFL_M\t\t\tBIT(29)\n+#define PF_FW_ARQLEN_ARQCRIT_M\t\t\tBIT(30)\n+#define PF_FW_ARQLEN_ARQENABLE_M\t\tBIT(31)\n+#define PF_FW_ARQT\t\t\t\t0x00080480\n+#define PF_FW_ATQBAH\t\t\t\t0x00080100\n+#define PF_FW_ATQBAL\t\t\t\t0x00080000\n+#define PF_FW_ATQH\t\t\t\t0x00080300\n+#define PF_FW_ATQH_ATQH_M\t\t\tICE_M(0x3FF, 0)\n+#define PF_FW_ATQLEN\t\t\t\t0x00080200\n+#define PF_FW_ATQLEN_ATQLEN_M\t\t\tICE_M(0x3FF, 0)\n+#define PF_FW_ATQLEN_ATQVFE_M\t\t\tBIT(28)\n+#define PF_FW_ATQLEN_ATQOVFL_M\t\t\tBIT(29)\n+#define PF_FW_ATQLEN_ATQCRIT_M\t\t\tBIT(30)\n+#define PF_FW_ATQLEN_ATQENABLE_M\t\tBIT(31)\n+#define PF_FW_ATQT\t\t\t\t0x00080400\n #define GLFLXP_RXDID_FLAGS(_i, _j)\t\t(0x0045D000 + ((_i) * 4 + (_j) * 256))\n #define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S\t0\n-#define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M\tICE_M(0x3F, GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S)\n+#define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M\tICE_M(0x3F, 0)\n #define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_S\t8\n-#define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_M\tICE_M(0x3F, GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_S)\n+#define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_M\tICE_M(0x3F, 8)\n #define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_S\t16\n-#define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_M\tICE_M(0x3F, GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_S)\n+#define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_M\tICE_M(0x3F, 16)\n #define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_S\t24\n-#define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_M\tICE_M(0x3F, GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_S)\n+#define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_M\tICE_M(0x3F, 24)\n #define GLFLXP_RXDID_FLX_WRD_0(_i)\t\t(0x0045c800 + ((_i) * 4))\n #define GLFLXP_RXDID_FLX_WRD_0_PROT_MDID_S\t0\n-#define GLFLXP_RXDID_FLX_WRD_0_PROT_MDID_M\tICE_M(0xFF, GLFLXP_RXDID_FLX_WRD_0_PROT_MDID_S)\n+#define GLFLXP_RXDID_FLX_WRD_0_PROT_MDID_M\tICE_M(0xFF, 0)\n #define GLFLXP_RXDID_FLX_WRD_0_RXDID_OPCODE_S\t30\n-#define GLFLXP_RXDID_FLX_WRD_0_RXDID_OPCODE_M\tICE_M(0x3, GLFLXP_RXDID_FLX_WRD_0_RXDID_OPCODE_S)\n+#define GLFLXP_RXDID_FLX_WRD_0_RXDID_OPCODE_M\tICE_M(0x3, 30)\n #define GLFLXP_RXDID_FLX_WRD_1(_i)\t\t(0x0045c900 + ((_i) * 4))\n #define GLFLXP_RXDID_FLX_WRD_1_PROT_MDID_S\t0\n-#define GLFLXP_RXDID_FLX_WRD_1_PROT_MDID_M\tICE_M(0xFF, GLFLXP_RXDID_FLX_WRD_1_PROT_MDID_S)\n+#define GLFLXP_RXDID_FLX_WRD_1_PROT_MDID_M\tICE_M(0xFF, 0)\n #define GLFLXP_RXDID_FLX_WRD_1_RXDID_OPCODE_S\t30\n-#define GLFLXP_RXDID_FLX_WRD_1_RXDID_OPCODE_M\tICE_M(0x3, GLFLXP_RXDID_FLX_WRD_1_RXDID_OPCODE_S)\n+#define GLFLXP_RXDID_FLX_WRD_1_RXDID_OPCODE_M\tICE_M(0x3, 30)\n #define GLFLXP_RXDID_FLX_WRD_2(_i)\t\t(0x0045ca00 + ((_i) * 4))\n #define GLFLXP_RXDID_FLX_WRD_2_PROT_MDID_S\t0\n-#define GLFLXP_RXDID_FLX_WRD_2_PROT_MDID_M\tICE_M(0xFF, GLFLXP_RXDID_FLX_WRD_2_PROT_MDID_S)\n+#define GLFLXP_RXDID_FLX_WRD_2_PROT_MDID_M\tICE_M(0xFF, 0)\n #define GLFLXP_RXDID_FLX_WRD_2_RXDID_OPCODE_S\t30\n-#define GLFLXP_RXDID_FLX_WRD_2_RXDID_OPCODE_M\tICE_M(0x3, GLFLXP_RXDID_FLX_WRD_2_RXDID_OPCODE_S)\n+#define GLFLXP_RXDID_FLX_WRD_2_RXDID_OPCODE_M\tICE_M(0x3, 30)\n #define GLFLXP_RXDID_FLX_WRD_3(_i)\t\t(0x0045cb00 + ((_i) * 4))\n #define GLFLXP_RXDID_FLX_WRD_3_PROT_MDID_S\t0\n-#define GLFLXP_RXDID_FLX_WRD_3_PROT_MDID_M\tICE_M(0xFF, GLFLXP_RXDID_FLX_WRD_3_PROT_MDID_S)\n+#define GLFLXP_RXDID_FLX_WRD_3_PROT_MDID_M\tICE_M(0xFF, 0)\n #define GLFLXP_RXDID_FLX_WRD_3_RXDID_OPCODE_S\t30\n-#define GLFLXP_RXDID_FLX_WRD_3_RXDID_OPCODE_M\tICE_M(0x3, GLFLXP_RXDID_FLX_WRD_3_RXDID_OPCODE_S)\n-\n-#define QRXFLXP_CNTXT(_QRX)\t\t(0x00480000 + ((_QRX) * 4))\n-#define QRXFLXP_CNTXT_RXDID_IDX_S\t0\n-#define QRXFLXP_CNTXT_RXDID_IDX_M\tICE_M(0x3F, QRXFLXP_CNTXT_RXDID_IDX_S)\n-#define QRXFLXP_CNTXT_RXDID_PRIO_S\t8\n-#define QRXFLXP_CNTXT_RXDID_PRIO_M\tICE_M(0x7, QRXFLXP_CNTXT_RXDID_PRIO_S)\n-#define QRXFLXP_CNTXT_TS_S\t\t11\n-#define QRXFLXP_CNTXT_TS_M\t\tBIT(QRXFLXP_CNTXT_TS_S)\n-#define GLGEN_RSTAT\t\t\t0x000B8188\n-#define GLGEN_RSTAT_DEVSTATE_S\t\t0\n-#define GLGEN_RSTAT_DEVSTATE_M\t\tICE_M(0x3, GLGEN_RSTAT_DEVSTATE_S)\n-#define GLGEN_RSTCTL\t\t\t0x000B8180\n-#define GLGEN_RSTCTL_GRSTDEL_S\t\t0\n-#define GLGEN_RSTCTL_GRSTDEL_M\t\tICE_M(0x3F, GLGEN_RSTCTL_GRSTDEL_S)\n-#define GLGEN_RSTAT_RESET_TYPE_S\t2\n-#define GLGEN_RSTAT_RESET_TYPE_M\tICE_M(0x3, GLGEN_RSTAT_RESET_TYPE_S)\n-#define GLGEN_RTRIG\t\t\t0x000B8190\n-#define GLGEN_RTRIG_CORER_S\t\t0\n-#define GLGEN_RTRIG_CORER_M\t\tBIT(GLGEN_RTRIG_CORER_S)\n-#define GLGEN_RTRIG_GLOBR_S\t\t1\n-#define GLGEN_RTRIG_GLOBR_M\t\tBIT(GLGEN_RTRIG_GLOBR_S)\n-#define GLGEN_STAT\t\t\t0x000B612C\n-#define PFGEN_CTRL\t\t\t0x00091000\n-#define PFGEN_CTRL_PFSWR_S\t\t0\n-#define PFGEN_CTRL_PFSWR_M\t\tBIT(PFGEN_CTRL_PFSWR_S)\n-#define PFGEN_STATE\t\t\t0x00088000\n-#define PRTGEN_STATUS\t\t\t0x000B8100\n-#define PFHMC_ERRORDATA\t\t\t0x00520500\n-#define PFHMC_ERRORINFO\t\t\t0x00520400\n-#define GLINT_DYN_CTL(_INT)\t\t(0x00160000 + ((_INT) * 4))\n-#define GLINT_DYN_CTL_INTENA_S\t\t0\n-#define GLINT_DYN_CTL_INTENA_M\t\tBIT(GLINT_DYN_CTL_INTENA_S)\n-#define GLINT_DYN_CTL_CLEARPBA_S\t1\n-#define GLINT_DYN_CTL_CLEARPBA_M\tBIT(GLINT_DYN_CTL_CLEARPBA_S)\n-#define GLINT_DYN_CTL_SWINT_TRIG_S\t2\n-#define GLINT_DYN_CTL_SWINT_TRIG_M\tBIT(GLINT_DYN_CTL_SWINT_TRIG_S)\n-#define GLINT_DYN_CTL_ITR_INDX_S\t3\n-#define GLINT_DYN_CTL_SW_ITR_INDX_S\t25\n-#define GLINT_DYN_CTL_SW_ITR_INDX_M\tICE_M(0x3, GLINT_DYN_CTL_SW_ITR_INDX_S)\n-#define GLINT_DYN_CTL_INTENA_MSK_S\t31\n-#define GLINT_DYN_CTL_INTENA_MSK_M\tBIT(GLINT_DYN_CTL_INTENA_MSK_S)\n-#define GLINT_ITR(_i, _INT)\t\t(0x00154000 + ((_i) * 8192 + (_INT) * 4))\n-#define PFINT_FW_CTL\t\t\t0x0016C800\n-#define PFINT_FW_CTL_MSIX_INDX_S\t0\n-#define PFINT_FW_CTL_MSIX_INDX_M\tICE_M(0x7FF, PFINT_FW_CTL_MSIX_INDX_S)\n-#define PFINT_FW_CTL_ITR_INDX_S\t\t11\n-#define PFINT_FW_CTL_ITR_INDX_M\t\tICE_M(0x3, PFINT_FW_CTL_ITR_INDX_S)\n-#define PFINT_FW_CTL_CAUSE_ENA_S\t30\n-#define PFINT_FW_CTL_CAUSE_ENA_M\tBIT(PFINT_FW_CTL_CAUSE_ENA_S)\n-#define PFINT_OICR\t\t\t0x0016CA00\n-#define PFINT_OICR_ECC_ERR_S\t\t16\n-#define PFINT_OICR_ECC_ERR_M\t\tBIT(PFINT_OICR_ECC_ERR_S)\n-#define PFINT_OICR_MAL_DETECT_S\t\t19\n-#define PFINT_OICR_MAL_DETECT_M\t\tBIT(PFINT_OICR_MAL_DETECT_S)\n-#define PFINT_OICR_GRST_S\t\t20\n-#define PFINT_OICR_GRST_M\t\tBIT(PFINT_OICR_GRST_S)\n-#define PFINT_OICR_PCI_EXCEPTION_S\t21\n-#define PFINT_OICR_PCI_EXCEPTION_M\tBIT(PFINT_OICR_PCI_EXCEPTION_S)\n-#define PFINT_OICR_HMC_ERR_S\t\t26\n-#define PFINT_OICR_HMC_ERR_M\t\tBIT(PFINT_OICR_HMC_ERR_S)\n-#define PFINT_OICR_PE_CRITERR_S\t\t28\n-#define PFINT_OICR_PE_CRITERR_M\t\tBIT(PFINT_OICR_PE_CRITERR_S)\n-#define PFINT_OICR_CTL\t\t\t0x0016CA80\n-#define PFINT_OICR_CTL_MSIX_INDX_S\t0\n-#define PFINT_OICR_CTL_MSIX_INDX_M\tICE_M(0x7FF, PFINT_OICR_CTL_MSIX_INDX_S)\n-#define PFINT_OICR_CTL_ITR_INDX_S\t11\n-#define PFINT_OICR_CTL_ITR_INDX_M\tICE_M(0x3, PFINT_OICR_CTL_ITR_INDX_S)\n-#define PFINT_OICR_CTL_CAUSE_ENA_S\t30\n-#define PFINT_OICR_CTL_CAUSE_ENA_M\tBIT(PFINT_OICR_CTL_CAUSE_ENA_S)\n-#define PFINT_OICR_ENA\t\t\t0x0016C900\n-#define QINT_RQCTL(_QRX)\t\t(0x00150000 + ((_QRX) * 4))\n-#define QINT_RQCTL_MSIX_INDX_S\t\t0\n-#define QINT_RQCTL_ITR_INDX_S\t\t11\n-#define QINT_RQCTL_CAUSE_ENA_S\t\t30\n-#define QINT_RQCTL_CAUSE_ENA_M\t\tBIT(QINT_RQCTL_CAUSE_ENA_S)\n-#define QINT_TQCTL(_DBQM)\t\t(0x00140000 + ((_DBQM) * 4))\n-#define QINT_TQCTL_MSIX_INDX_S\t\t0\n-#define QINT_TQCTL_ITR_INDX_S\t\t11\n-#define QINT_TQCTL_CAUSE_ENA_S\t\t30\n-#define QINT_TQCTL_CAUSE_ENA_M\t\tBIT(QINT_TQCTL_CAUSE_ENA_S)\n-#define GLLAN_RCTL_0\t\t\t0x002941F8\n-#define QRX_CONTEXT(_i, _QRX)\t\t(0x00280000 + ((_i) * 8192 + (_QRX) * 4))\n-#define QRX_CTRL(_QRX)\t\t\t(0x00120000 + ((_QRX) * 4))\n-#define QRX_CTRL_MAX_INDEX\t\t2047\n-#define QRX_CTRL_QENA_REQ_S\t\t0\n-#define QRX_CTRL_QENA_REQ_M\t\tBIT(QRX_CTRL_QENA_REQ_S)\n-#define QRX_CTRL_QENA_STAT_S\t\t2\n-#define QRX_CTRL_QENA_STAT_M\t\tBIT(QRX_CTRL_QENA_STAT_S)\n-#define QRX_ITR(_QRX)\t\t\t(0x00292000 + ((_QRX) * 4))\n-#define QRX_TAIL(_QRX)\t\t\t(0x00290000 + ((_QRX) * 4))\n-#define GLNVM_FLA\t\t\t0x000B6108\n-#define GLNVM_FLA_LOCKED_S\t\t6\n-#define GLNVM_FLA_LOCKED_M\t\tBIT(GLNVM_FLA_LOCKED_S)\n-#define GLNVM_GENS\t\t\t0x000B6100\n-#define GLNVM_GENS_SR_SIZE_S\t\t5\n-#define GLNVM_GENS_SR_SIZE_M\t\tICE_M(0x7, GLNVM_GENS_SR_SIZE_S)\n-#define GLNVM_ULD\t\t\t0x000B6008\n-#define GLNVM_ULD_CORER_DONE_S\t\t3\n-#define GLNVM_ULD_CORER_DONE_M\t\tBIT(GLNVM_ULD_CORER_DONE_S)\n-#define GLNVM_ULD_GLOBR_DONE_S\t\t4\n-#define GLNVM_ULD_GLOBR_DONE_M\t\tBIT(GLNVM_ULD_GLOBR_DONE_S)\n-#define PF_FUNC_RID\t\t\t0x0009E880\n-#define PF_FUNC_RID_FUNC_NUM_S\t\t0\n-#define PF_FUNC_RID_FUNC_NUM_M\t\tICE_M(0x7, PF_FUNC_RID_FUNC_NUM_S)\n-#define GLPRT_BPRCH(_i)\t\t\t(0x00381384 + ((_i) * 8))\n-#define GLPRT_BPRCL(_i)\t\t\t(0x00381380 + ((_i) * 8))\n-#define GLPRT_BPTCH(_i)\t\t\t(0x00381244 + ((_i) * 8))\n-#define GLPRT_BPTCL(_i)\t\t\t(0x00381240 + ((_i) * 8))\n-#define GLPRT_CRCERRS(_i)\t\t(0x00380100 + ((_i) * 8))\n-#define GLPRT_GORCH(_i)\t\t\t(0x00380004 + ((_i) * 8))\n-#define GLPRT_GORCL(_i)\t\t\t(0x00380000 + ((_i) * 8))\n-#define GLPRT_GOTCH(_i)\t\t\t(0x00380B44 + ((_i) * 8))\n-#define GLPRT_GOTCL(_i)\t\t\t(0x00380B40 + ((_i) * 8))\n-#define GLPRT_ILLERRC(_i)\t\t(0x003801C0 + ((_i) * 8))\n-#define GLPRT_LXOFFRXC(_i)\t\t(0x003802C0 + ((_i) * 8))\n-#define GLPRT_LXOFFTXC(_i)\t\t(0x00381180 + ((_i) * 8))\n-#define GLPRT_LXONRXC(_i)\t\t(0x00380280 + ((_i) * 8))\n-#define GLPRT_LXONTXC(_i)\t\t(0x00381140 + ((_i) * 8))\n-#define GLPRT_MLFC(_i)\t\t\t(0x00380040 + ((_i) * 8))\n-#define GLPRT_MPRCH(_i)\t\t\t(0x00381344 + ((_i) * 8))\n-#define GLPRT_MPRCL(_i)\t\t\t(0x00381340 + ((_i) * 8))\n-#define GLPRT_MPTCH(_i)\t\t\t(0x00381204 + ((_i) * 8))\n-#define GLPRT_MPTCL(_i)\t\t\t(0x00381200 + ((_i) * 8))\n-#define GLPRT_MRFC(_i)\t\t\t(0x00380080 + ((_i) * 8))\n-#define GLPRT_PRC1023H(_i)\t\t(0x00380A04 + ((_i) * 8))\n-#define GLPRT_PRC1023L(_i)\t\t(0x00380A00 + ((_i) * 8))\n-#define GLPRT_PRC127H(_i)\t\t(0x00380944 + ((_i) * 8))\n-#define GLPRT_PRC127L(_i)\t\t(0x00380940 + ((_i) * 8))\n-#define GLPRT_PRC1522H(_i)\t\t(0x00380A44 + ((_i) * 8))\n-#define GLPRT_PRC1522L(_i)\t\t(0x00380A40 + ((_i) * 8))\n-#define GLPRT_PRC255H(_i)\t\t(0x00380984 + ((_i) * 8))\n-#define GLPRT_PRC255L(_i)\t\t(0x00380980 + ((_i) * 8))\n-#define GLPRT_PRC511H(_i)\t\t(0x003809C4 + ((_i) * 8))\n-#define GLPRT_PRC511L(_i)\t\t(0x003809C0 + ((_i) * 8))\n-#define GLPRT_PRC64H(_i)\t\t(0x00380904 + ((_i) * 8))\n-#define GLPRT_PRC64L(_i)\t\t(0x00380900 + ((_i) * 8))\n-#define GLPRT_PRC9522H(_i)\t\t(0x00380A84 + ((_i) * 8))\n-#define GLPRT_PRC9522L(_i)\t\t(0x00380A80 + ((_i) * 8))\n-#define GLPRT_PTC1023H(_i)\t\t(0x00380C84 + ((_i) * 8))\n-#define GLPRT_PTC1023L(_i)\t\t(0x00380C80 + ((_i) * 8))\n-#define GLPRT_PTC127H(_i)\t\t(0x00380BC4 + ((_i) * 8))\n-#define GLPRT_PTC127L(_i)\t\t(0x00380BC0 + ((_i) * 8))\n-#define GLPRT_PTC1522H(_i)\t\t(0x00380CC4 + ((_i) * 8))\n-#define GLPRT_PTC1522L(_i)\t\t(0x00380CC0 + ((_i) * 8))\n-#define GLPRT_PTC255H(_i)\t\t(0x00380C04 + ((_i) * 8))\n-#define GLPRT_PTC255L(_i)\t\t(0x00380C00 + ((_i) * 8))\n-#define GLPRT_PTC511H(_i)\t\t(0x00380C44 + ((_i) * 8))\n-#define GLPRT_PTC511L(_i)\t\t(0x00380C40 + ((_i) * 8))\n-#define GLPRT_PTC64H(_i)\t\t(0x00380B84 + ((_i) * 8))\n-#define GLPRT_PTC64L(_i)\t\t(0x00380B80 + ((_i) * 8))\n-#define GLPRT_PTC9522H(_i)\t\t(0x00380D04 + ((_i) * 8))\n-#define GLPRT_PTC9522L(_i)\t\t(0x00380D00 + ((_i) * 8))\n-#define GLPRT_RFC(_i)\t\t\t(0x00380AC0 + ((_i) * 8))\n-#define GLPRT_RJC(_i)\t\t\t(0x00380B00 + ((_i) * 8))\n-#define GLPRT_RLEC(_i)\t\t\t(0x00380140 + ((_i) * 8))\n-#define GLPRT_ROC(_i)\t\t\t(0x00380240 + ((_i) * 8))\n-#define GLPRT_RUC(_i)\t\t\t(0x00380200 + ((_i) * 8))\n-#define GLPRT_TDOLD(_i)\t\t\t(0x00381280 + ((_i) * 8))\n-#define GLPRT_UPRCH(_i)\t\t\t(0x00381304 + ((_i) * 8))\n-#define GLPRT_UPRCL(_i)\t\t\t(0x00381300 + ((_i) * 8))\n-#define GLPRT_UPTCH(_i)\t\t\t(0x003811C4 + ((_i) * 8))\n-#define GLPRT_UPTCL(_i)\t\t\t(0x003811C0 + ((_i) * 8))\n-#define GLV_BPRCH(_i)\t\t\t(0x003B6004 + ((_i) * 8))\n-#define GLV_BPRCL(_i)\t\t\t(0x003B6000 + ((_i) * 8))\n-#define GLV_BPTCH(_i)\t\t\t(0x0030E004 + ((_i) * 8))\n-#define GLV_BPTCL(_i)\t\t\t(0x0030E000 + ((_i) * 8))\n-#define GLV_GORCH(_i)\t\t\t(0x003B0004 + ((_i) * 8))\n-#define GLV_GORCL(_i)\t\t\t(0x003B0000 + ((_i) * 8))\n-#define GLV_GOTCH(_i)\t\t\t(0x00300004 + ((_i) * 8))\n-#define GLV_GOTCL(_i)\t\t\t(0x00300000 + ((_i) * 8))\n-#define GLV_MPRCH(_i)\t\t\t(0x003B4004 + ((_i) * 8))\n-#define GLV_MPRCL(_i)\t\t\t(0x003B4000 + ((_i) * 8))\n-#define GLV_MPTCH(_i)\t\t\t(0x0030C004 + ((_i) * 8))\n-#define GLV_MPTCL(_i)\t\t\t(0x0030C000 + ((_i) * 8))\n-#define GLV_RDPC(_i)\t\t\t(0x00294C04 + ((_i) * 4))\n-#define GLV_TEPC(_VSI)\t\t\t(0x00312000 + ((_VSI) * 4))\n-#define GLV_UPRCH(_i)\t\t\t(0x003B2004 + ((_i) * 8))\n-#define GLV_UPRCL(_i)\t\t\t(0x003B2000 + ((_i) * 8))\n-#define GLV_UPTCH(_i)\t\t\t(0x0030A004 + ((_i) * 8))\n-#define GLV_UPTCL(_i)\t\t\t(0x0030A000 + ((_i) * 8))\n-#define VSIQF_HKEY_MAX_INDEX\t\t12\n+#define GLFLXP_RXDID_FLX_WRD_3_RXDID_OPCODE_M\tICE_M(0x3, 30)\n+#define QRXFLXP_CNTXT(_QRX)\t\t\t(0x00480000 + ((_QRX) * 4))\n+#define QRXFLXP_CNTXT_RXDID_IDX_S\t\t0\n+#define QRXFLXP_CNTXT_RXDID_IDX_M\t\tICE_M(0x3F, 0)\n+#define QRXFLXP_CNTXT_RXDID_PRIO_S\t\t8\n+#define QRXFLXP_CNTXT_RXDID_PRIO_M\t\tICE_M(0x7, 8)\n+#define GLGEN_RSTAT\t\t\t\t0x000B8188\n+#define GLGEN_RSTAT_DEVSTATE_M\t\t\tICE_M(0x3, 0)\n+#define GLGEN_RSTCTL\t\t\t\t0x000B8180\n+#define GLGEN_RSTCTL_GRSTDEL_S\t\t\t0\n+#define GLGEN_RSTCTL_GRSTDEL_M\t\t\tICE_M(0x3F, GLGEN_RSTCTL_GRSTDEL_S)\n+#define GLGEN_RSTAT_RESET_TYPE_S\t\t2\n+#define GLGEN_RSTAT_RESET_TYPE_M\t\tICE_M(0x3, 2)\n+#define GLGEN_RTRIG\t\t\t\t0x000B8190\n+#define GLGEN_RTRIG_CORER_M\t\t\tBIT(0)\n+#define GLGEN_RTRIG_GLOBR_M\t\t\tBIT(1)\n+#define GLGEN_STAT\t\t\t\t0x000B612C\n+#define PFGEN_CTRL\t\t\t\t0x00091000\n+#define PFGEN_CTRL_PFSWR_M\t\t\tBIT(0)\n+#define PFGEN_STATE\t\t\t\t0x00088000\n+#define PRTGEN_STATUS\t\t\t\t0x000B8100\n+#define PFHMC_ERRORDATA\t\t\t\t0x00520500\n+#define PFHMC_ERRORINFO\t\t\t\t0x00520400\n+#define GLINT_DYN_CTL(_INT)\t\t\t(0x00160000 + ((_INT) * 4))\n+#define GLINT_DYN_CTL_INTENA_M\t\t\tBIT(0)\n+#define GLINT_DYN_CTL_CLEARPBA_M\t\tBIT(1)\n+#define GLINT_DYN_CTL_SWINT_TRIG_M\t\tBIT(2)\n+#define GLINT_DYN_CTL_ITR_INDX_S\t\t3\n+#define GLINT_DYN_CTL_SW_ITR_INDX_M\t\tICE_M(0x3, 25)\n+#define GLINT_DYN_CTL_INTENA_MSK_M\t\tBIT(31)\n+#define GLINT_ITR(_i, _INT)\t\t\t(0x00154000 + ((_i) * 8192 + (_INT) * 4))\n+#define PFINT_FW_CTL\t\t\t\t0x0016C800\n+#define PFINT_FW_CTL_MSIX_INDX_M\t\tICE_M(0x7FF, 0)\n+#define PFINT_FW_CTL_ITR_INDX_S\t\t\t11\n+#define PFINT_FW_CTL_ITR_INDX_M\t\t\tICE_M(0x3, 11)\n+#define PFINT_FW_CTL_CAUSE_ENA_M\t\tBIT(30)\n+#define PFINT_OICR\t\t\t\t0x0016CA00\n+#define PFINT_OICR_ECC_ERR_M\t\t\tBIT(16)\n+#define PFINT_OICR_MAL_DETECT_M\t\t\tBIT(19)\n+#define PFINT_OICR_GRST_M\t\t\tBIT(20)\n+#define PFINT_OICR_PCI_EXCEPTION_M\t\tBIT(21)\n+#define PFINT_OICR_HMC_ERR_M\t\t\tBIT(26)\n+#define PFINT_OICR_PE_CRITERR_M\t\t\tBIT(28)\n+#define PFINT_OICR_CTL\t\t\t\t0x0016CA80\n+#define PFINT_OICR_CTL_MSIX_INDX_M\t\tICE_M(0x7FF, 0)\n+#define PFINT_OICR_CTL_ITR_INDX_S\t\t11\n+#define PFINT_OICR_CTL_ITR_INDX_M\t\tICE_M(0x3, 11)\n+#define PFINT_OICR_CTL_CAUSE_ENA_M\t\tBIT(30)\n+#define PFINT_OICR_ENA\t\t\t\t0x0016C900\n+#define QINT_RQCTL(_QRX)\t\t\t(0x00150000 + ((_QRX) * 4))\n+#define QINT_RQCTL_MSIX_INDX_S\t\t\t0\n+#define QINT_RQCTL_ITR_INDX_S\t\t\t11\n+#define QINT_RQCTL_CAUSE_ENA_M\t\t\tBIT(30)\n+#define QINT_TQCTL(_DBQM)\t\t\t(0x00140000 + ((_DBQM) * 4))\n+#define QINT_TQCTL_MSIX_INDX_S\t\t\t0\n+#define QINT_TQCTL_ITR_INDX_S\t\t\t11\n+#define QINT_TQCTL_CAUSE_ENA_M\t\t\tBIT(30)\n+#define QRX_CONTEXT(_i, _QRX)\t\t\t(0x00280000 + ((_i) * 8192 + (_QRX) * 4))\n+#define QRX_CTRL(_QRX)\t\t\t\t(0x00120000 + ((_QRX) * 4))\n+#define QRX_CTRL_MAX_INDEX\t\t\t2047\n+#define QRX_CTRL_QENA_REQ_S\t\t\t0\n+#define QRX_CTRL_QENA_REQ_M\t\t\tBIT(0)\n+#define QRX_CTRL_QENA_STAT_S\t\t\t2\n+#define QRX_CTRL_QENA_STAT_M\t\t\tBIT(2)\n+#define QRX_ITR(_QRX)\t\t\t\t(0x00292000 + ((_QRX) * 4))\n+#define QRX_TAIL(_QRX)\t\t\t\t(0x00290000 + ((_QRX) * 4))\n+#define GLNVM_FLA\t\t\t\t0x000B6108\n+#define GLNVM_FLA_LOCKED_M\t\t\tBIT(6)\n+#define GLNVM_GENS\t\t\t\t0x000B6100\n+#define GLNVM_GENS_SR_SIZE_S\t\t\t5\n+#define GLNVM_GENS_SR_SIZE_M\t\t\tICE_M(0x7, 5)\n+#define GLNVM_ULD\t\t\t\t0x000B6008\n+#define GLNVM_ULD_CORER_DONE_M\t\t\tBIT(3)\n+#define GLNVM_ULD_GLOBR_DONE_M\t\t\tBIT(4)\n+#define PF_FUNC_RID\t\t\t\t0x0009E880\n+#define PF_FUNC_RID_FUNC_NUM_S\t\t\t0\n+#define PF_FUNC_RID_FUNC_NUM_M\t\t\tICE_M(0x7, 0)\n+#define GLPRT_BPRCH(_i)\t\t\t\t(0x00381384 + ((_i) * 8))\n+#define GLPRT_BPRCL(_i)\t\t\t\t(0x00381380 + ((_i) * 8))\n+#define GLPRT_BPTCH(_i)\t\t\t\t(0x00381244 + ((_i) * 8))\n+#define GLPRT_BPTCL(_i)\t\t\t\t(0x00381240 + ((_i) * 8))\n+#define GLPRT_CRCERRS(_i)\t\t\t(0x00380100 + ((_i) * 8))\n+#define GLPRT_GORCH(_i)\t\t\t\t(0x00380004 + ((_i) * 8))\n+#define GLPRT_GORCL(_i)\t\t\t\t(0x00380000 + ((_i) * 8))\n+#define GLPRT_GOTCH(_i)\t\t\t\t(0x00380B44 + ((_i) * 8))\n+#define GLPRT_GOTCL(_i)\t\t\t\t(0x00380B40 + ((_i) * 8))\n+#define GLPRT_ILLERRC(_i)\t\t\t(0x003801C0 + ((_i) * 8))\n+#define GLPRT_LXOFFRXC(_i)\t\t\t(0x003802C0 + ((_i) * 8))\n+#define GLPRT_LXOFFTXC(_i)\t\t\t(0x00381180 + ((_i) * 8))\n+#define GLPRT_LXONRXC(_i)\t\t\t(0x00380280 + ((_i) * 8))\n+#define GLPRT_LXONTXC(_i)\t\t\t(0x00381140 + ((_i) * 8))\n+#define GLPRT_MLFC(_i)\t\t\t\t(0x00380040 + ((_i) * 8))\n+#define GLPRT_MPRCH(_i)\t\t\t\t(0x00381344 + ((_i) * 8))\n+#define GLPRT_MPRCL(_i)\t\t\t\t(0x00381340 + ((_i) * 8))\n+#define GLPRT_MPTCH(_i)\t\t\t\t(0x00381204 + ((_i) * 8))\n+#define GLPRT_MPTCL(_i)\t\t\t\t(0x00381200 + ((_i) * 8))\n+#define GLPRT_MRFC(_i)\t\t\t\t(0x00380080 + ((_i) * 8))\n+#define GLPRT_PRC1023H(_i)\t\t\t(0x00380A04 + ((_i) * 8))\n+#define GLPRT_PRC1023L(_i)\t\t\t(0x00380A00 + ((_i) * 8))\n+#define GLPRT_PRC127H(_i)\t\t\t(0x00380944 + ((_i) * 8))\n+#define GLPRT_PRC127L(_i)\t\t\t(0x00380940 + ((_i) * 8))\n+#define GLPRT_PRC1522H(_i)\t\t\t(0x00380A44 + ((_i) * 8))\n+#define GLPRT_PRC1522L(_i)\t\t\t(0x00380A40 + ((_i) * 8))\n+#define GLPRT_PRC255H(_i)\t\t\t(0x00380984 + ((_i) * 8))\n+#define GLPRT_PRC255L(_i)\t\t\t(0x00380980 + ((_i) * 8))\n+#define GLPRT_PRC511H(_i)\t\t\t(0x003809C4 + ((_i) * 8))\n+#define GLPRT_PRC511L(_i)\t\t\t(0x003809C0 + ((_i) * 8))\n+#define GLPRT_PRC64H(_i)\t\t\t(0x00380904 + ((_i) * 8))\n+#define GLPRT_PRC64L(_i)\t\t\t(0x00380900 + ((_i) * 8))\n+#define GLPRT_PRC9522H(_i)\t\t\t(0x00380A84 + ((_i) * 8))\n+#define GLPRT_PRC9522L(_i)\t\t\t(0x00380A80 + ((_i) * 8))\n+#define GLPRT_PTC1023H(_i)\t\t\t(0x00380C84 + ((_i) * 8))\n+#define GLPRT_PTC1023L(_i)\t\t\t(0x00380C80 + ((_i) * 8))\n+#define GLPRT_PTC127H(_i)\t\t\t(0x00380BC4 + ((_i) * 8))\n+#define GLPRT_PTC127L(_i)\t\t\t(0x00380BC0 + ((_i) * 8))\n+#define GLPRT_PTC1522H(_i)\t\t\t(0x00380CC4 + ((_i) * 8))\n+#define GLPRT_PTC1522L(_i)\t\t\t(0x00380CC0 + ((_i) * 8))\n+#define GLPRT_PTC255H(_i)\t\t\t(0x00380C04 + ((_i) * 8))\n+#define GLPRT_PTC255L(_i)\t\t\t(0x00380C00 + ((_i) * 8))\n+#define GLPRT_PTC511H(_i)\t\t\t(0x00380C44 + ((_i) * 8))\n+#define GLPRT_PTC511L(_i)\t\t\t(0x00380C40 + ((_i) * 8))\n+#define GLPRT_PTC64H(_i)\t\t\t(0x00380B84 + ((_i) * 8))\n+#define GLPRT_PTC64L(_i)\t\t\t(0x00380B80 + ((_i) * 8))\n+#define GLPRT_PTC9522H(_i)\t\t\t(0x00380D04 + ((_i) * 8))\n+#define GLPRT_PTC9522L(_i)\t\t\t(0x00380D00 + ((_i) * 8))\n+#define GLPRT_RFC(_i)\t\t\t\t(0x00380AC0 + ((_i) * 8))\n+#define GLPRT_RJC(_i)\t\t\t\t(0x00380B00 + ((_i) * 8))\n+#define GLPRT_RLEC(_i)\t\t\t\t(0x00380140 + ((_i) * 8))\n+#define GLPRT_ROC(_i)\t\t\t\t(0x00380240 + ((_i) * 8))\n+#define GLPRT_RUC(_i)\t\t\t\t(0x00380200 + ((_i) * 8))\n+#define GLPRT_TDOLD(_i)\t\t\t\t(0x00381280 + ((_i) * 8))\n+#define GLPRT_UPRCH(_i)\t\t\t\t(0x00381304 + ((_i) * 8))\n+#define GLPRT_UPRCL(_i)\t\t\t\t(0x00381300 + ((_i) * 8))\n+#define GLPRT_UPTCH(_i)\t\t\t\t(0x003811C4 + ((_i) * 8))\n+#define GLPRT_UPTCL(_i)\t\t\t\t(0x003811C0 + ((_i) * 8))\n+#define GLV_BPRCH(_i)\t\t\t\t(0x003B6004 + ((_i) * 8))\n+#define GLV_BPRCL(_i)\t\t\t\t(0x003B6000 + ((_i) * 8))\n+#define GLV_BPTCH(_i)\t\t\t\t(0x0030E004 + ((_i) * 8))\n+#define GLV_BPTCL(_i)\t\t\t\t(0x0030E000 + ((_i) * 8))\n+#define GLV_GORCH(_i)\t\t\t\t(0x003B0004 + ((_i) * 8))\n+#define GLV_GORCL(_i)\t\t\t\t(0x003B0000 + ((_i) * 8))\n+#define GLV_GOTCH(_i)\t\t\t\t(0x00300004 + ((_i) * 8))\n+#define GLV_GOTCL(_i)\t\t\t\t(0x00300000 + ((_i) * 8))\n+#define GLV_MPRCH(_i)\t\t\t\t(0x003B4004 + ((_i) * 8))\n+#define GLV_MPRCL(_i)\t\t\t\t(0x003B4000 + ((_i) * 8))\n+#define GLV_MPTCH(_i)\t\t\t\t(0x0030C004 + ((_i) * 8))\n+#define GLV_MPTCL(_i)\t\t\t\t(0x0030C000 + ((_i) * 8))\n+#define GLV_RDPC(_i)\t\t\t\t(0x00294C04 + ((_i) * 4))\n+#define GLV_TEPC(_VSI)\t\t\t\t(0x00312000 + ((_VSI) * 4))\n+#define GLV_UPRCH(_i)\t\t\t\t(0x003B2004 + ((_i) * 8))\n+#define GLV_UPRCL(_i)\t\t\t\t(0x003B2000 + ((_i) * 8))\n+#define GLV_UPTCH(_i)\t\t\t\t(0x0030A004 + ((_i) * 8))\n+#define GLV_UPTCL(_i)\t\t\t\t(0x0030A000 + ((_i) * 8))\n+#define VSIQF_HKEY_MAX_INDEX\t\t\t12\n \n #endif /* _ICE_HW_AUTOGEN_H_ */\n", "prefixes": [ "v2", "08/13" ] }