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GET /api/patches/931022/?format=api
{ "id": 931022, "url": "http://patchwork.ozlabs.org/api/patches/931022/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20180618160028.80602.76507.stgit@ahduyck-green-test.jf.intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20180618160028.80602.76507.stgit@ahduyck-green-test.jf.intel.com>", "list_archive_url": null, "date": "2018-06-18T16:02:00", "name": "[jkirsher/net-queue] ixgbe: Be more careful when modifying MAC filters", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "28e908e31ab66ea19ecc9fa296cb655f05d38e42", "submitter": { "id": 251, "url": "http://patchwork.ozlabs.org/api/people/251/?format=api", "name": "Duyck, Alexander H", "email": "alexander.h.duyck@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20180618160028.80602.76507.stgit@ahduyck-green-test.jf.intel.com/mbox/", "series": [ { "id": 50710, "url": "http://patchwork.ozlabs.org/api/series/50710/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=50710", "date": "2018-06-18T16:02:00", "name": "[jkirsher/net-queue] ixgbe: Be more careful when modifying MAC filters", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/50710/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/931022/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/931022/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=osuosl.org\n\t(client-ip=140.211.166.136; helo=silver.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=intel.com" ], "Received": [ "from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 418bfy3HC6z9s0W\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 19 Jun 2018 02:10:48 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby silver.osuosl.org (Postfix) with ESMTP id BFCDF26E29;\n\tMon, 18 Jun 2018 16:10:46 +0000 (UTC)", "from silver.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id XgAhuYV++wCo; Mon, 18 Jun 2018 16:10:43 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby silver.osuosl.org (Postfix) with ESMTP id C223626C89;\n\tMon, 18 Jun 2018 16:10:43 +0000 (UTC)", "from fraxinus.osuosl.org (smtp4.osuosl.org [140.211.166.137])\n\tby ash.osuosl.org (Postfix) with ESMTP id D16641C4378\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tMon, 18 Jun 2018 16:10:42 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id CE0E185E47\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tMon, 18 Jun 2018 16:10:42 +0000 (UTC)", "from fraxinus.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id mS80-AhWYJ-Y for <intel-wired-lan@lists.osuosl.org>;\n\tMon, 18 Jun 2018 16:10:42 +0000 (UTC)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n\tby fraxinus.osuosl.org (Postfix) with ESMTPS id D85E986B7E\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tMon, 18 Jun 2018 16:10:28 +0000 (UTC)", "from orsmga003.jf.intel.com ([10.7.209.27])\n\tby orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t18 Jun 2018 09:10:28 -0700", "from ahduyck-green-test.jf.intel.com ([10.166.244.179])\n\tby orsmga003.jf.intel.com with ESMTP; 18 Jun 2018 09:10:27 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.51,240,1526367600\"; d=\"scan'208\";a=\"60166786\"", "From": "Alexander Duyck <alexander.h.duyck@intel.com>", "To": "shannon.nelson@oracle.com, todd.fujinaka@intel.com,\n\tintel-wired-lan@lists.osuosl.org, jeffrey.t.kirsher@intel.com", "Date": "Mon, 18 Jun 2018 12:02:00 -0400", "Message-ID": "<20180618160028.80602.76507.stgit@ahduyck-green-test.jf.intel.com>", "User-Agent": "StGit/0.17.1-dirty", "MIME-Version": "1.0", "Subject": "[Intel-wired-lan] [jkirsher/net-queue PATCH] ixgbe: Be more careful\n\twhen modifying MAC filters", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.24", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "This change makes it so that we are much more explicit about the ordering\nof updates to the receive address register (RAR) table. Prior to this patch\nI believe we may have been updating the table while entries were still\nactive, or possibly allowing for reordering of things since we weren't\nexplicitly flushing writes to either the lower or upper portion of the\nregister prior to accessing the other half.\n\nSigned-off-by: Alexander Duyck <alexander.h.duyck@intel.com>\n---\n\nI am submitting this as a fix, but I am not certain this actually fixes\nanything or if it is more of just a clean-up. I know there have been some\nissues with MAC address updates reported recently so I decided to review\nthe code and found the bits here that I thought needed to be updated.\nEspecially the case where we were clearing the lower 32b of the address\nwith AV still set in the upper 32b of the register.\n\n drivers/net/ethernet/intel/ixgbe/ixgbe_common.c | 12 +++++++++++-\n 1 file changed, 11 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c\nindex 3f5c350..0bd1294 100644\n--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c\n+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c\n@@ -1871,7 +1871,12 @@ s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,\n \tif (enable_addr != 0)\n \t\trar_high |= IXGBE_RAH_AV;\n \n+\t/* Record lower 32 bits of MAC address and then make\n+\t * sure that write is flushed to hardware before writing\n+\t * the upper 16 bits and setting the valid bit.\n+\t */\n \tIXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);\n+\tIXGBE_WRITE_FLUSH(hw);\n \tIXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);\n \n \treturn 0;\n@@ -1903,8 +1908,13 @@ s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)\n \trar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));\n \trar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);\n \n-\tIXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);\n+\t/* Clear the address valid bit and upper 16 bits of the address\n+\t * before clearing the lower bits. This way we aren't updating\n+\t * a live filter.\n+\t */\n \tIXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);\n+\tIXGBE_WRITE_FLUSH(hw);\n+\tIXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);\n \n \t/* clear VMDq pool/queue selection for this RAR */\n \thw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);\n", "prefixes": [ "jkirsher/net-queue" ] }