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GET /api/patches/908464/?format=api
{ "id": 908464, "url": "http://patchwork.ozlabs.org/api/patches/908464/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20180504030811.28111-4-peterx@redhat.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20180504030811.28111-4-peterx@redhat.com>", "list_archive_url": null, "date": "2018-05-04T03:08:04", "name": "[v2,03/10] intel-iommu: add iommu lock", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "74bfa450d9518b0bbfbef30a74b8cd2e7969665c", "submitter": { "id": 67717, "url": "http://patchwork.ozlabs.org/api/people/67717/?format=api", "name": "Peter Xu", "email": "peterx@redhat.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20180504030811.28111-4-peterx@redhat.com/mbox/", "series": [ { "id": 42502, "url": "http://patchwork.ozlabs.org/api/series/42502/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=42502", "date": "2018-05-04T03:08:01", "name": "intel-iommu: nested vIOMMU, cleanups, bug fixes", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/42502/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/908464/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/908464/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=redhat.com" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 40ccWc1Z6xz9s3D\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 4 May 2018 13:12:28 +1000 (AEST)", "from localhost ([::1]:60180 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1fER8z-00044B-Q5\n\tfor incoming@patchwork.ozlabs.org; Thu, 03 May 2018 23:12:25 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:33256)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <peterx@redhat.com>) id 1fER5V-0001h8-3G\n\tfor qemu-devel@nongnu.org; Thu, 03 May 2018 23:08:50 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <peterx@redhat.com>) id 1fER5R-0005UI-0F\n\tfor qemu-devel@nongnu.org; Thu, 03 May 2018 23:08:49 -0400", "from mx3-rdu2.redhat.com ([66.187.233.73]:55760\n\thelo=mx1.redhat.com)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <peterx@redhat.com>) id 1fER5Q-0005Tt-R7\n\tfor qemu-devel@nongnu.org; Thu, 03 May 2018 23:08:44 -0400", "from smtp.corp.redhat.com\n\t(int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1.redhat.com (Postfix) with ESMTPS id 7ACF64182D59;\n\tFri, 4 May 2018 03:08:44 +0000 (UTC)", "from xz-mi.redhat.com (ovpn-12-46.pek2.redhat.com [10.72.12.46])\n\tby smtp.corp.redhat.com (Postfix) with ESMTP id 8F515111762B;\n\tFri, 4 May 2018 03:08:35 +0000 (UTC)" ], "From": "Peter Xu <peterx@redhat.com>", "To": "qemu-devel@nongnu.org", "Date": "Fri, 4 May 2018 11:08:04 +0800", "Message-Id": "<20180504030811.28111-4-peterx@redhat.com>", "In-Reply-To": "<20180504030811.28111-1-peterx@redhat.com>", "References": "<20180504030811.28111-1-peterx@redhat.com>", "X-Scanned-By": "MIMEDefang 2.78 on 10.11.54.3", "X-Greylist": [ "Sender IP whitelisted, not delayed by milter-greylist-4.5.16\n\t(mx1.redhat.com [10.11.55.7]);\n\tFri, 04 May 2018 03:08:44 +0000 (UTC)", "inspected by milter-greylist-4.5.16 (mx1.redhat.com\n\t[10.11.55.7]); \n\tFri, 04 May 2018 03:08:44 +0000 (UTC) for IP:'10.11.54.3'\n\tDOMAIN:'int-mx03.intmail.prod.int.rdu2.redhat.com'\n\tHELO:'smtp.corp.redhat.com' FROM:'peterx@redhat.com' RCPT:''" ], "X-detected-operating-system": "by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]", "X-Received-From": "66.187.233.73", "Subject": "[Qemu-devel] [PATCH v2 03/10] intel-iommu: add iommu lock", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "Tian Kevin <kevin.tian@intel.com>, \"Michael S . Tsirkin\" <mst@redhat.com>,\n\tJason Wang <jasowang@redhat.com>, peterx@redhat.com,\n\tAlex Williamson <alex.williamson@redhat.com>,\n\tJintack Lim <jintack@cs.columbia.edu>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "Add a per-iommu big lock to protect IOMMU status. Currently the only\nthing to be protected is the IOTLB/context cache, since that can be\naccessed even without BQL, e.g., in IO dataplane.\n\nNote that we don't need to protect device page tables since that's fully\ncontrolled by the guest kernel. However there is still possibility that\nmalicious drivers will program the device to not obey the rule. In that\ncase QEMU can't really do anything useful, instead the guest itself will\nbe responsible for all uncertainties.\n\nReported-by: Fam Zheng <famz@redhat.com>\nSigned-off-by: Peter Xu <peterx@redhat.com>\n---\n include/hw/i386/intel_iommu.h | 6 +++++\n hw/i386/intel_iommu.c | 43 +++++++++++++++++++++++++++++++----\n 2 files changed, 44 insertions(+), 5 deletions(-)", "diff": "diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h\nindex 220697253f..ee517704e7 100644\n--- a/include/hw/i386/intel_iommu.h\n+++ b/include/hw/i386/intel_iommu.h\n@@ -300,6 +300,12 @@ struct IntelIOMMUState {\n OnOffAuto intr_eim; /* Toggle for EIM cabability */\n bool buggy_eim; /* Force buggy EIM unless eim=off */\n uint8_t aw_bits; /* Host/IOVA address width (in bits) */\n+\n+ /*\n+ * Protects IOMMU states in general. Currently it protects the\n+ * per-IOMMU IOTLB cache, and context entry cache in VTDAddressSpace.\n+ */\n+ QemuMutex iommu_lock;\n };\n \n /* Find the VTD Address space associated with the given bus pointer,\ndiff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c\nindex 5987b48d43..112971638d 100644\n--- a/hw/i386/intel_iommu.c\n+++ b/hw/i386/intel_iommu.c\n@@ -128,6 +128,16 @@ static uint64_t vtd_set_clear_mask_quad(IntelIOMMUState *s, hwaddr addr,\n return new_val;\n }\n \n+static inline void vtd_iommu_lock(IntelIOMMUState *s)\n+{\n+ qemu_mutex_lock(&s->iommu_lock);\n+}\n+\n+static inline void vtd_iommu_unlock(IntelIOMMUState *s)\n+{\n+ qemu_mutex_unlock(&s->iommu_lock);\n+}\n+\n /* GHashTable functions */\n static gboolean vtd_uint64_equal(gconstpointer v1, gconstpointer v2)\n {\n@@ -172,7 +182,7 @@ static gboolean vtd_hash_remove_by_page(gpointer key, gpointer value,\n }\n \n /* Reset all the gen of VTDAddressSpace to zero and set the gen of\n- * IntelIOMMUState to 1.\n+ * IntelIOMMUState to 1. Must be with IOMMU lock held.\n */\n static void vtd_reset_context_cache(IntelIOMMUState *s)\n {\n@@ -197,12 +207,19 @@ static void vtd_reset_context_cache(IntelIOMMUState *s)\n s->context_cache_gen = 1;\n }\n \n-static void vtd_reset_iotlb(IntelIOMMUState *s)\n+static void vtd_reset_iotlb_locked(IntelIOMMUState *s)\n {\n assert(s->iotlb);\n g_hash_table_remove_all(s->iotlb);\n }\n \n+static void vtd_reset_iotlb(IntelIOMMUState *s)\n+{\n+ vtd_iommu_lock(s);\n+ vtd_reset_iotlb_locked(s);\n+ vtd_iommu_unlock(s);\n+}\n+\n static uint64_t vtd_get_iotlb_key(uint64_t gfn, uint16_t source_id,\n uint32_t level)\n {\n@@ -215,6 +232,7 @@ static uint64_t vtd_get_iotlb_gfn(hwaddr addr, uint32_t level)\n return (addr & vtd_slpt_level_page_mask(level)) >> VTD_PAGE_SHIFT_4K;\n }\n \n+/* Must be with IOMMU lock held */\n static VTDIOTLBEntry *vtd_lookup_iotlb(IntelIOMMUState *s, uint16_t source_id,\n hwaddr addr)\n {\n@@ -235,6 +253,7 @@ out:\n return entry;\n }\n \n+/* Must be with IOMMU lock held */\n static void vtd_update_iotlb(IntelIOMMUState *s, uint16_t source_id,\n uint16_t domain_id, hwaddr addr, uint64_t slpte,\n uint8_t access_flags, uint32_t level)\n@@ -246,7 +265,7 @@ static void vtd_update_iotlb(IntelIOMMUState *s, uint16_t source_id,\n trace_vtd_iotlb_page_update(source_id, addr, slpte, domain_id);\n if (g_hash_table_size(s->iotlb) >= VTD_IOTLB_MAX_SIZE) {\n trace_vtd_iotlb_reset(\"iotlb exceeds size limit\");\n- vtd_reset_iotlb(s);\n+ vtd_reset_iotlb_locked(s);\n }\n \n entry->gfn = gfn;\n@@ -1106,7 +1125,7 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus,\n IntelIOMMUState *s = vtd_as->iommu_state;\n VTDContextEntry ce;\n uint8_t bus_num = pci_bus_num(bus);\n- VTDContextCacheEntry *cc_entry = &vtd_as->context_cache_entry;\n+ VTDContextCacheEntry *cc_entry;\n uint64_t slpte, page_mask;\n uint32_t level;\n uint16_t source_id = vtd_make_source_id(bus_num, devfn);\n@@ -1123,6 +1142,10 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus,\n */\n assert(!vtd_is_interrupt_addr(addr));\n \n+ vtd_iommu_lock(s);\n+\n+ cc_entry = &vtd_as->context_cache_entry;\n+\n /* Try to fetch slpte form IOTLB */\n iotlb_entry = vtd_lookup_iotlb(s, source_id, addr);\n if (iotlb_entry) {\n@@ -1182,7 +1205,7 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus,\n * IOMMU region can be swapped back.\n */\n vtd_pt_enable_fast_path(s, source_id);\n-\n+ vtd_iommu_unlock(s);\n return true;\n }\n \n@@ -1203,6 +1226,7 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus,\n vtd_update_iotlb(s, source_id, VTD_CONTEXT_ENTRY_DID(ce.hi), addr, slpte,\n access_flags, level);\n out:\n+ vtd_iommu_unlock(s);\n entry->iova = addr & page_mask;\n entry->translated_addr = vtd_get_slpte_addr(slpte, s->aw_bits) & page_mask;\n entry->addr_mask = ~page_mask;\n@@ -1210,6 +1234,7 @@ out:\n return true;\n \n error:\n+ vtd_iommu_unlock(s);\n entry->iova = 0;\n entry->translated_addr = 0;\n entry->addr_mask = 0;\n@@ -1258,10 +1283,13 @@ static void vtd_iommu_replay_all(IntelIOMMUState *s)\n static void vtd_context_global_invalidate(IntelIOMMUState *s)\n {\n trace_vtd_inv_desc_cc_global();\n+ /* Protects context cache */\n+ vtd_iommu_lock(s);\n s->context_cache_gen++;\n if (s->context_cache_gen == VTD_CONTEXT_CACHE_GEN_MAX) {\n vtd_reset_context_cache(s);\n }\n+ vtd_iommu_unlock(s);\n vtd_switch_address_space_all(s);\n /*\n * From VT-d spec 6.5.2.1, a global context entry invalidation\n@@ -1377,8 +1405,10 @@ static void vtd_iotlb_domain_invalidate(IntelIOMMUState *s, uint16_t domain_id)\n \n trace_vtd_inv_desc_iotlb_domain(domain_id);\n \n+ vtd_iommu_lock(s);\n g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_domain,\n &domain_id);\n+ vtd_iommu_unlock(s);\n \n QLIST_FOREACH(vtd_as, &s->notifiers_list, next) {\n if (!vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus),\n@@ -1426,7 +1456,9 @@ static void vtd_iotlb_page_invalidate(IntelIOMMUState *s, uint16_t domain_id,\n info.domain_id = domain_id;\n info.addr = addr;\n info.mask = ~((1 << am) - 1);\n+ vtd_iommu_lock(s);\n g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_page, &info);\n+ vtd_iommu_unlock(s);\n vtd_iotlb_page_invalidate_notify(s, domain_id, addr, am);\n }\n \n@@ -3072,6 +3104,7 @@ static void vtd_realize(DeviceState *dev, Error **errp)\n }\n \n QLIST_INIT(&s->notifiers_list);\n+ qemu_mutex_init(&s->iommu_lock);\n memset(s->vtd_as_by_bus_num, 0, sizeof(s->vtd_as_by_bus_num));\n memory_region_init_io(&s->csrmem, OBJECT(s), &vtd_mem_ops, s,\n \"intel_iommu\", DMAR_REG_SIZE);\n", "prefixes": [ "v2", "03/10" ] }