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GET /api/patches/908222/?format=api
{ "id": 908222, "url": "http://patchwork.ozlabs.org/api/patches/908222/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/152537762921.62474.3606947168382589745.stgit@bhelgaas-glaptop.roam.corp.google.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<152537762921.62474.3606947168382589745.stgit@bhelgaas-glaptop.roam.corp.google.com>", "list_archive_url": null, "date": "2018-05-03T20:00:29", "name": "[v6,3/5] cxgb4: Report PCIe link properties with pcie_print_link_status()", "commit_ref": null, "pull_url": null, "state": "awaiting-upstream", "archived": false, "hash": "a41059d2299acaa1467cf58a8476dff4561332cf", "submitter": { "id": 67298, "url": "http://patchwork.ozlabs.org/api/people/67298/?format=api", "name": "Bjorn Helgaas", "email": "helgaas@kernel.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/152537762921.62474.3606947168382589745.stgit@bhelgaas-glaptop.roam.corp.google.com/mbox/", "series": [ { "id": 42437, "url": "http://patchwork.ozlabs.org/api/series/42437/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=42437", "date": "2018-05-03T20:00:07", "name": "PCI: Improve PCIe link status reporting", "version": 6, "mbox": "http://patchwork.ozlabs.org/series/42437/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/908222/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/908222/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=osuosl.org\n\t(client-ip=140.211.166.138; helo=whitealder.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=kernel.org", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=kernel.org header.i=@kernel.org\n\theader.b=\"0b7BaW4g\"; dkim-atps=neutral" ], "Received": [ "from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 40cQxH0lftz9s4r\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 4 May 2018 06:00:35 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 7A99F88D06;\n\tThu, 3 May 2018 20:00:33 +0000 (UTC)", "from whitealder.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id 0fRXiIcfRKe9; Thu, 3 May 2018 20:00:32 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 6628988AB1;\n\tThu, 3 May 2018 20:00:32 +0000 (UTC)", "from fraxinus.osuosl.org (smtp4.osuosl.org [140.211.166.137])\n\tby ash.osuosl.org (Postfix) with ESMTP id 791091CEF86\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 3 May 2018 20:00:31 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id 766BD87A28\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 3 May 2018 20:00:31 +0000 (UTC)", "from fraxinus.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id 87ZjA8iOZZ8O for <intel-wired-lan@lists.osuosl.org>;\n\tThu, 3 May 2018 20:00:30 +0000 (UTC)", "from mail.kernel.org (mail.kernel.org [198.145.29.99])\n\tby fraxinus.osuosl.org (Postfix) with ESMTPS id EE1EF87A1E\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 3 May 2018 20:00:30 +0000 (UTC)", "from localhost (unknown [69.71.5.252])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby mail.kernel.org (Postfix) with ESMTPSA id 88E0C21770;\n\tThu, 3 May 2018 20:00:30 +0000 (UTC)" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=default; t=1525377630;\n\tbh=rxbT8xj45/G27iJfQAW7k6bYjYqHwN6SXYBodfuT/1o=;\n\th=Subject:From:To:Cc:Date:In-Reply-To:References:From;\n\tb=0b7BaW4gl9gDOq6V06D+q7DEndb44y3lZIhMrvhQ3e/c9yErqyUIAnA28lUZdKuag\n\t1+XQyAGk3F8xmvO51c7UzGGDikrjP1/uBxslnsHdsKjQjfJ8Pqqi6cOEDh/Mw4EUDF\n\tlJ3gryDRPQTAiEBJGkt8f+QKcFEb4jcd9wZrNcjA=", "From": "Bjorn Helgaas <helgaas@kernel.org>", "To": "Jeff Kirsher <jeffrey.t.kirsher@intel.com>,\n\tGanesh Goudar <ganeshgr@chelsio.com>,\n\tMichael Chan <michael.chan@broadcom.com>, \n\tAriel Elior <ariel.elior@cavium.com>", "Date": "Thu, 03 May 2018 15:00:29 -0500", "Message-ID": "<152537762921.62474.3606947168382589745.stgit@bhelgaas-glaptop.roam.corp.google.com>", "In-Reply-To": "<152537719056.62474.2571390812509425478.stgit@bhelgaas-glaptop.roam.corp.google.com>", "References": "<152537719056.62474.2571390812509425478.stgit@bhelgaas-glaptop.roam.corp.google.com>", "User-Agent": "StGit/0.18", "MIME-Version": "1.0", "Subject": "[Intel-wired-lan] [PATCH v6 3/5] cxgb4: Report PCIe link properties\n\twith pcie_print_link_status()", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.24", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "Cc": "Jakub Kicinski <kubakici@wp.pl>, linux-pci@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, Tal Gilboa <talgi@mellanox.com>,\n\tintel-wired-lan@lists.osuosl.org, netdev@vger.kernel.org,\n\teverest-linux-l2@cavium.com, Tariq Toukan <tariqt@mellanox.com>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "From: Bjorn Helgaas <bhelgaas@google.com>\n\nPreviously the driver used pcie_get_minimum_link() to warn when the NIC\nis in a slot that can't supply as much bandwidth as the NIC could use.\n\npcie_get_minimum_link() can be misleading because it finds the slowest link\nand the narrowest link (which may be different links) without considering\nthe total bandwidth of each link. For a path with a 16 GT/s x1 link and a\n2.5 GT/s x16 link, it returns 2.5 GT/s x1, which corresponds to 250 MB/s of\nbandwidth, not the true available bandwidth of about 1969 MB/s for a\n16 GT/s x1 link.\n\nUse pcie_print_link_status() to report PCIe link speed and possible\nlimitations instead of implementing this in the driver itself. This finds\nthe slowest link in the path to the device by computing the total bandwidth\nof each link and compares that with the capabilities of the device.\n\nThe dmesg change is:\n\n - PCIe link speed is %s, device supports %s\n - PCIe link width is x%d, device supports x%d\n + %u.%03u Gb/s available PCIe bandwidth (%s x%d link)\n\nor, if the device is capable of better performance than is available in the\ncurrent slot:\n\n - A slot with more lanes and/or higher speed is suggested for optimal performance.\n + %u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n\nSigned-off-by: Bjorn Helgaas <bhelgaas@google.com>\n---\n drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c | 75 -----------------------\n 1 file changed, 1 insertion(+), 74 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c\nindex 24d2865b8806..7328f24ba1dd 100644\n--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c\n+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c\n@@ -5042,79 +5042,6 @@ static int init_rss(struct adapter *adap)\n \treturn 0;\n }\n \n-static int cxgb4_get_pcie_dev_link_caps(struct adapter *adap,\n-\t\t\t\t\tenum pci_bus_speed *speed,\n-\t\t\t\t\tenum pcie_link_width *width)\n-{\n-\tu32 lnkcap1, lnkcap2;\n-\tint err1, err2;\n-\n-#define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */\n-\n-\t*speed = PCI_SPEED_UNKNOWN;\n-\t*width = PCIE_LNK_WIDTH_UNKNOWN;\n-\n-\terr1 = pcie_capability_read_dword(adap->pdev, PCI_EXP_LNKCAP,\n-\t\t\t\t\t &lnkcap1);\n-\terr2 = pcie_capability_read_dword(adap->pdev, PCI_EXP_LNKCAP2,\n-\t\t\t\t\t &lnkcap2);\n-\tif (!err2 && lnkcap2) { /* PCIe r3.0-compliant */\n-\t\tif (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)\n-\t\t\t*speed = PCIE_SPEED_8_0GT;\n-\t\telse if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)\n-\t\t\t*speed = PCIE_SPEED_5_0GT;\n-\t\telse if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)\n-\t\t\t*speed = PCIE_SPEED_2_5GT;\n-\t}\n-\tif (!err1) {\n-\t\t*width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT;\n-\t\tif (!lnkcap2) { /* pre-r3.0 */\n-\t\t\tif (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB)\n-\t\t\t\t*speed = PCIE_SPEED_5_0GT;\n-\t\t\telse if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB)\n-\t\t\t\t*speed = PCIE_SPEED_2_5GT;\n-\t\t}\n-\t}\n-\n-\tif (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN)\n-\t\treturn err1 ? err1 : err2 ? err2 : -EINVAL;\n-\treturn 0;\n-}\n-\n-static void cxgb4_check_pcie_caps(struct adapter *adap)\n-{\n-\tenum pcie_link_width width, width_cap;\n-\tenum pci_bus_speed speed, speed_cap;\n-\n-#define PCIE_SPEED_STR(speed) \\\n-\t(speed == PCIE_SPEED_8_0GT ? \"8.0GT/s\" : \\\n-\t speed == PCIE_SPEED_5_0GT ? \"5.0GT/s\" : \\\n-\t speed == PCIE_SPEED_2_5GT ? \"2.5GT/s\" : \\\n-\t \"Unknown\")\n-\n-\tif (cxgb4_get_pcie_dev_link_caps(adap, &speed_cap, &width_cap)) {\n-\t\tdev_warn(adap->pdev_dev,\n-\t\t\t \"Unable to determine PCIe device BW capabilities\\n\");\n-\t\treturn;\n-\t}\n-\n-\tif (pcie_get_minimum_link(adap->pdev, &speed, &width) ||\n-\t speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {\n-\t\tdev_warn(adap->pdev_dev,\n-\t\t\t \"Unable to determine PCI Express bandwidth.\\n\");\n-\t\treturn;\n-\t}\n-\n-\tdev_info(adap->pdev_dev, \"PCIe link speed is %s, device supports %s\\n\",\n-\t\t PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap));\n-\tdev_info(adap->pdev_dev, \"PCIe link width is x%d, device supports x%d\\n\",\n-\t\t width, width_cap);\n-\tif (speed < speed_cap || width < width_cap)\n-\t\tdev_info(adap->pdev_dev,\n-\t\t\t \"A slot with more lanes and/or higher speed is \"\n-\t\t\t \"suggested for optimal performance.\\n\");\n-}\n-\n /* Dump basic information about the adapter */\n static void print_adapter_info(struct adapter *adapter)\n {\n@@ -5750,7 +5677,7 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)\n \t}\n \n \t/* check for PCI Express bandwidth capabiltites */\n-\tcxgb4_check_pcie_caps(adapter);\n+\tpcie_print_link_status(pdev);\n \n \terr = init_rss(adapter);\n \tif (err)\n", "prefixes": [ "v6", "3/5" ] }