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GET /api/patches/902053/?format=api
{ "id": 902053, "url": "http://patchwork.ozlabs.org/api/patches/902053/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20180420084140.8081-6-alice.michael@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20180420084140.8081-6-alice.michael@intel.com>", "list_archive_url": null, "date": "2018-04-20T08:41:38", "name": "[next,S90,6/8] i40e: avoid overflow in i40e_ptp_adjfreq()", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "8692f2ace726f2ea21a2d031e36217642538e242", "submitter": { "id": 71123, "url": "http://patchwork.ozlabs.org/api/people/71123/?format=api", "name": "Michael, Alice", "email": "alice.michael@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20180420084140.8081-6-alice.michael@intel.com/mbox/", "series": [ { "id": 40130, "url": "http://patchwork.ozlabs.org/api/series/40130/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=40130", "date": "2018-04-20T08:41:38", "name": "[next,S90,1/8] i40e/i40evf: cleanup incorrect function doxygen comments", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/40130/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/902053/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/902053/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=osuosl.org\n\t(client-ip=140.211.166.138; helo=whitealder.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=none (p=none dis=none) header.from=intel.com" ], "Received": [ "from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 40SML12kPfz9s3G\n\tfor <incoming@patchwork.ozlabs.org>;\n\tSat, 21 Apr 2018 02:50:32 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 18A8888CC5;\n\tFri, 20 Apr 2018 16:50:31 +0000 (UTC)", "from whitealder.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id 49tSJkOVErlp; Fri, 20 Apr 2018 16:50:29 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id E21F588CBE;\n\tFri, 20 Apr 2018 16:50:29 +0000 (UTC)", "from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136])\n\tby ash.osuosl.org (Postfix) with ESMTP id 0B0421CF121\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tFri, 20 Apr 2018 16:50:26 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby silver.osuosl.org (Postfix) with ESMTP id 05A0B2EDCC\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tFri, 20 Apr 2018 16:50:26 +0000 (UTC)", "from silver.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id zRK081Lr7CfI for <intel-wired-lan@lists.osuosl.org>;\n\tFri, 20 Apr 2018 16:50:23 +0000 (UTC)", "from mga14.intel.com (mga14.intel.com [192.55.52.115])\n\tby silver.osuosl.org (Postfix) with ESMTPS id BA3362EED5\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tFri, 20 Apr 2018 16:50:23 +0000 (UTC)", "from fmsmga008.fm.intel.com ([10.253.24.58])\n\tby fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t20 Apr 2018 09:50:22 -0700", "from alicemic-2.jf.intel.com ([10.166.16.121])\n\tby fmsmga008.fm.intel.com with ESMTP; 20 Apr 2018 09:50:22 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.49,302,1520924400\"; d=\"scan'208\";a=\"34086381\"", "From": "Alice Michael <alice.michael@intel.com>", "To": "alice.michael@intel.com,\n\tintel-wired-lan@lists.osuosl.org", "Date": "Fri, 20 Apr 2018 01:41:38 -0700", "Message-Id": "<20180420084140.8081-6-alice.michael@intel.com>", "X-Mailer": "git-send-email 2.9.5", "In-Reply-To": "<20180420084140.8081-1-alice.michael@intel.com>", "References": "<20180420084140.8081-1-alice.michael@intel.com>", "Subject": "[Intel-wired-lan] [next PATCH S90 6/8] i40e: avoid overflow in\n\ti40e_ptp_adjfreq()", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.24", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "From: Jacob Keller <jacob.e.keller@intel.com>\n\nWhen operating at 1GbE, the base incval for the PTP clock is so large\nthat multiplying it by numbers close to the max_adj can overflow the\nu64.\n\nRather than attempting to limit the max_adj to a value small enough to\navoid overflow, instead calculate the incvalue adjustment based on the\n40GbE incvalue, and then multiply that by the scaling factor for the\nlink speed.\n\nThis sacrifices a small amount of precision in the adjustment but we\navoid erratic behavior of the clock due to the overflow caused if ppb is\nvery near the maximum adjustment.\n\nSigned-off-by: Jacob Keller <jacob.e.keller@intel.com>\n---\n drivers/net/ethernet/intel/i40e/i40e.h | 2 +-\n drivers/net/ethernet/intel/i40e/i40e_ptp.c | 41 ++++++++++++++++++++----------\n 2 files changed, 28 insertions(+), 15 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/i40e/i40e.h b/drivers/net/ethernet/intel/i40e/i40e.h\nindex 70d369e..1d59ab6 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e.h\n+++ b/drivers/net/ethernet/intel/i40e/i40e.h\n@@ -586,7 +586,7 @@ struct i40e_pf {\n \tunsigned long ptp_tx_start;\n \tstruct hwtstamp_config tstamp_config;\n \tstruct mutex tmreg_lock; /* Used to protect the SYSTIME registers. */\n-\tu64 ptp_base_adj;\n+\tu32 ptp_adj_mult;\n \tu32 tx_hwtstamp_timeouts;\n \tu32 tx_hwtstamp_skipped;\n \tu32 rx_hwtstamp_cleared;\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_ptp.c b/drivers/net/ethernet/intel/i40e/i40e_ptp.c\nindex 43d7c44..4cc8522 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_ptp.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_ptp.c\n@@ -16,9 +16,9 @@\n * At 1Gb link, the period is multiplied by 20. (32ns)\n * 1588 functionality is not supported at 100Mbps.\n */\n-#define I40E_PTP_40GB_INCVAL 0x0199999999ULL\n-#define I40E_PTP_10GB_INCVAL 0x0333333333ULL\n-#define I40E_PTP_1GB_INCVAL 0x2000000000ULL\n+#define I40E_PTP_40GB_INCVAL 0x0199999999ULL\n+#define I40E_PTP_10GB_INCVAL_MULT 2\n+#define I40E_PTP_1GB_INCVAL_MULT 20\n \n #define I40E_PRTTSYN_CTL1_TSYNTYPE_V1 BIT(I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT)\n #define I40E_PRTTSYN_CTL1_TSYNTYPE_V2 (2 << \\\n@@ -106,17 +106,24 @@ static int i40e_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)\n \t\tppb = -ppb;\n \t}\n \n-\tsmp_mb(); /* Force any pending update before accessing. */\n-\tadj = READ_ONCE(pf->ptp_base_adj);\n-\n-\tfreq = adj;\n+\tfreq = I40E_PTP_40GB_INCVAL;\n \tfreq *= ppb;\n \tdiff = div_u64(freq, 1000000000ULL);\n \n \tif (neg_adj)\n-\t\tadj -= diff;\n+\t\tadj = I40E_PTP_40GB_INCVAL - diff;\n \telse\n-\t\tadj += diff;\n+\t\tadj = I40E_PTP_40GB_INCVAL + diff;\n+\n+\t/* At some link speeds, the base incval is so large that directly\n+\t * multiplying by ppb would result in arithmetic overflow even when\n+\t * using a u64. Avoid this by instead calculating the new incval\n+\t * always in terms of the 40GbE clock rate and then multiplying by the\n+\t * link speed factor afterwards. This does result in slightly lower\n+\t * precision at lower link speeds, but it is fairly minor.\n+\t */\n+\tsmp_mb(); /* Force any pending update before accessing. */\n+\tadj *= READ_ONCE(pf->ptp_adj_mult);\n \n \twr32(hw, I40E_PRTTSYN_INC_L, adj & 0xFFFFFFFF);\n \twr32(hw, I40E_PRTTSYN_INC_H, adj >> 32);\n@@ -438,6 +445,7 @@ void i40e_ptp_set_increment(struct i40e_pf *pf)\n \tstruct i40e_link_status *hw_link_info;\n \tstruct i40e_hw *hw = &pf->hw;\n \tu64 incval;\n+\tu32 mult;\n \n \thw_link_info = &hw->phy.link_info;\n \n@@ -445,10 +453,10 @@ void i40e_ptp_set_increment(struct i40e_pf *pf)\n \n \tswitch (hw_link_info->link_speed) {\n \tcase I40E_LINK_SPEED_10GB:\n-\t\tincval = I40E_PTP_10GB_INCVAL;\n+\t\tmult = I40E_PTP_10GB_INCVAL_MULT;\n \t\tbreak;\n \tcase I40E_LINK_SPEED_1GB:\n-\t\tincval = I40E_PTP_1GB_INCVAL;\n+\t\tmult = I40E_PTP_1GB_INCVAL_MULT;\n \t\tbreak;\n \tcase I40E_LINK_SPEED_100MB:\n \t{\n@@ -459,15 +467,20 @@ void i40e_ptp_set_increment(struct i40e_pf *pf)\n \t\t\t\t \"1588 functionality is not supported at 100 Mbps. Stopping the PHC.\\n\");\n \t\t\twarn_once++;\n \t\t}\n-\t\tincval = 0;\n+\t\tmult = 0;\n \t\tbreak;\n \t}\n \tcase I40E_LINK_SPEED_40GB:\n \tdefault:\n-\t\tincval = I40E_PTP_40GB_INCVAL;\n+\t\tmult = 1;\n \t\tbreak;\n \t}\n \n+\t/* The increment value is calculated by taking the base 40GbE incvalue\n+\t * and multiplying it by a factor based on the link speed.\n+\t */\n+\tincval = I40E_PTP_40GB_INCVAL * mult;\n+\n \t/* Write the new increment value into the increment register. The\n \t * hardware will not update the clock until both registers have been\n \t * written.\n@@ -476,7 +489,7 @@ void i40e_ptp_set_increment(struct i40e_pf *pf)\n \twr32(hw, I40E_PRTTSYN_INC_H, incval >> 32);\n \n \t/* Update the base adjustement value. */\n-\tWRITE_ONCE(pf->ptp_base_adj, incval);\n+\tWRITE_ONCE(pf->ptp_adj_mult, mult);\n \tsmp_mb(); /* Force the above update. */\n }\n \n", "prefixes": [ "next", "S90", "6/8" ] }