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GET /api/patches/897378/?format=api
{ "id": 897378, "url": "http://patchwork.ozlabs.org/api/patches/897378/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20180411192133.25503-1-anirudh.venkataramanan@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20180411192133.25503-1-anirudh.venkataramanan@intel.com>", "list_archive_url": null, "date": "2018-04-11T19:21:33", "name": "[v2] ice: Do not check INTEVENT bit for OICR interrupts", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "a9f00ed74b2810dfb026b3022ea7cc904bbe72be", "submitter": { "id": 73601, "url": "http://patchwork.ozlabs.org/api/people/73601/?format=api", "name": "Anirudh Venkataramanan", "email": "anirudh.venkataramanan@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20180411192133.25503-1-anirudh.venkataramanan@intel.com/mbox/", "series": [ { "id": 38510, "url": "http://patchwork.ozlabs.org/api/series/38510/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=38510", "date": "2018-04-11T19:21:33", "name": "[v2] ice: Do not check INTEVENT bit for OICR interrupts", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/38510/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/897378/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/897378/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=osuosl.org\n\t(client-ip=140.211.166.133; helo=hemlock.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=none (p=none dis=none) header.from=intel.com" ], "Received": [ "from hemlock.osuosl.org (smtp2.osuosl.org [140.211.166.133])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 40Lv6W1cvzz9s1l\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 12 Apr 2018 05:21:39 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id 8777C872E2;\n\tWed, 11 Apr 2018 19:21:37 +0000 (UTC)", "from hemlock.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id Dhw7N31fKMiY; Wed, 11 Apr 2018 19:21:35 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id DFCDF872AA;\n\tWed, 11 Apr 2018 19:21:35 +0000 (UTC)", "from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136])\n\tby ash.osuosl.org (Postfix) with ESMTP id 1652E1C3ED2\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tWed, 11 Apr 2018 19:21:35 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby silver.osuosl.org (Postfix) with ESMTP id 121BE228A5\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tWed, 11 Apr 2018 19:21:35 +0000 (UTC)", "from silver.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id 5SkHrhDHrI4L for <intel-wired-lan@lists.osuosl.org>;\n\tWed, 11 Apr 2018 19:21:34 +0000 (UTC)", "from mga03.intel.com (mga03.intel.com [134.134.136.65])\n\tby silver.osuosl.org (Postfix) with ESMTPS id 5BAE722773\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tWed, 11 Apr 2018 19:21:34 +0000 (UTC)", "from orsmga004.jf.intel.com ([10.7.209.38])\n\tby orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t11 Apr 2018 12:21:33 -0700", "from shasta.jf.intel.com ([10.166.241.32])\n\tby orsmga004.jf.intel.com with ESMTP; 11 Apr 2018 12:21:33 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.48,437,1517904000\"; d=\"scan'208\";a=\"190752646\"", "From": "Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Wed, 11 Apr 2018 12:21:33 -0700", "Message-Id": "<20180411192133.25503-1-anirudh.venkataramanan@intel.com>", "X-Mailer": "git-send-email 2.14.3", "Subject": "[Intel-wired-lan] [PATCH v2] ice: Do not check INTEVENT bit for\n\tOICR interrupts", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.24", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "From: Ben Shelton <benjamin.h.shelton@intel.com>\n\nAccording to the hardware spec, checking the INTEVENT bit isn't a\nreliable way to detect if an OICR interrupt has occurred. This is\nbecause this bit can be cleared by the hardware/firmware before the\ninterrupt service routine has run. So instead, just check for OICR\nevents everytime.\n\nFixes: 940b61af02f4 (\"ice: Initialize PF and setup miscellaneous\ninterrupt\")\n\nSigned-off-by: Ben Shelton <benjamin.h.shelton@intel.com>\nSigned-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>\n\n---\nv2: Add credits to the original author and fix formatting for \"Fixes\"\n---\n drivers/net/ethernet/intel/ice/ice_hw_autogen.h | 2 --\n drivers/net/ethernet/intel/ice/ice_main.c | 4 ----\n 2 files changed, 6 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/ice/ice_hw_autogen.h b/drivers/net/ethernet/intel/ice/ice_hw_autogen.h\nindex 1b9e2ef48a9d..499904874b3f 100644\n--- a/drivers/net/ethernet/intel/ice/ice_hw_autogen.h\n+++ b/drivers/net/ethernet/intel/ice/ice_hw_autogen.h\n@@ -121,8 +121,6 @@\n #define PFINT_FW_CTL_CAUSE_ENA_S\t30\n #define PFINT_FW_CTL_CAUSE_ENA_M\tBIT(PFINT_FW_CTL_CAUSE_ENA_S)\n #define PFINT_OICR\t\t\t0x0016CA00\n-#define PFINT_OICR_INTEVENT_S\t\t0\n-#define PFINT_OICR_INTEVENT_M\t\tBIT(PFINT_OICR_INTEVENT_S)\n #define PFINT_OICR_HLP_RDY_S\t\t14\n #define PFINT_OICR_HLP_RDY_M\t\tBIT(PFINT_OICR_HLP_RDY_S)\n #define PFINT_OICR_CPM_RDY_S\t\t15\ndiff --git a/drivers/net/ethernet/intel/ice/ice_main.c b/drivers/net/ethernet/intel/ice/ice_main.c\nindex 210b7910f1cd..5299caf55a7f 100644\n--- a/drivers/net/ethernet/intel/ice/ice_main.c\n+++ b/drivers/net/ethernet/intel/ice/ice_main.c\n@@ -1722,9 +1722,6 @@ static irqreturn_t ice_misc_intr(int __always_unused irq, void *data)\n \toicr = rd32(hw, PFINT_OICR);\n \tena_mask = rd32(hw, PFINT_OICR_ENA);\n \n-\tif (!(oicr & PFINT_OICR_INTEVENT_M))\n-\t\tgoto ena_intr;\n-\n \tif (oicr & PFINT_OICR_GRST_M) {\n \t\tu32 reset;\n \t\t/* we have a reset warning */\n@@ -1782,7 +1779,6 @@ static irqreturn_t ice_misc_intr(int __always_unused irq, void *data)\n \t}\n \tret = IRQ_HANDLED;\n \n-ena_intr:\n \t/* re-enable interrupt causes that are not handled during this pass */\n \twr32(hw, PFINT_OICR_ENA, ena_mask);\n \tif (!test_bit(__ICE_DOWN, pf->state)) {\n", "prefixes": [ "v2" ] }