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GET /api/patches/887908/?format=api
{ "id": 887908, "url": "http://patchwork.ozlabs.org/api/patches/887908/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20180319215644.31978-3-jeffrey.t.kirsher@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20180319215644.31978-3-jeffrey.t.kirsher@intel.com>", "list_archive_url": null, "date": "2018-03-19T21:56:32", "name": "[v3,03/15] ice: Start hardware initialization", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "29a0e75e9a1f08914b8004f898a0995ea36390eb", "submitter": { "id": 473, "url": "http://patchwork.ozlabs.org/api/people/473/?format=api", "name": "Kirsher, Jeffrey T", "email": "jeffrey.t.kirsher@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20180319215644.31978-3-jeffrey.t.kirsher@intel.com/mbox/", "series": [ { "id": 34702, "url": "http://patchwork.ozlabs.org/api/series/34702/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=34702", "date": "2018-03-19T21:56:30", "name": "[v3,01/15] ice: Add basic driver framework for Intel(R) E800 Series", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/34702/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/887908/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/887908/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=osuosl.org\n\t(client-ip=140.211.166.136; helo=silver.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=none (p=none dis=none) header.from=intel.com" ], "Received": [ "from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 404qdh4sJpz9sVM\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 20 Mar 2018 08:56:24 +1100 (AEDT)", "from localhost (localhost [127.0.0.1])\n\tby silver.osuosl.org (Postfix) with ESMTP id 13BB226230;\n\tMon, 19 Mar 2018 21:56:23 +0000 (UTC)", "from silver.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id UMoltu548R3R; Mon, 19 Mar 2018 21:56:14 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby silver.osuosl.org (Postfix) with ESMTP id F36DF26021;\n\tMon, 19 Mar 2018 21:56:13 +0000 (UTC)", "from hemlock.osuosl.org (smtp2.osuosl.org [140.211.166.133])\n\tby ash.osuosl.org (Postfix) with ESMTP id 1AE0C1C2272\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tMon, 19 Mar 2018 21:56:12 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id 1703F89259\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tMon, 19 Mar 2018 21:56:12 +0000 (UTC)", "from hemlock.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id 3sex1dvCCiAt for <intel-wired-lan@lists.osuosl.org>;\n\tMon, 19 Mar 2018 21:56:08 +0000 (UTC)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n\tby hemlock.osuosl.org (Postfix) with ESMTPS id 83D5288ED1\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tMon, 19 Mar 2018 21:56:08 +0000 (UTC)", "from orsmga008.jf.intel.com ([10.7.209.65])\n\tby orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t19 Mar 2018 14:56:07 -0700", "from jtkirshe-nuc.jf.intel.com ([134.134.177.59])\n\tby orsmga008.jf.intel.com with ESMTP; 19 Mar 2018 14:56:07 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.48,332,1517904000\"; d=\"scan'208\";a=\"26667080\"", "From": "Jeff Kirsher <jeffrey.t.kirsher@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Mon, 19 Mar 2018 14:56:32 -0700", "Message-Id": "<20180319215644.31978-3-jeffrey.t.kirsher@intel.com>", "X-Mailer": "git-send-email 2.14.3", "In-Reply-To": "<20180319215644.31978-1-jeffrey.t.kirsher@intel.com>", "References": "<20180319215644.31978-1-jeffrey.t.kirsher@intel.com>", "Subject": "[Intel-wired-lan] [PATCH v3 03/15] ice: Start hardware\n\tinitialization", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.24", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "From: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>\n\nThis patch implements multiple pieces of the initialization flow\nas follows:\n\n1) A reset is issued to ensure a clean device state, followed\n by initialization of admin queue interface.\n\n2) Once the admin queue interface is up, clear the PF config\n and transition the device to non-PXE mode.\n\n3) Get the NVM configuration stored in the device's non-volatile\n memory (NVM) using ice_init_nvm.\n\nCC: Shannon Nelson <shannon.nelson@oracle.com>\nSigned-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>\nAcked-by: Shannon Nelson <shannon.nelson@oracle.com>\n---\n drivers/net/ethernet/intel/ice/Makefile | 3 +-\n drivers/net/ethernet/intel/ice/ice.h | 2 +\n drivers/net/ethernet/intel/ice/ice_adminq_cmd.h | 79 +++++\n drivers/net/ethernet/intel/ice/ice_common.c | 405 ++++++++++++++++++++++++\n drivers/net/ethernet/intel/ice/ice_common.h | 11 +\n drivers/net/ethernet/intel/ice/ice_controlq.h | 3 +\n drivers/net/ethernet/intel/ice/ice_hw_autogen.h | 30 ++\n drivers/net/ethernet/intel/ice/ice_main.c | 31 ++\n drivers/net/ethernet/intel/ice/ice_nvm.c | 250 +++++++++++++++\n drivers/net/ethernet/intel/ice/ice_osdep.h | 1 +\n drivers/net/ethernet/intel/ice/ice_status.h | 5 +\n drivers/net/ethernet/intel/ice/ice_type.h | 49 +++\n 12 files changed, 868 insertions(+), 1 deletion(-)\n create mode 100644 drivers/net/ethernet/intel/ice/ice_nvm.c", "diff": "diff --git a/drivers/net/ethernet/intel/ice/Makefile b/drivers/net/ethernet/intel/ice/Makefile\nindex eebf619e84a8..373d481dbb25 100644\n--- a/drivers/net/ethernet/intel/ice/Makefile\n+++ b/drivers/net/ethernet/intel/ice/Makefile\n@@ -26,4 +26,5 @@ obj-$(CONFIG_ICE) += ice.o\n \n ice-y := ice_main.o\t\\\n \t ice_controlq.o\t\\\n-\t ice_common.o\n+\t ice_common.o\t\\\n+\t ice_nvm.o\ndiff --git a/drivers/net/ethernet/intel/ice/ice.h b/drivers/net/ethernet/intel/ice/ice.h\nindex ea2fb63bb095..ab2800c31906 100644\n--- a/drivers/net/ethernet/intel/ice/ice.h\n+++ b/drivers/net/ethernet/intel/ice/ice.h\n@@ -30,8 +30,10 @@\n #include <linux/bitmap.h>\n #include \"ice_devids.h\"\n #include \"ice_type.h\"\n+#include \"ice_common.h\"\n \n #define ICE_BAR0\t\t0\n+#define ICE_AQ_LEN\t\t64\n \n #define ICE_DFLT_NETIF_M (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)\n \ndiff --git a/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h b/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h\nindex 885fa3c6fec4..05b22a1ffd70 100644\n--- a/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h\n+++ b/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h\n@@ -50,6 +50,67 @@ struct ice_aqc_q_shutdown {\n \tu8 reserved[12];\n };\n \n+/* Request resource ownership (direct 0x0008)\n+ * Release resource ownership (direct 0x0009)\n+ */\n+struct ice_aqc_req_res {\n+\t__le16 res_id;\n+#define ICE_AQC_RES_ID_NVM\t\t1\n+#define ICE_AQC_RES_ID_SDP\t\t2\n+#define ICE_AQC_RES_ID_CHNG_LOCK\t3\n+#define ICE_AQC_RES_ID_GLBL_LOCK\t4\n+\t__le16 access_type;\n+#define ICE_AQC_RES_ACCESS_READ\t\t1\n+#define ICE_AQC_RES_ACCESS_WRITE\t2\n+\n+\t/* Upon successful completion, FW writes this value and driver is\n+\t * expected to release resource before timeout. This value is provided\n+\t * in milliseconds.\n+\t */\n+\t__le32 timeout;\n+#define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS\t3000\n+#define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS\t180000\n+#define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS\t1000\n+#define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS\t3000\n+\t/* For SDP: pin id of the SDP */\n+\t__le32 res_number;\n+\t/* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */\n+\t__le16 status;\n+#define ICE_AQ_RES_GLBL_SUCCESS\t\t0\n+#define ICE_AQ_RES_GLBL_IN_PROG\t\t1\n+#define ICE_AQ_RES_GLBL_DONE\t\t2\n+\tu8 reserved[2];\n+};\n+\n+/* Clear PXE Command and response (direct 0x0110) */\n+struct ice_aqc_clear_pxe {\n+\tu8 rx_cnt;\n+#define ICE_AQC_CLEAR_PXE_RX_CNT\t\t0x2\n+\tu8 reserved[15];\n+};\n+\n+/* NVM Read command (indirect 0x0701)\n+ * NVM Erase commands (direct 0x0702)\n+ * NVM Update commands (indirect 0x0703)\n+ */\n+struct ice_aqc_nvm {\n+\tu8\tcmd_flags;\n+#define ICE_AQC_NVM_LAST_CMD\t\tBIT(0)\n+#define ICE_AQC_NVM_PCIR_REQ\t\tBIT(0)\t/* Used by NVM Update reply */\n+#define ICE_AQC_NVM_PRESERVATION_S\t1\n+#define ICE_AQC_NVM_PRESERVATION_M\t(3 << CSR_AQ_NVM_PRESERVATION_S)\n+#define ICE_AQC_NVM_NO_PRESERVATION\t(0 << CSR_AQ_NVM_PRESERVATION_S)\n+#define ICE_AQC_NVM_PRESERVE_ALL\tBIT(1)\n+#define ICE_AQC_NVM_PRESERVE_SELECTED\t(3 << CSR_AQ_NVM_PRESERVATION_S)\n+#define ICE_AQC_NVM_FLASH_ONLY\t\tBIT(7)\n+\tu8\tmodule_typeid;\n+\t__le16\tlength;\n+#define ICE_AQC_NVM_ERASE_LEN\t0xFFFF\n+\t__le32\toffset;\n+\t__le32\taddr_high;\n+\t__le32\taddr_low;\n+};\n+\n /**\n * struct ice_aq_desc - Admin Queue (AQ) descriptor\n * @flags: ICE_AQ_FLAG_* flags\n@@ -79,6 +140,9 @@ struct ice_aq_desc {\n \t\tstruct ice_aqc_generic generic;\n \t\tstruct ice_aqc_get_ver get_ver;\n \t\tstruct ice_aqc_q_shutdown q_shutdown;\n+\t\tstruct ice_aqc_req_res res_owner;\n+\t\tstruct ice_aqc_clear_pxe clear_pxe;\n+\t\tstruct ice_aqc_nvm nvm;\n \t} params;\n };\n \n@@ -96,6 +160,8 @@ struct ice_aq_desc {\n /* error codes */\n enum ice_aq_err {\n \tICE_AQ_RC_OK\t\t= 0, /* success */\n+\tICE_AQ_RC_EBUSY\t\t= 12, /* Device or resource busy */\n+\tICE_AQ_RC_EEXIST\t= 13, /* object already exists */\n };\n \n /* Admin Queue command opcodes */\n@@ -103,6 +169,19 @@ enum ice_adminq_opc {\n \t/* AQ commands */\n \tice_aqc_opc_get_ver\t\t\t\t= 0x0001,\n \tice_aqc_opc_q_shutdown\t\t\t\t= 0x0003,\n+\n+\t/* resource ownership */\n+\tice_aqc_opc_req_res\t\t\t\t= 0x0008,\n+\tice_aqc_opc_release_res\t\t\t\t= 0x0009,\n+\n+\t/* PXE */\n+\tice_aqc_opc_clear_pxe_mode\t\t\t= 0x0110,\n+\n+\tice_aqc_opc_clear_pf_cfg\t\t\t= 0x02A4,\n+\n+\t/* NVM commands */\n+\tice_aqc_opc_nvm_read\t\t\t\t= 0x0701,\n+\n };\n \n #endif /* _ICE_ADMINQ_CMD_H_ */\ndiff --git a/drivers/net/ethernet/intel/ice/ice_common.c b/drivers/net/ethernet/intel/ice/ice_common.c\nindex d980f0518744..04cee856d456 100644\n--- a/drivers/net/ethernet/intel/ice/ice_common.c\n+++ b/drivers/net/ethernet/intel/ice/ice_common.c\n@@ -18,6 +18,224 @@\n #include \"ice_common.h\"\n #include \"ice_adminq_cmd.h\"\n \n+#define ICE_PF_RESET_WAIT_COUNT\t200\n+\n+/**\n+ * ice_set_mac_type - Sets MAC type\n+ * @hw: pointer to the HW structure\n+ *\n+ * This function sets the MAC type of the adapter based on the\n+ * vendor ID and device ID stored in the hw structure.\n+ */\n+static enum ice_status ice_set_mac_type(struct ice_hw *hw)\n+{\n+\tif (hw->vendor_id != PCI_VENDOR_ID_INTEL)\n+\t\treturn ICE_ERR_DEVICE_NOT_SUPPORTED;\n+\n+\thw->mac_type = ICE_MAC_GENERIC;\n+\treturn 0;\n+}\n+\n+/**\n+ * ice_clear_pf_cfg - Clear PF configuration\n+ * @hw: pointer to the hardware structure\n+ */\n+enum ice_status ice_clear_pf_cfg(struct ice_hw *hw)\n+{\n+\tstruct ice_aq_desc desc;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg);\n+\n+\treturn ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);\n+}\n+\n+/**\n+ * ice_init_hw - main hardware initialization routine\n+ * @hw: pointer to the hardware structure\n+ */\n+enum ice_status ice_init_hw(struct ice_hw *hw)\n+{\n+\tenum ice_status status;\n+\n+\t/* Set MAC type based on DeviceID */\n+\tstatus = ice_set_mac_type(hw);\n+\tif (status)\n+\t\treturn status;\n+\n+\thw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) &\n+\t\t\t PF_FUNC_RID_FUNC_NUM_M) >>\n+\t\tPF_FUNC_RID_FUNC_NUM_S;\n+\n+\tstatus = ice_reset(hw, ICE_RESET_PFR);\n+\tif (status)\n+\t\treturn status;\n+\n+\tstatus = ice_init_all_ctrlq(hw);\n+\tif (status)\n+\t\tgoto err_unroll_cqinit;\n+\n+\tstatus = ice_clear_pf_cfg(hw);\n+\tif (status)\n+\t\tgoto err_unroll_cqinit;\n+\n+\tice_clear_pxe_mode(hw);\n+\n+\tstatus = ice_init_nvm(hw);\n+\tif (status)\n+\t\tgoto err_unroll_cqinit;\n+\n+\treturn 0;\n+\n+err_unroll_cqinit:\n+\tice_shutdown_all_ctrlq(hw);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_deinit_hw - unroll initialization operations done by ice_init_hw\n+ * @hw: pointer to the hardware structure\n+ */\n+void ice_deinit_hw(struct ice_hw *hw)\n+{\n+\tice_shutdown_all_ctrlq(hw);\n+}\n+\n+/**\n+ * ice_check_reset - Check to see if a global reset is complete\n+ * @hw: pointer to the hardware structure\n+ */\n+enum ice_status ice_check_reset(struct ice_hw *hw)\n+{\n+\tu32 cnt, reg = 0, grst_delay;\n+\n+\t/* Poll for Device Active state in case a recent CORER, GLOBR,\n+\t * or EMPR has occurred. The grst delay value is in 100ms units.\n+\t * Add 1sec for outstanding AQ commands that can take a long time.\n+\t */\n+\tgrst_delay = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >>\n+\t\t GLGEN_RSTCTL_GRSTDEL_S) + 10;\n+\n+\tfor (cnt = 0; cnt < grst_delay; cnt++) {\n+\t\tmdelay(100);\n+\t\treg = rd32(hw, GLGEN_RSTAT);\n+\t\tif (!(reg & GLGEN_RSTAT_DEVSTATE_M))\n+\t\t\tbreak;\n+\t}\n+\n+\tif (cnt == grst_delay) {\n+\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t \"Global reset polling failed to complete.\\n\");\n+\t\treturn ICE_ERR_RESET_FAILED;\n+\t}\n+\n+#define ICE_RESET_DONE_MASK\t(GLNVM_ULD_CORER_DONE_M | \\\n+\t\t\t\t GLNVM_ULD_GLOBR_DONE_M)\n+\n+\t/* Device is Active; check Global Reset processes are done */\n+\tfor (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {\n+\t\treg = rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK;\n+\t\tif (reg == ICE_RESET_DONE_MASK) {\n+\t\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t\t \"Global reset processes done. %d\\n\", cnt);\n+\t\t\tbreak;\n+\t\t}\n+\t\tmdelay(10);\n+\t}\n+\n+\tif (cnt == ICE_PF_RESET_WAIT_COUNT) {\n+\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t \"Wait for Reset Done timed out. GLNVM_ULD = 0x%x\\n\",\n+\t\t\t reg);\n+\t\treturn ICE_ERR_RESET_FAILED;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * ice_pf_reset - Reset the PF\n+ * @hw: pointer to the hardware structure\n+ *\n+ * If a global reset has been triggered, this function checks\n+ * for its completion and then issues the PF reset\n+ */\n+static enum ice_status ice_pf_reset(struct ice_hw *hw)\n+{\n+\tu32 cnt, reg;\n+\n+\t/* If at function entry a global reset was already in progress, i.e.\n+\t * state is not 'device active' or any of the reset done bits are not\n+\t * set in GLNVM_ULD, there is no need for a PF Reset; poll until the\n+\t * global reset is done.\n+\t */\n+\tif ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) ||\n+\t (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) {\n+\t\t/* poll on global reset currently in progress until done */\n+\t\tif (ice_check_reset(hw))\n+\t\t\treturn ICE_ERR_RESET_FAILED;\n+\n+\t\treturn 0;\n+\t}\n+\n+\t/* Reset the PF */\n+\treg = rd32(hw, PFGEN_CTRL);\n+\n+\twr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));\n+\n+\tfor (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {\n+\t\treg = rd32(hw, PFGEN_CTRL);\n+\t\tif (!(reg & PFGEN_CTRL_PFSWR_M))\n+\t\t\tbreak;\n+\n+\t\tmdelay(1);\n+\t}\n+\n+\tif (cnt == ICE_PF_RESET_WAIT_COUNT) {\n+\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t \"PF reset polling failed to complete.\\n\");\n+\t\treturn ICE_ERR_RESET_FAILED;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * ice_reset - Perform different types of reset\n+ * @hw: pointer to the hardware structure\n+ * @req: reset request\n+ *\n+ * This function triggers a reset as specified by the req parameter.\n+ *\n+ * Note:\n+ * If anything other than a PF reset is triggered, PXE mode is restored.\n+ * This has to be cleared using ice_clear_pxe_mode again, once the AQ\n+ * interface has been restored in the rebuild flow.\n+ */\n+enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req)\n+{\n+\tu32 val = 0;\n+\n+\tswitch (req) {\n+\tcase ICE_RESET_PFR:\n+\t\treturn ice_pf_reset(hw);\n+\tcase ICE_RESET_CORER:\n+\t\tice_debug(hw, ICE_DBG_INIT, \"CoreR requested\\n\");\n+\t\tval = GLGEN_RTRIG_CORER_M;\n+\t\tbreak;\n+\tcase ICE_RESET_GLOBR:\n+\t\tice_debug(hw, ICE_DBG_INIT, \"GlobalR requested\\n\");\n+\t\tval = GLGEN_RTRIG_GLOBR_M;\n+\t\tbreak;\n+\t}\n+\n+\tval |= rd32(hw, GLGEN_RTRIG);\n+\twr32(hw, GLGEN_RTRIG, val);\n+\tice_flush(hw);\n+\n+\t/* wait for the FW to be ready */\n+\treturn ice_check_reset(hw);\n+}\n+\n /**\n * ice_debug_cq\n * @hw: pointer to the hardware structure\n@@ -142,3 +360,190 @@ enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading)\n \n \treturn ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);\n }\n+\n+/**\n+ * ice_aq_req_res\n+ * @hw: pointer to the hw struct\n+ * @res: resource id\n+ * @access: access type\n+ * @sdp_number: resource number\n+ * @timeout: the maximum time in ms that the driver may hold the resource\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * requests common resource using the admin queue commands (0x0008)\n+ */\n+static enum ice_status\n+ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res,\n+\t enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout,\n+\t struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_req_res *cmd_resp;\n+\tstruct ice_aq_desc desc;\n+\tenum ice_status status;\n+\n+\tcmd_resp = &desc.params.res_owner;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res);\n+\n+\tcmd_resp->res_id = cpu_to_le16(res);\n+\tcmd_resp->access_type = cpu_to_le16(access);\n+\tcmd_resp->res_number = cpu_to_le32(sdp_number);\n+\n+\tstatus = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);\n+\t/* The completion specifies the maximum time in ms that the driver\n+\t * may hold the resource in the Timeout field.\n+\t * If the resource is held by someone else, the command completes with\n+\t * busy return value and the timeout field indicates the maximum time\n+\t * the current owner of the resource has to free it.\n+\t */\n+\tif (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY)\n+\t\t*timeout = le32_to_cpu(cmd_resp->timeout);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_aq_release_res\n+ * @hw: pointer to the hw struct\n+ * @res: resource id\n+ * @sdp_number: resource number\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * release common resource using the admin queue commands (0x0009)\n+ */\n+static enum ice_status\n+ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number,\n+\t\t struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_req_res *cmd;\n+\tstruct ice_aq_desc desc;\n+\n+\tcmd = &desc.params.res_owner;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res);\n+\n+\tcmd->res_id = cpu_to_le16(res);\n+\tcmd->res_number = cpu_to_le32(sdp_number);\n+\n+\treturn ice_aq_send_cmd(hw, &desc, NULL, 0, cd);\n+}\n+\n+/**\n+ * ice_acquire_res\n+ * @hw: pointer to the HW structure\n+ * @res: resource id\n+ * @access: access type (read or write)\n+ *\n+ * This function will attempt to acquire the ownership of a resource.\n+ */\n+enum ice_status\n+ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,\n+\t\tenum ice_aq_res_access_type access)\n+{\n+#define ICE_RES_POLLING_DELAY_MS\t10\n+\tu32 delay = ICE_RES_POLLING_DELAY_MS;\n+\tenum ice_status status;\n+\tu32 time_left = 0;\n+\tu32 timeout;\n+\n+\tstatus = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);\n+\n+\t/* An admin queue return code of ICE_AQ_RC_EEXIST means that another\n+\t * driver has previously acquired the resource and performed any\n+\t * necessary updates; in this case the caller does not obtain the\n+\t * resource and has no further work to do.\n+\t */\n+\tif (hw->adminq.sq_last_status == ICE_AQ_RC_EEXIST) {\n+\t\tstatus = ICE_ERR_AQ_NO_WORK;\n+\t\tgoto ice_acquire_res_exit;\n+\t}\n+\n+\tif (status)\n+\t\tice_debug(hw, ICE_DBG_RES,\n+\t\t\t \"resource %d acquire type %d failed.\\n\", res, access);\n+\n+\t/* If necessary, poll until the current lock owner timeouts */\n+\ttimeout = time_left;\n+\twhile (status && timeout && time_left) {\n+\t\tmdelay(delay);\n+\t\ttimeout = (timeout > delay) ? timeout - delay : 0;\n+\t\tstatus = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);\n+\n+\t\tif (hw->adminq.sq_last_status == ICE_AQ_RC_EEXIST) {\n+\t\t\t/* lock free, but no work to do */\n+\t\t\tstatus = ICE_ERR_AQ_NO_WORK;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tif (!status)\n+\t\t\t/* lock acquired */\n+\t\t\tbreak;\n+\t}\n+\tif (status && status != ICE_ERR_AQ_NO_WORK)\n+\t\tice_debug(hw, ICE_DBG_RES, \"resource acquire timed out.\\n\");\n+\n+ice_acquire_res_exit:\n+\tif (status == ICE_ERR_AQ_NO_WORK) {\n+\t\tif (access == ICE_RES_WRITE)\n+\t\t\tice_debug(hw, ICE_DBG_RES,\n+\t\t\t\t \"resource indicates no work to do.\\n\");\n+\t\telse\n+\t\t\tice_debug(hw, ICE_DBG_RES,\n+\t\t\t\t \"Warning: ICE_ERR_AQ_NO_WORK not expected\\n\");\n+\t}\n+\treturn status;\n+}\n+\n+/**\n+ * ice_release_res\n+ * @hw: pointer to the HW structure\n+ * @res: resource id\n+ *\n+ * This function will release a resource using the proper Admin Command.\n+ */\n+void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res)\n+{\n+\tenum ice_status status;\n+\tu32 total_delay = 0;\n+\n+\tstatus = ice_aq_release_res(hw, res, 0, NULL);\n+\n+\t/* there are some rare cases when trying to release the resource\n+\t * results in an admin Q timeout, so handle them correctly\n+\t */\n+\twhile ((status == ICE_ERR_AQ_TIMEOUT) &&\n+\t (total_delay < hw->adminq.sq_cmd_timeout)) {\n+\t\tmdelay(1);\n+\t\tstatus = ice_aq_release_res(hw, res, 0, NULL);\n+\t\ttotal_delay++;\n+\t}\n+}\n+\n+/**\n+ * ice_aq_clear_pxe_mode\n+ * @hw: pointer to the hw struct\n+ *\n+ * Tell the firmware that the driver is taking over from PXE (0x0110).\n+ */\n+static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw)\n+{\n+\tstruct ice_aq_desc desc;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode);\n+\tdesc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT;\n+\n+\treturn ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);\n+}\n+\n+/**\n+ * ice_clear_pxe_mode - clear pxe operations mode\n+ * @hw: pointer to the hw struct\n+ *\n+ * Make sure all PXE mode settings are cleared, including things\n+ * like descriptor fetch/write-back mode.\n+ */\n+void ice_clear_pxe_mode(struct ice_hw *hw)\n+{\n+\tif (ice_check_sq_alive(hw, &hw->adminq))\n+\t\tice_aq_clear_pxe_mode(hw);\n+}\ndiff --git a/drivers/net/ethernet/intel/ice/ice_common.h b/drivers/net/ethernet/intel/ice/ice_common.h\nindex 1e3caecc38c6..0876fd98090a 100644\n--- a/drivers/net/ethernet/intel/ice/ice_common.h\n+++ b/drivers/net/ethernet/intel/ice/ice_common.h\n@@ -23,12 +23,22 @@\n \n void ice_debug_cq(struct ice_hw *hw, u32 mask, void *desc, void *buf,\n \t\t u16 buf_len);\n+enum ice_status ice_init_hw(struct ice_hw *hw);\n+void ice_deinit_hw(struct ice_hw *hw);\n+enum ice_status ice_check_reset(struct ice_hw *hw);\n+enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req);\n enum ice_status ice_init_all_ctrlq(struct ice_hw *hw);\n void ice_shutdown_all_ctrlq(struct ice_hw *hw);\n enum ice_status\n+ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,\n+\t\tenum ice_aq_res_access_type access);\n+void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res);\n+enum ice_status ice_init_nvm(struct ice_hw *hw);\n+enum ice_status\n ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,\n \t\tstruct ice_aq_desc *desc, void *buf, u16 buf_size,\n \t\tstruct ice_sq_cd *cd);\n+void ice_clear_pxe_mode(struct ice_hw *hw);\n bool ice_check_sq_alive(struct ice_hw *hw, struct ice_ctl_q_info *cq);\n enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading);\n void ice_fill_dflt_direct_cmd_desc(struct ice_aq_desc *desc, u16 opcode);\n@@ -36,4 +46,5 @@ enum ice_status\n ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc,\n \t\tvoid *buf, u16 buf_size, struct ice_sq_cd *cd);\n enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd);\n+enum ice_status ice_clear_pf_cfg(struct ice_hw *hw);\n #endif /* _ICE_COMMON_H_ */\ndiff --git a/drivers/net/ethernet/intel/ice/ice_controlq.h b/drivers/net/ethernet/intel/ice/ice_controlq.h\nindex 143578d02aec..835c035419a3 100644\n--- a/drivers/net/ethernet/intel/ice/ice_controlq.h\n+++ b/drivers/net/ethernet/intel/ice/ice_controlq.h\n@@ -20,6 +20,9 @@\n \n #include \"ice_adminq_cmd.h\"\n \n+/* Maximum buffer lengths for all control queue types */\n+#define ICE_AQ_MAX_BUF_LEN 4096\n+\n #define ICE_CTL_Q_DESC(R, i) \\\n \t(&(((struct ice_aq_desc *)((R).desc_buf.va))[i]))\n \ndiff --git a/drivers/net/ethernet/intel/ice/ice_hw_autogen.h b/drivers/net/ethernet/intel/ice/ice_hw_autogen.h\nindex 3d6bb273e4c8..e258a12099b8 100644\n--- a/drivers/net/ethernet/intel/ice/ice_hw_autogen.h\n+++ b/drivers/net/ethernet/intel/ice/ice_hw_autogen.h\n@@ -42,5 +42,35 @@\n #define PF_FW_ATQLEN_ATQENABLE_S\t31\n #define PF_FW_ATQLEN_ATQENABLE_M\tBIT(PF_FW_ATQLEN_ATQENABLE_S)\n #define PF_FW_ATQT\t\t\t0x00080400\n+#define GLGEN_RSTAT\t\t\t0x000B8188\n+#define GLGEN_RSTAT_DEVSTATE_S\t\t0\n+#define GLGEN_RSTAT_DEVSTATE_M\t\tICE_M(0x3, GLGEN_RSTAT_DEVSTATE_S)\n+#define GLGEN_RSTCTL\t\t\t0x000B8180\n+#define GLGEN_RSTCTL_GRSTDEL_S\t\t0\n+#define GLGEN_RSTCTL_GRSTDEL_M\t\tICE_M(0x3F, GLGEN_RSTCTL_GRSTDEL_S)\n+#define GLGEN_RTRIG\t\t\t0x000B8190\n+#define GLGEN_RTRIG_CORER_S\t\t0\n+#define GLGEN_RTRIG_CORER_M\t\tBIT(GLGEN_RTRIG_CORER_S)\n+#define GLGEN_RTRIG_GLOBR_S\t\t1\n+#define GLGEN_RTRIG_GLOBR_M\t\tBIT(GLGEN_RTRIG_GLOBR_S)\n+#define GLGEN_STAT\t\t\t0x000B612C\n+#define PFGEN_CTRL\t\t\t0x00091000\n+#define PFGEN_CTRL_PFSWR_S\t\t0\n+#define PFGEN_CTRL_PFSWR_M\t\tBIT(PFGEN_CTRL_PFSWR_S)\n+#define GLLAN_RCTL_0\t\t\t0x002941F8\n+#define GLNVM_FLA\t\t\t0x000B6108\n+#define GLNVM_FLA_LOCKED_S\t\t6\n+#define GLNVM_FLA_LOCKED_M\t\tBIT(GLNVM_FLA_LOCKED_S)\n+#define GLNVM_GENS\t\t\t0x000B6100\n+#define GLNVM_GENS_SR_SIZE_S\t\t5\n+#define GLNVM_GENS_SR_SIZE_M\t\tICE_M(0x7, GLNVM_GENS_SR_SIZE_S)\n+#define GLNVM_ULD\t\t\t0x000B6008\n+#define GLNVM_ULD_CORER_DONE_S\t\t3\n+#define GLNVM_ULD_CORER_DONE_M\t\tBIT(GLNVM_ULD_CORER_DONE_S)\n+#define GLNVM_ULD_GLOBR_DONE_S\t\t4\n+#define GLNVM_ULD_GLOBR_DONE_M\t\tBIT(GLNVM_ULD_GLOBR_DONE_S)\n+#define PF_FUNC_RID\t\t\t0x0009E880\n+#define PF_FUNC_RID_FUNC_NUM_S\t\t0\n+#define PF_FUNC_RID_FUNC_NUM_M\t\tICE_M(0x7, PF_FUNC_RID_FUNC_NUM_S)\n \n #endif /* _ICE_HW_AUTOGEN_H_ */\ndiff --git a/drivers/net/ethernet/intel/ice/ice_main.c b/drivers/net/ethernet/intel/ice/ice_main.c\nindex 408ae90d6562..2ee4a0547ba3 100644\n--- a/drivers/net/ethernet/intel/ice/ice_main.c\n+++ b/drivers/net/ethernet/intel/ice/ice_main.c\n@@ -40,6 +40,18 @@ MODULE_PARM_DESC(debug, \"netif level (0=none,...,16=all), hw debug_mask (0x8XXXX\n MODULE_PARM_DESC(debug, \"netif level (0=none,...,16=all)\");\n #endif /* !CONFIG_DYNAMIC_DEBUG */\n \n+/**\n+ * ice_set_ctrlq_len - helper function to set controlq length\n+ * @hw: pointer to the hw instance\n+ */\n+static void ice_set_ctrlq_len(struct ice_hw *hw)\n+{\n+\thw->adminq.num_rq_entries = ICE_AQ_LEN;\n+\thw->adminq.num_sq_entries = ICE_AQ_LEN;\n+\thw->adminq.rq_buf_size = ICE_AQ_MAX_BUF_LEN;\n+\thw->adminq.sq_buf_size = ICE_AQ_MAX_BUF_LEN;\n+}\n+\n /**\n * ice_probe - Device initialization routine\n * @pdev: PCI device information struct\n@@ -95,6 +107,8 @@ static int ice_probe(struct pci_dev *pdev,\n \thw->subsystem_device_id = pdev->subsystem_device;\n \thw->bus.device = PCI_SLOT(pdev->devfn);\n \thw->bus.func = PCI_FUNC(pdev->devfn);\n+\tice_set_ctrlq_len(hw);\n+\n \tpf->msg_enable = netif_msg_init(debug, ICE_DFLT_NETIF_M);\n \n #ifndef CONFIG_DYNAMIC_DEBUG\n@@ -102,7 +116,22 @@ static int ice_probe(struct pci_dev *pdev,\n \t\thw->debug_mask = debug;\n #endif\n \n+\terr = ice_init_hw(hw);\n+\tif (err) {\n+\t\tdev_err(&pdev->dev, \"ice_init_hw failed: %d\\n\", err);\n+\t\terr = -EIO;\n+\t\tgoto err_exit_unroll;\n+\t}\n+\n+\tdev_info(&pdev->dev, \"firmware %d.%d.%05d api %d.%d\\n\",\n+\t\t hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,\n+\t\t hw->api_maj_ver, hw->api_min_ver);\n+\n \treturn 0;\n+\n+err_exit_unroll:\n+\tpci_disable_pcie_error_reporting(pdev);\n+\treturn err;\n }\n \n /**\n@@ -117,6 +146,8 @@ static void ice_remove(struct pci_dev *pdev)\n \t\treturn;\n \n \tset_bit(__ICE_DOWN, pf->state);\n+\n+\tice_deinit_hw(&pf->hw);\n \tpci_disable_pcie_error_reporting(pdev);\n }\n \ndiff --git a/drivers/net/ethernet/intel/ice/ice_nvm.c b/drivers/net/ethernet/intel/ice/ice_nvm.c\nnew file mode 100644\nindex 000000000000..76c438db68ff\n--- /dev/null\n+++ b/drivers/net/ethernet/intel/ice/ice_nvm.c\n@@ -0,0 +1,250 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/* Intel(R) Ethernet Connection E800 Series Linux Driver\n+ * Copyright (c) 2018, Intel Corporation.\n+ *\n+ * This program is free software; you can redistribute it and/or modify it\n+ * under the terms and conditions of the GNU General Public License,\n+ * version 2, as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope it will be useful, but WITHOUT\n+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n+ * more details.\n+ *\n+ * The full GNU General Public License is included in this distribution in\n+ * the file called \"COPYING\".\n+ */\n+\n+#include \"ice_common.h\"\n+\n+/**\n+ * ice_aq_read_nvm\n+ * @hw: pointer to the hw struct\n+ * @module_typeid: module pointer location in words from the NVM beginning\n+ * @offset: byte offset from the module beginning\n+ * @length: length of the section to be read (in bytes from the offset)\n+ * @data: command buffer (size [bytes] = length)\n+ * @last_command: tells if this is the last command in a series\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Read the NVM using the admin queue commands (0x0701)\n+ */\n+static enum ice_status\n+ice_aq_read_nvm(struct ice_hw *hw, u8 module_typeid, u32 offset, u16 length,\n+\t\tvoid *data, bool last_command, struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aq_desc desc;\n+\tstruct ice_aqc_nvm *cmd;\n+\n+\tcmd = &desc.params.nvm;\n+\n+\t/* In offset the highest byte must be zeroed. */\n+\tif (offset & 0xFF000000)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_read);\n+\n+\t/* If this is the last command in a series, set the proper flag. */\n+\tif (last_command)\n+\t\tcmd->cmd_flags |= ICE_AQC_NVM_LAST_CMD;\n+\tcmd->module_typeid = module_typeid;\n+\tcmd->offset = cpu_to_le32(offset);\n+\tcmd->length = cpu_to_le16(length);\n+\n+\treturn ice_aq_send_cmd(hw, &desc, data, length, cd);\n+}\n+\n+/**\n+ * ice_check_sr_access_params - verify params for Shadow RAM R/W operations.\n+ * @hw: pointer to the HW structure\n+ * @offset: offset in words from module start\n+ * @words: number of words to access\n+ */\n+static enum ice_status\n+ice_check_sr_access_params(struct ice_hw *hw, u32 offset, u16 words)\n+{\n+\tif ((offset + words) > hw->nvm.sr_words) {\n+\t\tice_debug(hw, ICE_DBG_NVM,\n+\t\t\t \"NVM error: offset beyond SR lmt.\\n\");\n+\t\treturn ICE_ERR_PARAM;\n+\t}\n+\n+\tif (words > ICE_SR_SECTOR_SIZE_IN_WORDS) {\n+\t\t/* We can access only up to 4KB (one sector), in one AQ write */\n+\t\tice_debug(hw, ICE_DBG_NVM,\n+\t\t\t \"NVM error: tried to access %d words, limit is %d.\\n\",\n+\t\t\t words, ICE_SR_SECTOR_SIZE_IN_WORDS);\n+\t\treturn ICE_ERR_PARAM;\n+\t}\n+\n+\tif (((offset + (words - 1)) / ICE_SR_SECTOR_SIZE_IN_WORDS) !=\n+\t (offset / ICE_SR_SECTOR_SIZE_IN_WORDS)) {\n+\t\t/* A single access cannot spread over two sectors */\n+\t\tice_debug(hw, ICE_DBG_NVM,\n+\t\t\t \"NVM error: cannot spread over two sectors.\\n\");\n+\t\treturn ICE_ERR_PARAM;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * ice_read_sr_aq - Read Shadow RAM.\n+ * @hw: pointer to the HW structure\n+ * @offset: offset in words from module start\n+ * @words: number of words to read\n+ * @data: buffer for words reads from Shadow RAM\n+ * @last_command: tells the AdminQ that this is the last command\n+ *\n+ * Reads 16-bit word buffers from the Shadow RAM using the admin command.\n+ */\n+static enum ice_status\n+ice_read_sr_aq(struct ice_hw *hw, u32 offset, u16 words, u16 *data,\n+\t bool last_command)\n+{\n+\tenum ice_status status;\n+\n+\tstatus = ice_check_sr_access_params(hw, offset, words);\n+\n+\t/* values in \"offset\" and \"words\" parameters are sized as words\n+\t * (16 bits) but ice_aq_read_nvm expects these values in bytes.\n+\t * So do this conversion while calling ice_aq_read_nvm.\n+\t */\n+\tif (!status)\n+\t\tstatus = ice_aq_read_nvm(hw, 0, 2 * offset, 2 * words, data,\n+\t\t\t\t\t last_command, NULL);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_read_sr_word_aq - Reads Shadow RAM via AQ\n+ * @hw: pointer to the HW structure\n+ * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)\n+ * @data: word read from the Shadow RAM\n+ *\n+ * Reads one 16 bit word from the Shadow RAM using the ice_read_sr_aq method.\n+ */\n+static enum ice_status\n+ice_read_sr_word_aq(struct ice_hw *hw, u16 offset, u16 *data)\n+{\n+\tenum ice_status status;\n+\n+\tstatus = ice_read_sr_aq(hw, offset, 1, data, true);\n+\tif (!status)\n+\t\t*data = le16_to_cpu(*(__le16 *)data);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_acquire_nvm - Generic request for acquiring the NVM ownership\n+ * @hw: pointer to the HW structure\n+ * @access: NVM access type (read or write)\n+ *\n+ * This function will request NVM ownership.\n+ */\n+static enum\n+ice_status ice_acquire_nvm(struct ice_hw *hw,\n+\t\t\t enum ice_aq_res_access_type access)\n+{\n+\tif (hw->nvm.blank_nvm_mode)\n+\t\treturn 0;\n+\n+\treturn ice_acquire_res(hw, ICE_NVM_RES_ID, access);\n+}\n+\n+/**\n+ * ice_release_nvm - Generic request for releasing the NVM ownership\n+ * @hw: pointer to the HW structure\n+ *\n+ * This function will release NVM ownership.\n+ */\n+static void ice_release_nvm(struct ice_hw *hw)\n+{\n+\tif (hw->nvm.blank_nvm_mode)\n+\t\treturn;\n+\n+\tice_release_res(hw, ICE_NVM_RES_ID);\n+}\n+\n+/**\n+ * ice_read_sr_word - Reads Shadow RAM word and acquire NVM if necessary\n+ * @hw: pointer to the HW structure\n+ * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)\n+ * @data: word read from the Shadow RAM\n+ *\n+ * Reads one 16 bit word from the Shadow RAM using the ice_read_sr_word_aq.\n+ */\n+static enum ice_status\n+ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data)\n+{\n+\tenum ice_status status;\n+\n+\tstatus = ice_acquire_nvm(hw, ICE_RES_READ);\n+\tif (!status) {\n+\t\tstatus = ice_read_sr_word_aq(hw, offset, data);\n+\t\tice_release_nvm(hw);\n+\t}\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_init_nvm - initializes NVM setting\n+ * @hw: pointer to the hw struct\n+ *\n+ * This function reads and populates NVM settings such as Shadow RAM size,\n+ * max_timeout, and blank_nvm_mode\n+ */\n+enum ice_status ice_init_nvm(struct ice_hw *hw)\n+{\n+\tstruct ice_nvm_info *nvm = &hw->nvm;\n+\tu16 eetrack_lo, eetrack_hi;\n+\tenum ice_status status = 0;\n+\tu32 fla, gens_stat;\n+\tu8 sr_size;\n+\n+\t/* The SR size is stored regardless of the nvm programming mode\n+\t * as the blank mode may be used in the factory line.\n+\t */\n+\tgens_stat = rd32(hw, GLNVM_GENS);\n+\tsr_size = (gens_stat & GLNVM_GENS_SR_SIZE_M) >> GLNVM_GENS_SR_SIZE_S;\n+\n+\t/* Switching to words (sr_size contains power of 2) */\n+\tnvm->sr_words = BIT(sr_size) * ICE_SR_WORDS_IN_1KB;\n+\n+\t/* Check if we are in the normal or blank NVM programming mode */\n+\tfla = rd32(hw, GLNVM_FLA);\n+\tif (fla & GLNVM_FLA_LOCKED_M) { /* Normal programming mode */\n+\t\tnvm->blank_nvm_mode = false;\n+\t} else { /* Blank programming mode */\n+\t\tnvm->blank_nvm_mode = true;\n+\t\tstatus = ICE_ERR_NVM_BLANK_MODE;\n+\t\tice_debug(hw, ICE_DBG_NVM,\n+\t\t\t \"NVM init error: unsupported blank mode.\\n\");\n+\t\treturn status;\n+\t}\n+\n+\tstatus = ice_read_sr_word(hw, ICE_SR_NVM_DEV_STARTER_VER, &hw->nvm.ver);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t \"Failed to read DEV starter version.\\n\");\n+\t\treturn status;\n+\t}\n+\n+\tstatus = ice_read_sr_word(hw, ICE_SR_NVM_EETRACK_LO, &eetrack_lo);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_INIT, \"Failed to read EETRACK lo.\\n\");\n+\t\treturn status;\n+\t}\n+\tstatus = ice_read_sr_word(hw, ICE_SR_NVM_EETRACK_HI, &eetrack_hi);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_INIT, \"Failed to read EETRACK hi.\\n\");\n+\t\treturn status;\n+\t}\n+\n+\thw->nvm.eetrack = (eetrack_hi << 16) | eetrack_lo;\n+\n+\treturn status;\n+}\ndiff --git a/drivers/net/ethernet/intel/ice/ice_osdep.h b/drivers/net/ethernet/intel/ice/ice_osdep.h\nindex fc6576a3a9d1..d7af84c714c1 100644\n--- a/drivers/net/ethernet/intel/ice/ice_osdep.h\n+++ b/drivers/net/ethernet/intel/ice/ice_osdep.h\n@@ -29,6 +29,7 @@\n #define wr64(a, reg, value)\twriteq((value), ((a)->hw_addr + (reg)))\n #define rd64(a, reg)\t\treadq((a)->hw_addr + (reg))\n \n+#define ice_flush(a)\t\trd32((a), GLGEN_STAT)\n #define ICE_M(m, s)\t\t((m) << (s))\n \n struct ice_dma_mem {\ndiff --git a/drivers/net/ethernet/intel/ice/ice_status.h b/drivers/net/ethernet/intel/ice/ice_status.h\nindex 940d6f57adcf..1fb6eb8301cf 100644\n--- a/drivers/net/ethernet/intel/ice/ice_status.h\n+++ b/drivers/net/ethernet/intel/ice/ice_status.h\n@@ -23,12 +23,17 @@ enum ice_status {\n \tICE_ERR_PARAM\t\t\t\t= -1,\n \tICE_ERR_NOT_READY\t\t\t= -3,\n \tICE_ERR_INVAL_SIZE\t\t\t= -6,\n+\tICE_ERR_DEVICE_NOT_SUPPORTED\t\t= -8,\n+\tICE_ERR_RESET_FAILED\t\t\t= -9,\n \tICE_ERR_FW_API_VER\t\t\t= -10,\n \tICE_ERR_NO_MEMORY\t\t\t= -11,\n \tICE_ERR_CFG\t\t\t\t= -12,\n+\tICE_ERR_OUT_OF_RANGE\t\t\t= -13,\n+\tICE_ERR_NVM_BLANK_MODE\t\t\t= -53,\n \tICE_ERR_AQ_ERROR\t\t\t= -100,\n \tICE_ERR_AQ_TIMEOUT\t\t\t= -101,\n \tICE_ERR_AQ_FULL\t\t\t\t= -102,\n+\tICE_ERR_AQ_NO_WORK\t\t\t= -103,\n \tICE_ERR_AQ_EMPTY\t\t\t= -104,\n };\n \ndiff --git a/drivers/net/ethernet/intel/ice/ice_type.h b/drivers/net/ethernet/intel/ice/ice_type.h\nindex cfa98e55a33a..e40fab48cf7f 100644\n--- a/drivers/net/ethernet/intel/ice/ice_type.h\n+++ b/drivers/net/ethernet/intel/ice/ice_type.h\n@@ -24,20 +24,58 @@\n #include \"ice_controlq.h\"\n \n /* debug masks - set these bits in hw->debug_mask to control output */\n+#define ICE_DBG_INIT\t\tBIT_ULL(1)\n+#define ICE_DBG_NVM\t\tBIT_ULL(7)\n+#define ICE_DBG_RES\t\tBIT_ULL(17)\n #define ICE_DBG_AQ_MSG\t\tBIT_ULL(24)\n #define ICE_DBG_AQ_CMD\t\tBIT_ULL(27)\n \n+enum ice_aq_res_ids {\n+\tICE_NVM_RES_ID = 1,\n+\tICE_SPD_RES_ID,\n+\tICE_GLOBAL_CFG_LOCK_RES_ID,\n+\tICE_CHANGE_LOCK_RES_ID\n+};\n+\n+enum ice_aq_res_access_type {\n+\tICE_RES_READ = 1,\n+\tICE_RES_WRITE\n+};\n+\n+/* Various MAC types */\n+enum ice_mac_type {\n+\tICE_MAC_UNKNOWN = 0,\n+\tICE_MAC_GENERIC,\n+};\n+\n+/* Various RESET request, These are not tied with HW reset types */\n+enum ice_reset_req {\n+\tICE_RESET_PFR\t= 0,\n+\tICE_RESET_CORER\t= 1,\n+\tICE_RESET_GLOBR\t= 2,\n+};\n+\n /* Bus parameters */\n struct ice_bus_info {\n \tu16 device;\n \tu8 func;\n };\n \n+/* NVM Information */\n+struct ice_nvm_info {\n+\tu32 eetrack; /* NVM data version */\n+\tu32 oem_ver; /* OEM version info */\n+\tu16 sr_words; /* Shadow RAM size in words */\n+\tu16 ver; /* NVM package version */\n+\tbool blank_nvm_mode; /* is NVM empty (no FW present) */\n+};\n+\n /* Port hardware description */\n struct ice_hw {\n \tu8 __iomem *hw_addr;\n \tvoid *back;\n \tu64 debug_mask;\t\t/* bitmap for debug mask */\n+\tenum ice_mac_type mac_type;\n \n \t/* pci info */\n \tu16 device_id;\n@@ -46,7 +84,11 @@ struct ice_hw {\n \tu16 subsystem_vendor_id;\n \tu8 revision_id;\n \n+\tu8 pf_id;\t\t/* device profile info */\n+\n \tstruct ice_bus_info bus;\n+\tstruct ice_nvm_info nvm;\n+\n \t/* Control Queue info */\n \tstruct ice_ctl_q_info adminq;\n \n@@ -61,4 +103,11 @@ struct ice_hw {\n \tu32 fw_build;\t\t/* firmware build number */\n };\n \n+/* Checksum and Shadow RAM pointers */\n+#define ICE_SR_NVM_DEV_STARTER_VER\t0x18\n+#define ICE_SR_NVM_EETRACK_LO\t\t0x2D\n+#define ICE_SR_NVM_EETRACK_HI\t\t0x2E\n+#define ICE_SR_SECTOR_SIZE_IN_WORDS\t0x800\n+#define ICE_SR_WORDS_IN_1KB\t\t512\n+\n #endif /* _ICE_TYPE_H_ */\n", "prefixes": [ "v3", "03/15" ] }