Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/856691/?format=api
{ "id": 856691, "url": "http://patchwork.ozlabs.org/api/patches/856691/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20180108024558.17983-25-f4bug@amsat.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20180108024558.17983-25-f4bug@amsat.org>", "list_archive_url": null, "date": "2018-01-08T02:45:53", "name": "[24/29] hw/i386: extract i440fx code from piix.c into i440fx.c", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "7e1cbf74a235ea6585a8680ac942be9c405d03b3", "submitter": { "id": 70924, "url": "http://patchwork.ozlabs.org/api/people/70924/?format=api", "name": "Philippe Mathieu-Daudé", "email": "f4bug@amsat.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20180108024558.17983-25-f4bug@amsat.org/mbox/", "series": [ { "id": 21847, "url": "http://patchwork.ozlabs.org/api/series/21847/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=21847", "date": "2018-01-08T02:45:30", "name": "remove i386/pc dependency: generic SuperIO, PIIX cleanup", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/21847/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/856691/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/856691/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"USrQPSKV\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3zFL0W6SCXz9s71\n\tfor <incoming@patchwork.ozlabs.org>;\n\tMon, 8 Jan 2018 14:11:55 +1100 (AEDT)", "from localhost ([::1]:60366 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1eYNqs-0003Fy-0r\n\tfor incoming@patchwork.ozlabs.org; Sun, 07 Jan 2018 22:11:54 -0500", "from eggs.gnu.org ([2001:4830:134:3::10]:51760)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <philippe.mathieu.daude@gmail.com>)\n\tid 1eYNTN-0007eD-Kr\n\tfor qemu-devel@nongnu.org; Sun, 07 Jan 2018 21:47:41 -0500", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <philippe.mathieu.daude@gmail.com>)\n\tid 1eYNTJ-0003Gy-Qb\n\tfor qemu-devel@nongnu.org; Sun, 07 Jan 2018 21:47:37 -0500", "from mail-qk0-x22d.google.com ([2607:f8b0:400d:c09::22d]:34179)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <philippe.mathieu.daude@gmail.com>)\n\tid 1eYNTJ-0003Fz-IZ\n\tfor qemu-devel@nongnu.org; Sun, 07 Jan 2018 21:47:33 -0500", "by mail-qk0-x22d.google.com with SMTP id m193so4290966qke.1\n\tfor <qemu-devel@nongnu.org>; Sun, 07 Jan 2018 18:47:33 -0800 (PST)", "from x1.local ([138.117.48.219]) by smtp.gmail.com with ESMTPSA id\n\td10sm7156245qkg.16.2018.01.07.18.47.28\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tSun, 07 Jan 2018 18:47:31 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=sender:from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=wbwemXjrNzydoZJzZElOwzcM2tIhwETP2/vBVfOJwRA=;\n\tb=USrQPSKV9Tfjr25+fw9FkT+kfFNbgiCqExYMfnLVIGxNFXvojVEndjHojGULmEXHC2\n\tgM4/cev6Bluc6Po/e7TMUvrUkR4OJgcGiq8LGFZkqIu0KBIJb1kKlTfeiQ/pt+4/LCw5\n\tFFzbJbJBUa+VFkFdOJwXZASQk6eYfViUky3B1X5GbJY0QXwq2PfjnLmKAorwxjt3zRna\n\tBVX8eFe8ZXmeRyron+zuV8ZJ2eWKnVGwk2PgcCjTvKRVHeB9lgyjHaLNKZG6870fgm8L\n\t91tA96jx+AbUGTEf9t5WgrY2l8xN1xlOe5yX+X0CZYkO00h/SRw/0HlY33gcN/HXn+0A\n\tgexA==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:sender:from:to:cc:subject:date:message-id\n\t:in-reply-to:references:mime-version:content-transfer-encoding;\n\tbh=wbwemXjrNzydoZJzZElOwzcM2tIhwETP2/vBVfOJwRA=;\n\tb=TVxbA0BslIRdfvM1er5bhP/K2L53HVR4WisnEs1HRfTCZjcboa9JzMmwOv18TmUM8R\n\tcT/UZ5b/nRIdKisNG4KCGmgKeCVt45muJIKoBvWRCpLFl6Kfx1uBQqGUsd/pDUBXNgkH\n\tNDBVG6xB8/T9Y2twHMnq6TFsajFssFEQmqqscnZFtK9KaK6ArMSikwXNA6lN1gFapNQ7\n\tdkEs9RL05GsCe417wgsBQlgHpkZ0C41T46vZAtoPU33xGdMhkMelfD2pg0fNzn8qslCV\n\toVEQIYnmfc0tcQ4/XMg2j+oiKPj6ZvANnGp5K/IxES2EwTYAm3SFYmQjhvRGN1M8MWBJ\n\tEMyw==", "X-Gm-Message-State": "AKwxyteEUwZJBBeoUwJ2NVgaua9FHPM/ziwJ20XV362haJYnoAbbRl0d\n\tyqB1Ch9VeBpy0heEL9GjTbouCa+N", "X-Google-Smtp-Source": "ACJfBotJbIjK44pibRKu5GwL2hpbqLTVAXhQQXsag7CtkY9OY1yCC0afUrsPF0X0J3g4zKcdajGKmg==", "X-Received": "by 10.55.68.79 with SMTP id r76mr14011109qka.187.1515379652534; \n\tSun, 07 Jan 2018 18:47:32 -0800 (PST)", "From": "=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <f4bug@amsat.org>", "To": "Paolo Bonzini <pbonzini@redhat.com>,\n\t\"Michael S. Tsirkin\" <mst@redhat.com>, =?utf-8?q?Herv=C3=A9_Poussinea?=\n\t=?utf-8?q?u?= <hpoussin@reactos.org>,\n\tAurelien Jarno <aurelien@aurel32.net>, Eduardo Habkost\n\t<ehabkost@redhat.com>, Marcel Apfelbaum <marcel@redhat.com>", "Date": "Sun, 7 Jan 2018 23:45:53 -0300", "Message-Id": "<20180108024558.17983-25-f4bug@amsat.org>", "X-Mailer": "git-send-email 2.15.1", "In-Reply-To": "<20180108024558.17983-1-f4bug@amsat.org>", "References": "<20180108024558.17983-1-f4bug@amsat.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400d:c09::22d", "Subject": "[Qemu-devel] [PATCH 24/29] hw/i386: extract i440fx code from piix.c\n\tinto i440fx.c", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "Igor Mammedov <imammedo@redhat.com>, =?utf-8?q?Philippe_Mathieu-Daud?=\n\t=?utf-8?b?w6k=?= <f4bug@amsat.org>, \tqemu-devel@nongnu.org", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>\n---\n default-configs/i386-softmmu.mak | 1 +\n default-configs/x86_64-softmmu.mak | 1 +\n hw/pci-host/i440fx.c | 543 +++++++++++++++++++++++++++++++++++++\n hw/pci-host/piix.c | 522 +----------------------------------\n MAINTAINERS | 1 +\n hw/pci-host/Makefile.objs | 1 +\n 6 files changed, 552 insertions(+), 517 deletions(-)\n create mode 100644 hw/pci-host/i440fx.c", "diff": "diff --git a/default-configs/i386-softmmu.mak b/default-configs/i386-softmmu.mak\nindex 95ac4b464a..c7e4af01a5 100644\n--- a/default-configs/i386-softmmu.mak\n+++ b/default-configs/i386-softmmu.mak\n@@ -38,6 +38,7 @@ CONFIG_I8259=y\n CONFIG_PFLASH_CFI01=y\n CONFIG_TPM_TIS=$(CONFIG_TPM)\n CONFIG_MC146818RTC=y\n+CONFIG_PCI_I440FX=y\n CONFIG_PCI_PIIX=y\n CONFIG_WDT_IB700=y\n CONFIG_ISA_DEBUG=y\ndiff --git a/default-configs/x86_64-softmmu.mak b/default-configs/x86_64-softmmu.mak\nindex 0221236825..926997fe60 100644\n--- a/default-configs/x86_64-softmmu.mak\n+++ b/default-configs/x86_64-softmmu.mak\n@@ -38,6 +38,7 @@ CONFIG_I8259=y\n CONFIG_PFLASH_CFI01=y\n CONFIG_TPM_TIS=$(CONFIG_TPM)\n CONFIG_MC146818RTC=y\n+CONFIG_PCI_I440FX=y\n CONFIG_PCI_PIIX=y\n CONFIG_WDT_IB700=y\n CONFIG_ISA_DEBUG=y\ndiff --git a/hw/pci-host/i440fx.c b/hw/pci-host/i440fx.c\nnew file mode 100644\nindex 0000000000..76968f8fbf\n--- /dev/null\n+++ b/hw/pci-host/i440fx.c\n@@ -0,0 +1,543 @@\n+/*\n+ * QEMU i440FX North Bridge Emulation\n+ *\n+ * Copyright (c) 2006 Fabrice Bellard\n+ *\n+ * Permission is hereby granted, free of charge, to any person obtaining a copy\n+ * of this software and associated documentation files (the \"Software\"), to deal\n+ * in the Software without restriction, including without limitation the rights\n+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n+ * copies of the Software, and to permit persons to whom the Software is\n+ * furnished to do so, subject to the following conditions:\n+ *\n+ * The above copyright notice and this permission notice shall be included in\n+ * all copies or substantial portions of the Software.\n+ *\n+ * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n+ * THE SOFTWARE.\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"qemu/error-report.h\"\n+#include \"qapi/error.h\"\n+#include \"qapi/visitor.h\"\n+#include \"hw/hw.h\"\n+#include \"hw/i386/pc.h\"\n+#include \"hw/pci/pci.h\"\n+#include \"hw/pci/pci_host.h\"\n+#include \"hw/pci-host/pam.h\"\n+#include \"hw/pci-host/i440fx.h\"\n+#include \"hw/southbridge/i82371_piix.h\"\n+\n+/*\n+ * I440FX chipset data sheet.\n+ * http://download.intel.com/design/chipsets/datashts/29054901.pdf\n+ */\n+\n+#define I440FX_PCI_HOST_BRIDGE(obj) \\\n+ OBJECT_CHECK(I440FXState, (obj), TYPE_I440FX_PCI_HOST_BRIDGE)\n+\n+typedef struct I440FXState {\n+ PCIHostState parent_obj;\n+ Range pci_hole;\n+ uint64_t pci_hole64_size;\n+ bool pci_hole64_fix;\n+ uint32_t short_root_bus;\n+} I440FXState;\n+\n+#define I440FX_PCI_DEVICE(obj) \\\n+ OBJECT_CHECK(PCII440FXState, (obj), TYPE_I440FX_PCI_DEVICE)\n+\n+struct PCII440FXState {\n+ /*< private >*/\n+ PCIDevice parent_obj;\n+ /*< public >*/\n+\n+ MemoryRegion *system_memory;\n+ MemoryRegion *pci_address_space;\n+ MemoryRegion *ram_memory;\n+ PAMMemoryRegion pam_regions[13];\n+ MemoryRegion smram_region;\n+ MemoryRegion smram, low_smram;\n+};\n+\n+\n+#define I440FX_PAM 0x59\n+#define I440FX_PAM_SIZE 7\n+#define I440FX_SMRAM 0x72\n+\n+/* Keep it 2G to comply with older win32 guests */\n+#define I440FX_PCI_HOST_HOLE64_SIZE_DEFAULT (1ULL << 31)\n+\n+/* Older coreboot versions (4.0 and older) read a config register that doesn't\n+ * exist in real hardware, to get the RAM size from QEMU.\n+ */\n+#define I440FX_COREBOOT_RAM_SIZE 0x57\n+\n+static void i440fx_update_memory_mappings(PCII440FXState *d)\n+{\n+ int i;\n+ PCIDevice *pd = PCI_DEVICE(d);\n+\n+ memory_region_transaction_begin();\n+ for (i = 0; i < 13; i++) {\n+ pam_update(&d->pam_regions[i], i,\n+ pd->config[I440FX_PAM + (DIV_ROUND_UP(i, 2))]);\n+ }\n+ memory_region_set_enabled(&d->smram_region,\n+ !(pd->config[I440FX_SMRAM] & SMRAM_D_OPEN));\n+ memory_region_set_enabled(&d->smram,\n+ pd->config[I440FX_SMRAM] & SMRAM_G_SMRAME);\n+ memory_region_transaction_commit();\n+}\n+\n+\n+static void i440fx_write_config(PCIDevice *dev,\n+ uint32_t address, uint32_t val, int len)\n+{\n+ PCII440FXState *d = I440FX_PCI_DEVICE(dev);\n+\n+ /* XXX: implement SMRAM.D_LOCK */\n+ pci_default_write_config(dev, address, val, len);\n+ if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||\n+ range_covers_byte(address, len, I440FX_SMRAM)) {\n+ i440fx_update_memory_mappings(d);\n+ }\n+}\n+\n+static int i440fx_load_old(QEMUFile *f, void *opaque, int version_id)\n+{\n+ PCII440FXState *d = opaque;\n+ PCIDevice *pd = PCI_DEVICE(d);\n+ int ret, i;\n+ uint8_t smm_enabled;\n+\n+ ret = pci_device_load(pd, f);\n+ if (ret < 0) {\n+ return ret;\n+ }\n+ i440fx_update_memory_mappings(d);\n+ qemu_get_8s(f, &smm_enabled);\n+\n+ if (version_id == 2) {\n+ for (i = 0; i < PIIX_NUM_PIRQS; i++) {\n+ qemu_get_be32(f); /* dummy load for compatibility */\n+ }\n+ }\n+\n+ return 0;\n+}\n+\n+static int i440fx_post_load(void *opaque, int version_id)\n+{\n+ PCII440FXState *d = opaque;\n+\n+ i440fx_update_memory_mappings(d);\n+ return 0;\n+}\n+\n+static const VMStateDescription vmstate_i440fx = {\n+ .name = \"I440FX\",\n+ .version_id = 3,\n+ .minimum_version_id = 3,\n+ .minimum_version_id_old = 1,\n+ .load_state_old = i440fx_load_old,\n+ .post_load = i440fx_post_load,\n+ .fields = (VMStateField[]) {\n+ VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState),\n+ /* Used to be smm_enabled, which was basically always zero because\n+ * SeaBIOS hardly uses SMM. SMRAM is now handled by CPU code.\n+ */\n+ VMSTATE_UNUSED(1),\n+ VMSTATE_END_OF_LIST()\n+ }\n+};\n+\n+static void i440fx_pcihost_get_pci_hole_start(Object *obj, Visitor *v,\n+ const char *name, void *opaque,\n+ Error **errp)\n+{\n+ I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);\n+ uint64_t val64;\n+ uint32_t value;\n+\n+ val64 = range_is_empty(&s->pci_hole) ? 0 : range_lob(&s->pci_hole);\n+ value = val64;\n+ assert(value == val64);\n+ visit_type_uint32(v, name, &value, errp);\n+}\n+\n+static void i440fx_pcihost_get_pci_hole_end(Object *obj, Visitor *v,\n+ const char *name, void *opaque,\n+ Error **errp)\n+{\n+ I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);\n+ uint64_t val64;\n+ uint32_t value;\n+\n+ val64 = range_is_empty(&s->pci_hole) ? 0 : range_upb(&s->pci_hole) + 1;\n+ value = val64;\n+ assert(value == val64);\n+ visit_type_uint32(v, name, &value, errp);\n+}\n+\n+/*\n+ * The 64bit PCI hole start is set by the Guest firmware\n+ * as the address of the first 64bit PCI MEM resource.\n+ * If no PCI device has resources on the 64bit area,\n+ * the 64bit PCI hole will start after \"over 4G RAM\" and the\n+ * reserved space for memory hotplug if any.\n+ */\n+static void i440fx_pcihost_get_pci_hole64_start(Object *obj, Visitor *v,\n+ const char *name,\n+ void *opaque, Error **errp)\n+{\n+ PCIHostState *h = PCI_HOST_BRIDGE(obj);\n+ I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);\n+ Range w64;\n+ uint64_t value;\n+\n+ pci_bus_get_w64_range(h->bus, &w64);\n+ value = range_is_empty(&w64) ? 0 : range_lob(&w64);\n+ if (!value && s->pci_hole64_fix) {\n+ value = pc_pci_hole64_start();\n+ }\n+ visit_type_uint64(v, name, &value, errp);\n+}\n+\n+/*\n+ * The 64bit PCI hole end is set by the Guest firmware\n+ * as the address of the last 64bit PCI MEM resource.\n+ * Then it is expanded to the PCI_HOST_PROP_PCI_HOLE64_SIZE\n+ * that can be configured by the user.\n+ */\n+static void i440fx_pcihost_get_pci_hole64_end(Object *obj, Visitor *v,\n+ const char *name, void *opaque,\n+ Error **errp)\n+{\n+ PCIHostState *h = PCI_HOST_BRIDGE(obj);\n+ I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);\n+ uint64_t hole64_start = pc_pci_hole64_start();\n+ Range w64;\n+ uint64_t value, hole64_end;\n+\n+ pci_bus_get_w64_range(h->bus, &w64);\n+ value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1;\n+ hole64_end = ROUND_UP(hole64_start + s->pci_hole64_size, 1ULL << 30);\n+ if (s->pci_hole64_fix && value < hole64_end) {\n+ value = hole64_end;\n+ }\n+ visit_type_uint64(v, name, &value, errp);\n+}\n+\n+static void i440fx_pcihost_initfn(Object *obj)\n+{\n+ PCIHostState *s = PCI_HOST_BRIDGE(obj);\n+\n+ memory_region_init_io(&s->conf_mem, obj, &pci_host_conf_le_ops, s,\n+ \"pci-conf-idx\", 4);\n+ memory_region_init_io(&s->data_mem, obj, &pci_host_data_le_ops, s,\n+ \"pci-conf-data\", 4);\n+\n+ object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, \"uint32\",\n+ i440fx_pcihost_get_pci_hole_start,\n+ NULL, NULL, NULL, NULL);\n+\n+ object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, \"uint32\",\n+ i440fx_pcihost_get_pci_hole_end,\n+ NULL, NULL, NULL, NULL);\n+\n+ object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, \"uint64\",\n+ i440fx_pcihost_get_pci_hole64_start,\n+ NULL, NULL, NULL, NULL);\n+\n+ object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, \"uint64\",\n+ i440fx_pcihost_get_pci_hole64_end,\n+ NULL, NULL, NULL, NULL);\n+}\n+\n+static void i440fx_pcihost_realize(DeviceState *dev, Error **errp)\n+{\n+ PCIHostState *s = PCI_HOST_BRIDGE(dev);\n+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);\n+\n+ sysbus_add_io(sbd, 0xcf8, &s->conf_mem);\n+ sysbus_init_ioports(sbd, 0xcf8, 4);\n+\n+ sysbus_add_io(sbd, 0xcfc, &s->data_mem);\n+ sysbus_init_ioports(sbd, 0xcfc, 4);\n+}\n+\n+static void i440fx_realize(PCIDevice *dev, Error **errp)\n+{\n+ dev->config[I440FX_SMRAM] = 0x02;\n+\n+ if (object_property_get_bool(qdev_get_machine(), \"iommu\", NULL)) {\n+ warn_report(\"i440fx doesn't support emulated iommu\");\n+ }\n+}\n+\n+PCIBus *i440fx_init(const char *host_type, const char *pci_type,\n+ PCII440FXState **pi440fx_state,\n+ int *piix3_devfn,\n+ ISABus **isa_bus, qemu_irq *pic,\n+ MemoryRegion *address_space_mem,\n+ MemoryRegion *address_space_io,\n+ ram_addr_t ram_size,\n+ ram_addr_t below_4g_mem_size,\n+ ram_addr_t above_4g_mem_size,\n+ MemoryRegion *pci_address_space,\n+ MemoryRegion *ram_memory)\n+{\n+ DeviceState *dev;\n+ PCIBus *b;\n+ PCIDevice *d;\n+ PCIHostState *s;\n+ PCII440FXState *f;\n+ unsigned i;\n+ I440FXState *i440fx;\n+\n+ dev = qdev_create(NULL, host_type);\n+ s = PCI_HOST_BRIDGE(dev);\n+ b = pci_bus_new(dev, NULL, pci_address_space,\n+ address_space_io, 0, TYPE_PCI_BUS);\n+ s->bus = b;\n+ object_property_add_child(qdev_get_machine(), \"i440fx\", OBJECT(dev), NULL);\n+ qdev_init_nofail(dev);\n+\n+ d = pci_create_simple(b, 0, pci_type);\n+ *pi440fx_state = I440FX_PCI_DEVICE(d);\n+ f = *pi440fx_state;\n+ f->system_memory = address_space_mem;\n+ f->pci_address_space = pci_address_space;\n+ f->ram_memory = ram_memory;\n+\n+ i440fx = I440FX_PCI_HOST_BRIDGE(dev);\n+ range_set_bounds(&i440fx->pci_hole, below_4g_mem_size,\n+ IO_APIC_DEFAULT_ADDRESS - 1);\n+\n+ /* setup pci memory mapping */\n+ pc_pci_as_mapping_init(OBJECT(f), f->system_memory,\n+ f->pci_address_space);\n+\n+ /* if *disabled* show SMRAM to all CPUs */\n+ memory_region_init_alias(&f->smram_region, OBJECT(d), \"smram-region\",\n+ f->pci_address_space, 0xa0000, 0x20000);\n+ memory_region_add_subregion_overlap(f->system_memory, 0xa0000,\n+ &f->smram_region, 1);\n+ memory_region_set_enabled(&f->smram_region, true);\n+\n+ /* smram, as seen by SMM CPUs */\n+ memory_region_init(&f->smram, OBJECT(d), \"smram\", 1ull << 32);\n+ memory_region_set_enabled(&f->smram, true);\n+ memory_region_init_alias(&f->low_smram, OBJECT(d), \"smram-low\",\n+ f->ram_memory, 0xa0000, 0x20000);\n+ memory_region_set_enabled(&f->low_smram, true);\n+ memory_region_add_subregion(&f->smram, 0xa0000, &f->low_smram);\n+ object_property_add_const_link(qdev_get_machine(), \"smram\",\n+ OBJECT(&f->smram), &error_abort);\n+\n+ init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,\n+ &f->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);\n+ for (i = 0; i < 12; ++i) {\n+ init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,\n+ &f->pam_regions[i + 1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,\n+ PAM_EXPAN_SIZE);\n+ }\n+\n+ piix3_init(b, isa_bus, pic, piix3_devfn);\n+\n+ ram_size = ram_size / 8 / 1024 / 1024;\n+ if (ram_size > 255) {\n+ ram_size = 255;\n+ }\n+ d->config[I440FX_COREBOOT_RAM_SIZE] = ram_size;\n+\n+ i440fx_update_memory_mappings(f);\n+\n+ return b;\n+}\n+\n+PCIBus *find_i440fx(void)\n+{\n+ PCIHostState *s = OBJECT_CHECK(PCIHostState,\n+ object_resolve_path(\"/machine/i440fx\", NULL),\n+ TYPE_PCI_HOST_BRIDGE);\n+ return s ? s->bus : NULL;\n+}\n+\n+static void i440fx_class_init(ObjectClass *klass, void *data)\n+{\n+ DeviceClass *dc = DEVICE_CLASS(klass);\n+ PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);\n+\n+ k->realize = i440fx_realize;\n+ k->config_write = i440fx_write_config;\n+ k->vendor_id = PCI_VENDOR_ID_INTEL;\n+ k->device_id = PCI_DEVICE_ID_INTEL_82441;\n+ k->revision = 0x02;\n+ k->class_id = PCI_CLASS_BRIDGE_HOST;\n+ dc->desc = \"Host bridge\";\n+ dc->vmsd = &vmstate_i440fx;\n+ /*\n+ * PCI-facing part of the host bridge, not usable without the\n+ * host-facing part, which can't be device_add'ed, yet.\n+ */\n+ dc->user_creatable = false;\n+ dc->hotpluggable = false;\n+}\n+\n+static const TypeInfo i440fx_info = {\n+ .name = TYPE_I440FX_PCI_DEVICE,\n+ .parent = TYPE_PCI_DEVICE,\n+ .instance_size = sizeof(PCII440FXState),\n+ .class_init = i440fx_class_init,\n+ .interfaces = (InterfaceInfo[]) {\n+ { INTERFACE_CONVENTIONAL_PCI_DEVICE },\n+ { },\n+ },\n+};\n+\n+/* IGD Passthrough Host Bridge. */\n+typedef struct {\n+ uint8_t offset;\n+ uint8_t len;\n+} IGDHostInfo;\n+\n+/* Here we just expose minimal host bridge offset subset. */\n+static const IGDHostInfo igd_host_bridge_infos[] = {\n+ {0x08, 2}, /* revision id */\n+ {0x2c, 2}, /* sybsystem vendor id */\n+ {0x2e, 2}, /* sybsystem id */\n+ {0x50, 2}, /* SNB: processor graphics control register */\n+ {0x52, 2}, /* processor graphics control register */\n+ {0xa4, 4}, /* SNB: graphics base of stolen memory */\n+ {0xa8, 4}, /* SNB: base of GTT stolen memory */\n+};\n+\n+static int host_pci_config_read(int pos, int len, uint32_t *val)\n+{\n+ char path[PATH_MAX];\n+ int config_fd;\n+ ssize_t size = sizeof(path);\n+ /* Access real host bridge. */\n+ int rc = snprintf(path, size, \"/sys/bus/pci/devices/%04x:%02x:%02x.%d/%s\",\n+ 0, 0, 0, 0, \"config\");\n+ int ret = 0;\n+\n+ if (rc >= size || rc < 0) {\n+ return -ENODEV;\n+ }\n+\n+ config_fd = open(path, O_RDWR);\n+ if (config_fd < 0) {\n+ return -ENODEV;\n+ }\n+\n+ if (lseek(config_fd, pos, SEEK_SET) != pos) {\n+ ret = -errno;\n+ goto out;\n+ }\n+\n+ do {\n+ rc = read(config_fd, (uint8_t *)val, len);\n+ } while (rc < 0 && (errno == EINTR || errno == EAGAIN));\n+ if (rc != len) {\n+ ret = -errno;\n+ }\n+\n+out:\n+ close(config_fd);\n+ return ret;\n+}\n+\n+static int igd_pt_i440fx_initfn(struct PCIDevice *pci_dev)\n+{\n+ uint32_t val = 0;\n+ int rc, i, num;\n+ int pos, len;\n+\n+ num = ARRAY_SIZE(igd_host_bridge_infos);\n+ for (i = 0; i < num; i++) {\n+ pos = igd_host_bridge_infos[i].offset;\n+ len = igd_host_bridge_infos[i].len;\n+ rc = host_pci_config_read(pos, len, &val);\n+ if (rc) {\n+ return -ENODEV;\n+ }\n+ pci_default_write_config(pci_dev, pos, val, len);\n+ }\n+\n+ return 0;\n+}\n+\n+static void igd_passthrough_i440fx_class_init(ObjectClass *klass, void *data)\n+{\n+ DeviceClass *dc = DEVICE_CLASS(klass);\n+ PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);\n+\n+ k->init = igd_pt_i440fx_initfn;\n+ dc->desc = \"IGD Passthrough Host bridge\";\n+}\n+\n+static const TypeInfo igd_passthrough_i440fx_info = {\n+ .name = TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE,\n+ .parent = TYPE_I440FX_PCI_DEVICE,\n+ .instance_size = sizeof(PCII440FXState),\n+ .class_init = igd_passthrough_i440fx_class_init,\n+};\n+\n+static const char *i440fx_pcihost_root_bus_path(PCIHostState *host_bridge,\n+ PCIBus *rootbus)\n+{\n+ I440FXState *s = I440FX_PCI_HOST_BRIDGE(host_bridge);\n+\n+ /* For backwards compat with old device paths */\n+ if (s->short_root_bus) {\n+ return \"0000\";\n+ }\n+ return \"0000:00\";\n+}\n+\n+static Property i440fx_props[] = {\n+ DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, I440FXState,\n+ pci_hole64_size, I440FX_PCI_HOST_HOLE64_SIZE_DEFAULT),\n+ DEFINE_PROP_UINT32(\"short_root_bus\", I440FXState, short_root_bus, 0),\n+ DEFINE_PROP_BOOL(\"x-pci-hole64-fix\", I440FXState, pci_hole64_fix, true),\n+ DEFINE_PROP_END_OF_LIST(),\n+};\n+\n+static void i440fx_pcihost_class_init(ObjectClass *klass, void *data)\n+{\n+ DeviceClass *dc = DEVICE_CLASS(klass);\n+ PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);\n+\n+ hc->root_bus_path = i440fx_pcihost_root_bus_path;\n+ dc->realize = i440fx_pcihost_realize;\n+ dc->fw_name = \"pci\";\n+ dc->props = i440fx_props;\n+ /* Reason: needs to be wired up by pc_init1 */\n+ dc->user_creatable = false;\n+}\n+\n+static const TypeInfo i440fx_pcihost_info = {\n+ .name = TYPE_I440FX_PCI_HOST_BRIDGE,\n+ .parent = TYPE_PCI_HOST_BRIDGE,\n+ .instance_size = sizeof(I440FXState),\n+ .instance_init = i440fx_pcihost_initfn,\n+ .class_init = i440fx_pcihost_class_init,\n+};\n+\n+static void i440fx_register_types(void)\n+{\n+ type_register_static(&i440fx_info);\n+ type_register_static(&igd_passthrough_i440fx_info);\n+ type_register_static(&i440fx_pcihost_info);\n+}\n+\n+type_init(i440fx_register_types)\ndiff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c\nindex 6f963b5a07..df08d94a59 100644\n--- a/hw/pci-host/piix.c\n+++ b/hw/pci-host/piix.c\n@@ -1,5 +1,5 @@\n /*\n- * QEMU i440FX/PIIX3 PCI Bridge Emulation\n+ * QEMU PIIX South Bridge Emulation\n *\n * Copyright (c) 2006 Fabrice Bellard\n *\n@@ -23,38 +23,11 @@\n */\n \n #include \"qemu/osdep.h\"\n+#include \"qemu/range.h\"\n+#include \"sysemu/sysemu.h\"\n #include \"hw/hw.h\"\n-#include \"hw/i386/pc.h\"\n-#include \"hw/pci/pci.h\"\n-#include \"hw/pci/pci_host.h\"\n-#include \"hw/pci-host/i440fx.h\"\n #include \"hw/southbridge/i82371_piix.h\"\n-#include \"hw/isa/isa.h\"\n-#include \"hw/sysbus.h\"\n-#include \"qapi/error.h\"\n-#include \"qemu/range.h\"\n #include \"hw/xen/xen.h\"\n-#include \"hw/pci-host/pam.h\"\n-#include \"sysemu/sysemu.h\"\n-#include \"hw/i386/ioapic.h\"\n-#include \"qapi/visitor.h\"\n-#include \"qemu/error-report.h\"\n-\n-/*\n- * I440FX chipset data sheet.\n- * http://download.intel.com/design/chipsets/datashts/29054901.pdf\n- */\n-\n-#define I440FX_PCI_HOST_BRIDGE(obj) \\\n- OBJECT_CHECK(I440FXState, (obj), TYPE_I440FX_PCI_HOST_BRIDGE)\n-\n-typedef struct I440FXState {\n- PCIHostState parent_obj;\n- Range pci_hole;\n- uint64_t pci_hole64_size;\n- bool pci_hole64_fix;\n- uint32_t short_root_bus;\n-} I440FXState;\n \n #define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */\n #define XEN_PIIX_NUM_PIRQS 128ULL\n@@ -93,35 +66,6 @@ typedef struct PIIX3State {\n #define PIIX3_PCI_DEVICE(obj) \\\n OBJECT_CHECK(PIIX3State, (obj), TYPE_PIIX3_PCI_DEVICE)\n \n-#define I440FX_PCI_DEVICE(obj) \\\n- OBJECT_CHECK(PCII440FXState, (obj), TYPE_I440FX_PCI_DEVICE)\n-\n-struct PCII440FXState {\n- /*< private >*/\n- PCIDevice parent_obj;\n- /*< public >*/\n-\n- MemoryRegion *system_memory;\n- MemoryRegion *pci_address_space;\n- MemoryRegion *ram_memory;\n- PAMMemoryRegion pam_regions[13];\n- MemoryRegion smram_region;\n- MemoryRegion smram, low_smram;\n-};\n-\n-\n-#define I440FX_PAM 0x59\n-#define I440FX_PAM_SIZE 7\n-#define I440FX_SMRAM 0x72\n-\n-/* Keep it 2G to comply with older win32 guests */\n-#define I440FX_PCI_HOST_HOLE64_SIZE_DEFAULT (1ULL << 31)\n-\n-/* Older coreboot versions (4.0 and older) read a config register that doesn't\n- * exist in real hardware, to get the RAM size from QEMU.\n- */\n-#define I440FX_COREBOOT_RAM_SIZE 0x57\n-\n /* return the global irq number corresponding to a given device irq\n pin. We could also use the bus number to have a more precise\n mapping. */\n@@ -132,297 +76,6 @@ static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)\n return (pci_intx + slot_addend) & 3;\n }\n \n-static void i440fx_update_memory_mappings(PCII440FXState *d)\n-{\n- int i;\n- PCIDevice *pd = PCI_DEVICE(d);\n-\n- memory_region_transaction_begin();\n- for (i = 0; i < 13; i++) {\n- pam_update(&d->pam_regions[i], i,\n- pd->config[I440FX_PAM + (DIV_ROUND_UP(i, 2))]);\n- }\n- memory_region_set_enabled(&d->smram_region,\n- !(pd->config[I440FX_SMRAM] & SMRAM_D_OPEN));\n- memory_region_set_enabled(&d->smram,\n- pd->config[I440FX_SMRAM] & SMRAM_G_SMRAME);\n- memory_region_transaction_commit();\n-}\n-\n-\n-static void i440fx_write_config(PCIDevice *dev,\n- uint32_t address, uint32_t val, int len)\n-{\n- PCII440FXState *d = I440FX_PCI_DEVICE(dev);\n-\n- /* XXX: implement SMRAM.D_LOCK */\n- pci_default_write_config(dev, address, val, len);\n- if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||\n- range_covers_byte(address, len, I440FX_SMRAM)) {\n- i440fx_update_memory_mappings(d);\n- }\n-}\n-\n-static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)\n-{\n- PCII440FXState *d = opaque;\n- PCIDevice *pd = PCI_DEVICE(d);\n- int ret, i;\n- uint8_t smm_enabled;\n-\n- ret = pci_device_load(pd, f);\n- if (ret < 0)\n- return ret;\n- i440fx_update_memory_mappings(d);\n- qemu_get_8s(f, &smm_enabled);\n-\n- if (version_id == 2) {\n- for (i = 0; i < PIIX_NUM_PIRQS; i++) {\n- qemu_get_be32(f); /* dummy load for compatibility */\n- }\n- }\n-\n- return 0;\n-}\n-\n-static int i440fx_post_load(void *opaque, int version_id)\n-{\n- PCII440FXState *d = opaque;\n-\n- i440fx_update_memory_mappings(d);\n- return 0;\n-}\n-\n-static const VMStateDescription vmstate_i440fx = {\n- .name = \"I440FX\",\n- .version_id = 3,\n- .minimum_version_id = 3,\n- .minimum_version_id_old = 1,\n- .load_state_old = i440fx_load_old,\n- .post_load = i440fx_post_load,\n- .fields = (VMStateField[]) {\n- VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState),\n- /* Used to be smm_enabled, which was basically always zero because\n- * SeaBIOS hardly uses SMM. SMRAM is now handled by CPU code.\n- */\n- VMSTATE_UNUSED(1),\n- VMSTATE_END_OF_LIST()\n- }\n-};\n-\n-static void i440fx_pcihost_get_pci_hole_start(Object *obj, Visitor *v,\n- const char *name, void *opaque,\n- Error **errp)\n-{\n- I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);\n- uint64_t val64;\n- uint32_t value;\n-\n- val64 = range_is_empty(&s->pci_hole) ? 0 : range_lob(&s->pci_hole);\n- value = val64;\n- assert(value == val64);\n- visit_type_uint32(v, name, &value, errp);\n-}\n-\n-static void i440fx_pcihost_get_pci_hole_end(Object *obj, Visitor *v,\n- const char *name, void *opaque,\n- Error **errp)\n-{\n- I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);\n- uint64_t val64;\n- uint32_t value;\n-\n- val64 = range_is_empty(&s->pci_hole) ? 0 : range_upb(&s->pci_hole) + 1;\n- value = val64;\n- assert(value == val64);\n- visit_type_uint32(v, name, &value, errp);\n-}\n-\n-/*\n- * The 64bit PCI hole start is set by the Guest firmware\n- * as the address of the first 64bit PCI MEM resource.\n- * If no PCI device has resources on the 64bit area,\n- * the 64bit PCI hole will start after \"over 4G RAM\" and the\n- * reserved space for memory hotplug if any.\n- */\n-static void i440fx_pcihost_get_pci_hole64_start(Object *obj, Visitor *v,\n- const char *name,\n- void *opaque, Error **errp)\n-{\n- PCIHostState *h = PCI_HOST_BRIDGE(obj);\n- I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);\n- Range w64;\n- uint64_t value;\n-\n- pci_bus_get_w64_range(h->bus, &w64);\n- value = range_is_empty(&w64) ? 0 : range_lob(&w64);\n- if (!value && s->pci_hole64_fix) {\n- value = pc_pci_hole64_start();\n- }\n- visit_type_uint64(v, name, &value, errp);\n-}\n-\n-/*\n- * The 64bit PCI hole end is set by the Guest firmware\n- * as the address of the last 64bit PCI MEM resource.\n- * Then it is expanded to the PCI_HOST_PROP_PCI_HOLE64_SIZE\n- * that can be configured by the user.\n- */\n-static void i440fx_pcihost_get_pci_hole64_end(Object *obj, Visitor *v,\n- const char *name, void *opaque,\n- Error **errp)\n-{\n- PCIHostState *h = PCI_HOST_BRIDGE(obj);\n- I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);\n- uint64_t hole64_start = pc_pci_hole64_start();\n- Range w64;\n- uint64_t value, hole64_end;\n-\n- pci_bus_get_w64_range(h->bus, &w64);\n- value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1;\n- hole64_end = ROUND_UP(hole64_start + s->pci_hole64_size, 1ULL << 30);\n- if (s->pci_hole64_fix && value < hole64_end) {\n- value = hole64_end;\n- }\n- visit_type_uint64(v, name, &value, errp);\n-}\n-\n-static void i440fx_pcihost_initfn(Object *obj)\n-{\n- PCIHostState *s = PCI_HOST_BRIDGE(obj);\n-\n- memory_region_init_io(&s->conf_mem, obj, &pci_host_conf_le_ops, s,\n- \"pci-conf-idx\", 4);\n- memory_region_init_io(&s->data_mem, obj, &pci_host_data_le_ops, s,\n- \"pci-conf-data\", 4);\n-\n- object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, \"uint32\",\n- i440fx_pcihost_get_pci_hole_start,\n- NULL, NULL, NULL, NULL);\n-\n- object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, \"uint32\",\n- i440fx_pcihost_get_pci_hole_end,\n- NULL, NULL, NULL, NULL);\n-\n- object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, \"uint64\",\n- i440fx_pcihost_get_pci_hole64_start,\n- NULL, NULL, NULL, NULL);\n-\n- object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, \"uint64\",\n- i440fx_pcihost_get_pci_hole64_end,\n- NULL, NULL, NULL, NULL);\n-}\n-\n-static void i440fx_pcihost_realize(DeviceState *dev, Error **errp)\n-{\n- PCIHostState *s = PCI_HOST_BRIDGE(dev);\n- SysBusDevice *sbd = SYS_BUS_DEVICE(dev);\n-\n- sysbus_add_io(sbd, 0xcf8, &s->conf_mem);\n- sysbus_init_ioports(sbd, 0xcf8, 4);\n-\n- sysbus_add_io(sbd, 0xcfc, &s->data_mem);\n- sysbus_init_ioports(sbd, 0xcfc, 4);\n-}\n-\n-static void i440fx_realize(PCIDevice *dev, Error **errp)\n-{\n- dev->config[I440FX_SMRAM] = 0x02;\n-\n- if (object_property_get_bool(qdev_get_machine(), \"iommu\", NULL)) {\n- warn_report(\"i440fx doesn't support emulated iommu\");\n- }\n-}\n-\n-PCIBus *i440fx_init(const char *host_type, const char *pci_type,\n- PCII440FXState **pi440fx_state,\n- int *piix3_devfn,\n- ISABus **isa_bus, qemu_irq *pic,\n- MemoryRegion *address_space_mem,\n- MemoryRegion *address_space_io,\n- ram_addr_t ram_size,\n- ram_addr_t below_4g_mem_size,\n- ram_addr_t above_4g_mem_size,\n- MemoryRegion *pci_address_space,\n- MemoryRegion *ram_memory)\n-{\n- DeviceState *dev;\n- PCIBus *b;\n- PCIDevice *d;\n- PCIHostState *s;\n- PCII440FXState *f;\n- unsigned i;\n- I440FXState *i440fx;\n-\n- dev = qdev_create(NULL, host_type);\n- s = PCI_HOST_BRIDGE(dev);\n- b = pci_bus_new(dev, NULL, pci_address_space,\n- address_space_io, 0, TYPE_PCI_BUS);\n- s->bus = b;\n- object_property_add_child(qdev_get_machine(), \"i440fx\", OBJECT(dev), NULL);\n- qdev_init_nofail(dev);\n-\n- d = pci_create_simple(b, 0, pci_type);\n- *pi440fx_state = I440FX_PCI_DEVICE(d);\n- f = *pi440fx_state;\n- f->system_memory = address_space_mem;\n- f->pci_address_space = pci_address_space;\n- f->ram_memory = ram_memory;\n-\n- i440fx = I440FX_PCI_HOST_BRIDGE(dev);\n- range_set_bounds(&i440fx->pci_hole, below_4g_mem_size,\n- IO_APIC_DEFAULT_ADDRESS - 1);\n-\n- /* setup pci memory mapping */\n- pc_pci_as_mapping_init(OBJECT(f), f->system_memory,\n- f->pci_address_space);\n-\n- /* if *disabled* show SMRAM to all CPUs */\n- memory_region_init_alias(&f->smram_region, OBJECT(d), \"smram-region\",\n- f->pci_address_space, 0xa0000, 0x20000);\n- memory_region_add_subregion_overlap(f->system_memory, 0xa0000,\n- &f->smram_region, 1);\n- memory_region_set_enabled(&f->smram_region, true);\n-\n- /* smram, as seen by SMM CPUs */\n- memory_region_init(&f->smram, OBJECT(d), \"smram\", 1ull << 32);\n- memory_region_set_enabled(&f->smram, true);\n- memory_region_init_alias(&f->low_smram, OBJECT(d), \"smram-low\",\n- f->ram_memory, 0xa0000, 0x20000);\n- memory_region_set_enabled(&f->low_smram, true);\n- memory_region_add_subregion(&f->smram, 0xa0000, &f->low_smram);\n- object_property_add_const_link(qdev_get_machine(), \"smram\",\n- OBJECT(&f->smram), &error_abort);\n-\n- init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,\n- &f->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);\n- for (i = 0; i < 12; ++i) {\n- init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,\n- &f->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,\n- PAM_EXPAN_SIZE);\n- }\n-\n- piix3_init(b, isa_bus, pic, piix3_devfn);\n-\n- ram_size = ram_size / 8 / 1024 / 1024;\n- if (ram_size > 255) {\n- ram_size = 255;\n- }\n- d->config[I440FX_COREBOOT_RAM_SIZE] = ram_size;\n-\n- i440fx_update_memory_mappings(f);\n-\n- return b;\n-}\n-\n-PCIBus *find_i440fx(void)\n-{\n- PCIHostState *s = OBJECT_CHECK(PCIHostState,\n- object_resolve_path(\"/machine/i440fx\", NULL),\n- TYPE_PCI_HOST_BRIDGE);\n- return s ? s->bus : NULL;\n-}\n-\n /* PIIX3 PCI to ISA bridge */\n static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)\n {\n@@ -761,176 +414,11 @@ static const TypeInfo piix3_xen_info = {\n .class_init = piix3_xen_class_init,\n };\n \n-static void i440fx_class_init(ObjectClass *klass, void *data)\n-{\n- DeviceClass *dc = DEVICE_CLASS(klass);\n- PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);\n-\n- k->realize = i440fx_realize;\n- k->config_write = i440fx_write_config;\n- k->vendor_id = PCI_VENDOR_ID_INTEL;\n- k->device_id = PCI_DEVICE_ID_INTEL_82441;\n- k->revision = 0x02;\n- k->class_id = PCI_CLASS_BRIDGE_HOST;\n- dc->desc = \"Host bridge\";\n- dc->vmsd = &vmstate_i440fx;\n- /*\n- * PCI-facing part of the host bridge, not usable without the\n- * host-facing part, which can't be device_add'ed, yet.\n- */\n- dc->user_creatable = false;\n- dc->hotpluggable = false;\n-}\n-\n-static const TypeInfo i440fx_info = {\n- .name = TYPE_I440FX_PCI_DEVICE,\n- .parent = TYPE_PCI_DEVICE,\n- .instance_size = sizeof(PCII440FXState),\n- .class_init = i440fx_class_init,\n- .interfaces = (InterfaceInfo[]) {\n- { INTERFACE_CONVENTIONAL_PCI_DEVICE },\n- { },\n- },\n-};\n-\n-/* IGD Passthrough Host Bridge. */\n-typedef struct {\n- uint8_t offset;\n- uint8_t len;\n-} IGDHostInfo;\n-\n-/* Here we just expose minimal host bridge offset subset. */\n-static const IGDHostInfo igd_host_bridge_infos[] = {\n- {0x08, 2}, /* revision id */\n- {0x2c, 2}, /* sybsystem vendor id */\n- {0x2e, 2}, /* sybsystem id */\n- {0x50, 2}, /* SNB: processor graphics control register */\n- {0x52, 2}, /* processor graphics control register */\n- {0xa4, 4}, /* SNB: graphics base of stolen memory */\n- {0xa8, 4}, /* SNB: base of GTT stolen memory */\n-};\n-\n-static int host_pci_config_read(int pos, int len, uint32_t *val)\n-{\n- char path[PATH_MAX];\n- int config_fd;\n- ssize_t size = sizeof(path);\n- /* Access real host bridge. */\n- int rc = snprintf(path, size, \"/sys/bus/pci/devices/%04x:%02x:%02x.%d/%s\",\n- 0, 0, 0, 0, \"config\");\n- int ret = 0;\n-\n- if (rc >= size || rc < 0) {\n- return -ENODEV;\n- }\n-\n- config_fd = open(path, O_RDWR);\n- if (config_fd < 0) {\n- return -ENODEV;\n- }\n-\n- if (lseek(config_fd, pos, SEEK_SET) != pos) {\n- ret = -errno;\n- goto out;\n- }\n-\n- do {\n- rc = read(config_fd, (uint8_t *)val, len);\n- } while (rc < 0 && (errno == EINTR || errno == EAGAIN));\n- if (rc != len) {\n- ret = -errno;\n- }\n-\n-out:\n- close(config_fd);\n- return ret;\n-}\n-\n-static int igd_pt_i440fx_initfn(struct PCIDevice *pci_dev)\n-{\n- uint32_t val = 0;\n- int rc, i, num;\n- int pos, len;\n-\n- num = ARRAY_SIZE(igd_host_bridge_infos);\n- for (i = 0; i < num; i++) {\n- pos = igd_host_bridge_infos[i].offset;\n- len = igd_host_bridge_infos[i].len;\n- rc = host_pci_config_read(pos, len, &val);\n- if (rc) {\n- return -ENODEV;\n- }\n- pci_default_write_config(pci_dev, pos, val, len);\n- }\n-\n- return 0;\n-}\n-\n-static void igd_passthrough_i440fx_class_init(ObjectClass *klass, void *data)\n-{\n- DeviceClass *dc = DEVICE_CLASS(klass);\n- PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);\n-\n- k->init = igd_pt_i440fx_initfn;\n- dc->desc = \"IGD Passthrough Host bridge\";\n-}\n-\n-static const TypeInfo igd_passthrough_i440fx_info = {\n- .name = TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE,\n- .parent = TYPE_I440FX_PCI_DEVICE,\n- .instance_size = sizeof(PCII440FXState),\n- .class_init = igd_passthrough_i440fx_class_init,\n-};\n-\n-static const char *i440fx_pcihost_root_bus_path(PCIHostState *host_bridge,\n- PCIBus *rootbus)\n-{\n- I440FXState *s = I440FX_PCI_HOST_BRIDGE(host_bridge);\n-\n- /* For backwards compat with old device paths */\n- if (s->short_root_bus) {\n- return \"0000\";\n- }\n- return \"0000:00\";\n-}\n-\n-static Property i440fx_props[] = {\n- DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, I440FXState,\n- pci_hole64_size, I440FX_PCI_HOST_HOLE64_SIZE_DEFAULT),\n- DEFINE_PROP_UINT32(\"short_root_bus\", I440FXState, short_root_bus, 0),\n- DEFINE_PROP_BOOL(\"x-pci-hole64-fix\", I440FXState, pci_hole64_fix, true),\n- DEFINE_PROP_END_OF_LIST(),\n-};\n-\n-static void i440fx_pcihost_class_init(ObjectClass *klass, void *data)\n-{\n- DeviceClass *dc = DEVICE_CLASS(klass);\n- PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);\n-\n- hc->root_bus_path = i440fx_pcihost_root_bus_path;\n- dc->realize = i440fx_pcihost_realize;\n- dc->fw_name = \"pci\";\n- dc->props = i440fx_props;\n- /* Reason: needs to be wired up by pc_init1 */\n- dc->user_creatable = false;\n-}\n-\n-static const TypeInfo i440fx_pcihost_info = {\n- .name = TYPE_I440FX_PCI_HOST_BRIDGE,\n- .parent = TYPE_PCI_HOST_BRIDGE,\n- .instance_size = sizeof(I440FXState),\n- .instance_init = i440fx_pcihost_initfn,\n- .class_init = i440fx_pcihost_class_init,\n-};\n-\n-static void i440fx_register_types(void)\n+static void piix_register_types(void)\n {\n- type_register_static(&i440fx_info);\n- type_register_static(&igd_passthrough_i440fx_info);\n type_register_static(&piix3_pci_type_info);\n type_register_static(&piix3_info);\n type_register_static(&piix3_xen_info);\n- type_register_static(&i440fx_pcihost_info);\n }\n \n-type_init(i440fx_register_types)\n+type_init(piix_register_types)\ndiff --git a/MAINTAINERS b/MAINTAINERS\nindex c3efcd2316..a4dc72a47b 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -849,6 +849,7 @@ S: Supported\n F: include/hw/i386/\n F: hw/i386/\n F: hw/pci-host/piix.c\n+F: hw/pci-host/i440fx.c\n F: hw/pci-host/q35.c\n F: hw/pci-host/pam.c\n F: include/hw/pci-host/q35.h\ndiff --git a/hw/pci-host/Makefile.objs b/hw/pci-host/Makefile.objs\nindex 9c7909cf44..acf61023b5 100644\n--- a/hw/pci-host/Makefile.objs\n+++ b/hw/pci-host/Makefile.objs\n@@ -14,6 +14,7 @@ common-obj-$(CONFIG_VERSATILE_PCI) += versatile.o\n common-obj-$(CONFIG_PCI_APB) += apb.o\n common-obj-$(CONFIG_FULONG) += bonito.o\n common-obj-$(CONFIG_PCI_PIIX) += piix.o\n+common-obj-$(CONFIG_PCI_I440FX) += i440fx.o\n common-obj-$(CONFIG_PCI_Q35) += q35.o\n common-obj-$(CONFIG_PCI_GENERIC) += gpex.o\n common-obj-$(CONFIG_PCI_XILINX) += xilinx-pcie.o\n", "prefixes": [ "24/29" ] }