Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/854011/?format=api
{ "id": 854011, "url": "http://patchwork.ozlabs.org/api/patches/854011/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20171229135108.14645-1-alice.michael@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20171229135108.14645-1-alice.michael@intel.com>", "list_archive_url": null, "date": "2017-12-29T13:51:08", "name": "[next,S85-V1,11/14] i40e/i40evf: Use usec value instead of reg value for ITR defines", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "bdb133df8132c743d7aa32b3de2fd2bc3e6b7102", "submitter": { "id": 71123, "url": "http://patchwork.ozlabs.org/api/people/71123/?format=api", "name": "Michael, Alice", "email": "alice.michael@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20171229135108.14645-1-alice.michael@intel.com/mbox/", "series": [ { "id": 20665, "url": "http://patchwork.ozlabs.org/api/series/20665/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=20665", "date": "2017-12-29T13:48:33", "name": "[next,S85-V1,01/14] i40e: fix typo in function description", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/20665/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/854011/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/854011/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=osuosl.org\n\t(client-ip=140.211.166.138; helo=whitealder.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3z7gSd0BdPz9s7G\n\tfor <incoming@patchwork.ozlabs.org>;\n\tSat, 30 Dec 2017 08:58:09 +1100 (AEDT)", "from localhost (localhost [127.0.0.1])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 98E9087EEB;\n\tFri, 29 Dec 2017 21:58:07 +0000 (UTC)", "from whitealder.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id c5-nsdaV8GxU; Fri, 29 Dec 2017 21:58:05 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id B2BBC87698;\n\tFri, 29 Dec 2017 21:58:05 +0000 (UTC)", "from fraxinus.osuosl.org (smtp4.osuosl.org [140.211.166.137])\n\tby ash.osuosl.org (Postfix) with ESMTP id 1C7491C0180\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tFri, 29 Dec 2017 21:58:05 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id 191D586C6B\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tFri, 29 Dec 2017 21:58:05 +0000 (UTC)", "from fraxinus.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id Lu0xzx26ofyp for <intel-wired-lan@lists.osuosl.org>;\n\tFri, 29 Dec 2017 21:58:04 +0000 (UTC)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n\tby fraxinus.osuosl.org (Postfix) with ESMTPS id 2AC6686C61\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tFri, 29 Dec 2017 21:58:04 +0000 (UTC)", "from orsmga001.jf.intel.com ([10.7.209.18])\n\tby orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t29 Dec 2017 13:58:02 -0800", "from alicemic-2.jf.intel.com ([10.166.16.121])\n\tby orsmga001.jf.intel.com with ESMTP; 29 Dec 2017 13:58:03 -0800" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.45,478,1508828400\"; d=\"scan'208\";a=\"19860475\"", "From": "Alice Michael <alice.michael@intel.com>", "To": "alice.michael@intel.com,\n\tintel-wired-lan@lists.osuosl.org", "Date": "Fri, 29 Dec 2017 08:51:08 -0500", "Message-Id": "<20171229135108.14645-1-alice.michael@intel.com>", "X-Mailer": "git-send-email 2.9.5", "Subject": "[Intel-wired-lan] [next PATCH S85-V1 11/14] i40e/i40evf: Use usec\n\tvalue instead of reg value for ITR defines", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.24", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "From: Alexander Duyck <alexander.h.duyck@intel.com>\n\nInstead of using the register value for the defines when setting up the\nring ITR we can just use the actual values and avoid the use of shifts and\nmacros to translate between the values we have and the values we want.\n\nThis helps to make the code more readable as we can quickly translate from\none value to the other.\n\nSigned-off-by: Alexander Duyck <alexander.h.duyck@intel.com>\n---\n drivers/net/ethernet/intel/i40e/i40e_ethtool.c | 12 +++---\n drivers/net/ethernet/intel/i40e/i40e_txrx.c | 11 +++++-\n drivers/net/ethernet/intel/i40e/i40e_txrx.h | 45 ++++++++++++----------\n drivers/net/ethernet/intel/i40evf/i40e_txrx.c | 11 +++++-\n drivers/net/ethernet/intel/i40evf/i40e_txrx.h | 44 +++++++++++----------\n drivers/net/ethernet/intel/i40evf/i40evf_ethtool.c | 12 +++---\n 6 files changed, 79 insertions(+), 56 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/i40e/i40e_ethtool.c b/drivers/net/ethernet/intel/i40e/i40e_ethtool.c\nindex 1607e5a..0212f6c 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_ethtool.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_ethtool.c\n@@ -2315,8 +2315,8 @@ static void i40e_set_itr_per_queue(struct i40e_vsi *vsi,\n \n \tintrl = i40e_intrl_usec_to_reg(vsi->int_rate_limit);\n \n-\trx_ring->itr_setting = ec->rx_coalesce_usecs;\n-\ttx_ring->itr_setting = ec->tx_coalesce_usecs;\n+\trx_ring->itr_setting = ITR_REG_ALIGN(ec->rx_coalesce_usecs);\n+\ttx_ring->itr_setting = ITR_REG_ALIGN(ec->tx_coalesce_usecs);\n \n \tif (ec->use_adaptive_rx_coalesce)\n \t\trx_ring->itr_setting |= I40E_ITR_DYNAMIC;\n@@ -2396,7 +2396,7 @@ static int __i40e_set_coalesce(struct net_device *netdev,\n \t\treturn -EINVAL;\n \t}\n \n-\tif (ec->rx_coalesce_usecs > (I40E_MAX_ITR << 1)) {\n+\tif (ec->rx_coalesce_usecs > I40E_MAX_ITR) {\n \t\tnetif_info(pf, drv, netdev, \"Invalid value, rx-usecs range is 0-8160\\n\");\n \t\treturn -EINVAL;\n \t}\n@@ -2407,16 +2407,16 @@ static int __i40e_set_coalesce(struct net_device *netdev,\n \t\treturn -EINVAL;\n \t}\n \n-\tif (ec->tx_coalesce_usecs > (I40E_MAX_ITR << 1)) {\n+\tif (ec->tx_coalesce_usecs > I40E_MAX_ITR) {\n \t\tnetif_info(pf, drv, netdev, \"Invalid value, tx-usecs range is 0-8160\\n\");\n \t\treturn -EINVAL;\n \t}\n \n \tif (ec->use_adaptive_rx_coalesce && !cur_rx_itr)\n-\t\tec->rx_coalesce_usecs = I40E_MIN_ITR << 1;\n+\t\tec->rx_coalesce_usecs = I40E_MIN_ITR;\n \n \tif (ec->use_adaptive_tx_coalesce && !cur_tx_itr)\n-\t\tec->tx_coalesce_usecs = I40E_MIN_ITR << 1;\n+\t\tec->tx_coalesce_usecs = I40E_MIN_ITR;\n \n \tintrl_reg = i40e_intrl_usec_to_reg(ec->rx_coalesce_usecs_high);\n \tvsi->int_rate_limit = INTRL_REG_TO_USEC(intrl_reg);\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_txrx.c b/drivers/net/ethernet/intel/i40e/i40e_txrx.c\nindex 628ec59..170256e 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_txrx.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_txrx.c\n@@ -2263,7 +2263,7 @@ static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget)\n \treturn failure ? budget : (int)total_rx_packets;\n }\n \n-static u32 i40e_buildreg_itr(const int type, const u16 itr)\n+static inline u32 i40e_buildreg_itr(const int type, u16 itr)\n {\n \tu32 val;\n \n@@ -2276,10 +2276,17 @@ static u32 i40e_buildreg_itr(const int type, const u16 itr)\n \t * xxINT_DYN_CTLx CSR with INTENA_MSK (bit 31) set to 0 will clear\n \t * an event in the PBA anyway so we need to rely on the automask\n \t * to hold pending events for us until the interrupt is re-enabled\n+\t *\n+\t * The itr value is reported in microseconds, and the register\n+\t * value is recorded in 2 microsecond units. For this reason we\n+\t * only need to shift by the interval shift - 1 instead of the\n+\t * full value.\n \t */\n+\titr &= I40E_ITR_MASK;\n+\n \tval = I40E_PFINT_DYN_CTLN_INTENA_MASK |\n \t (type << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |\n-\t (itr << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT);\n+\t (itr << (I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT - 1));\n \n \treturn val;\n }\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_txrx.h b/drivers/net/ethernet/intel/i40e/i40e_txrx.h\nindex 61eee3d..d226c7c 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_txrx.h\n+++ b/drivers/net/ethernet/intel/i40e/i40e_txrx.h\n@@ -28,32 +28,37 @@\n #define _I40E_TXRX_H_\n \n /* Interrupt Throttling and Rate Limiting Goodies */\n-\n-#define I40E_MAX_ITR 0x0FF0 /* reg uses 2 usec resolution */\n-#define I40E_MIN_ITR 0x0001 /* reg uses 2 usec resolution */\n-#define I40E_ITR_100K 0x0005\n-#define I40E_ITR_50K 0x000A\n-#define I40E_ITR_20K 0x0019\n-#define I40E_ITR_18K 0x001B\n-#define I40E_ITR_8K 0x003E\n-#define I40E_ITR_4K 0x007A\n-#define I40E_MAX_INTRL 0x3B /* reg uses 4 usec resolution */\n-#define I40E_ITR_RX_DEF (ITR_REG_TO_USEC(I40E_ITR_20K) | \\\n-\t\t\t\t I40E_ITR_DYNAMIC)\n-#define I40E_ITR_TX_DEF (ITR_REG_TO_USEC(I40E_ITR_20K) | \\\n-\t\t\t\t I40E_ITR_DYNAMIC)\n-#define I40E_ITR_DYNAMIC 0x8000 /* use top bit as a flag */\n-#define I40E_MIN_INT_RATE 250 /* ~= 1000000 / (I40E_MAX_ITR * 2) */\n-#define I40E_MAX_INT_RATE 500000 /* == 1000000 / (I40E_MIN_ITR * 2) */\n #define I40E_DEFAULT_IRQ_WORK 256\n-#define ITR_TO_REG(setting) ((setting & ~I40E_ITR_DYNAMIC) >> 1)\n-#define ITR_IS_DYNAMIC(setting) (!!(setting & I40E_ITR_DYNAMIC))\n-#define ITR_REG_TO_USEC(itr_reg) (itr_reg << 1)\n+\n+/* The datasheet for the X710 and XL710 indicate that the maximum value for\n+ * the ITR is 8160usec which is then called out as 0xFF0 with a 2usec\n+ * resoltion. 8160 is 0x1FE0 when written out in hex. So instead of storing\n+ * the register value which is divided by 2 lets use the actual values and\n+ * avoid an excessive amount of translation.\n+ */\n+#define I40E_ITR_DYNAMIC\t0x8000\t/* use top bit as a flag */\n+#define I40E_ITR_MASK\t\t0x1FFE\t/* mask for ITR register value */\n+#define I40E_MIN_ITR\t\t 2\t/* reg uses 2 usec resolution */\n+#define I40E_ITR_100K\t\t 10 /* all values below must be even */\n+#define I40E_ITR_50K\t\t 20\n+#define I40E_ITR_20K\t\t 50\n+#define I40E_ITR_18K\t\t 60\n+#define I40E_ITR_8K\t\t 122\n+#define I40E_MAX_ITR\t\t 8160\t/* maximum value as per datasheet */\n+#define ITR_TO_REG(setting) ((setting) & ~I40E_ITR_DYNAMIC)\n+#define ITR_REG_ALIGN(setting) __ALIGN_MASK(setting, ~I40E_ITR_MASK)\n+#define ITR_IS_DYNAMIC(setting) (!!((setting) & I40E_ITR_DYNAMIC))\n+\n+#define I40E_ITR_RX_DEF (I40E_ITR_20K | I40E_ITR_DYNAMIC)\n+#define I40E_ITR_TX_DEF (I40E_ITR_20K | I40E_ITR_DYNAMIC)\n+\n /* 0x40 is the enable bit for interrupt rate limiting, and must be set if\n * the value of the rate limit is non-zero\n */\n #define INTRL_ENA BIT(6)\n+#define I40E_MAX_INTRL 0x3B /* reg uses 4 usec resolution */\n #define INTRL_REG_TO_USEC(intrl) ((intrl & ~INTRL_ENA) << 2)\n+\n /**\n * i40e_intrl_usec_to_reg - convert interrupt rate limit to register\n * @intrl: interrupt rate limit to convert\ndiff --git a/drivers/net/ethernet/intel/i40evf/i40e_txrx.c b/drivers/net/ethernet/intel/i40evf/i40e_txrx.c\nindex 34d898f..c5f8e94 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40e_txrx.c\n+++ b/drivers/net/ethernet/intel/i40evf/i40e_txrx.c\n@@ -1460,7 +1460,7 @@ static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget)\n \treturn failure ? budget : (int)total_rx_packets;\n }\n \n-static u32 i40e_buildreg_itr(const int type, const u16 itr)\n+static inline u32 i40e_buildreg_itr(const int type, u16 itr)\n {\n \tu32 val;\n \n@@ -1473,10 +1473,17 @@ static u32 i40e_buildreg_itr(const int type, const u16 itr)\n \t * xxINT_DYN_CTLx CSR with INTENA_MSK (bit 31) set to 0 will clear\n \t * an event in the PBA anyway so we need to rely on the automask\n \t * to hold pending events for us until the interrupt is re-enabled\n+\t *\n+\t * The itr value is reported in microseconds, and the register\n+\t * value is recorded in 2 microsecond units. For this reason we\n+\t * only need to shift by the interval shift - 1 instead of the\n+\t * full value.\n \t */\n+\titr &= I40E_ITR_MASK;\n+\n \tval = I40E_VFINT_DYN_CTLN1_INTENA_MASK |\n \t (type << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |\n-\t (itr << I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT);\n+\t (itr << (I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT - 1));\n \n \treturn val;\n }\ndiff --git a/drivers/net/ethernet/intel/i40evf/i40e_txrx.h b/drivers/net/ethernet/intel/i40evf/i40e_txrx.h\nindex 81210c3..f1c5ef7 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40e_txrx.h\n+++ b/drivers/net/ethernet/intel/i40evf/i40e_txrx.h\n@@ -28,31 +28,35 @@\n #define _I40E_TXRX_H_\n \n /* Interrupt Throttling and Rate Limiting Goodies */\n-\n-#define I40E_MAX_ITR 0x0FF0 /* reg uses 2 usec resolution */\n-#define I40E_MIN_ITR 0x0001 /* reg uses 2 usec resolution */\n-#define I40E_ITR_100K 0x0005\n-#define I40E_ITR_50K 0x000A\n-#define I40E_ITR_20K 0x0019\n-#define I40E_ITR_18K 0x001B\n-#define I40E_ITR_8K 0x003E\n-#define I40E_ITR_4K 0x007A\n-#define I40E_MAX_INTRL 0x3B /* reg uses 4 usec resolution */\n-#define I40E_ITR_RX_DEF (ITR_REG_TO_USEC(I40E_ITR_20K) | \\\n-\t\t\t\t I40E_ITR_DYNAMIC)\n-#define I40E_ITR_TX_DEF (ITR_REG_TO_USEC(I40E_ITR_20K) | \\\n-\t\t\t\t I40E_ITR_DYNAMIC)\n-#define I40E_ITR_DYNAMIC 0x8000 /* use top bit as a flag */\n-#define I40E_MIN_INT_RATE 250 /* ~= 1000000 / (I40E_MAX_ITR * 2) */\n-#define I40E_MAX_INT_RATE 500000 /* == 1000000 / (I40E_MIN_ITR * 2) */\n #define I40E_DEFAULT_IRQ_WORK 256\n-#define ITR_TO_REG(setting) ((setting & ~I40E_ITR_DYNAMIC) >> 1)\n-#define ITR_IS_DYNAMIC(setting) (!!(setting & I40E_ITR_DYNAMIC))\n-#define ITR_REG_TO_USEC(itr_reg) (itr_reg << 1)\n+\n+/* The datasheet for the X710 and XL710 indicate that the maximum value for\n+ * the ITR is 8160usec which is then called out as 0xFF0 with a 2usec\n+ * resoltion. 8160 is 0x1FE0 when written out in hex. So instead of storing\n+ * the register value which is divided by 2 lets use the actual values and\n+ * avoid an excessive amount of translation.\n+ */\n+#define I40E_ITR_DYNAMIC\t0x8000\t/* use top bit as a flag */\n+#define I40E_ITR_MASK\t\t0x1FFE\t/* mask for ITR register value */\n+#define I40E_MIN_ITR\t\t 2\t/* reg uses 2 usec resolution */\n+#define I40E_ITR_100K\t\t 10 /* all values below must be even */\n+#define I40E_ITR_50K\t\t 20\n+#define I40E_ITR_20K\t\t 50\n+#define I40E_ITR_18K\t\t 60\n+#define I40E_ITR_8K\t\t 122\n+#define I40E_MAX_ITR\t\t 8160\t/* maximum value as per datasheet */\n+#define ITR_TO_REG(setting) ((setting) & ~I40E_ITR_DYNAMIC)\n+#define ITR_REG_ALIGN(setting) __ALIGN_MASK(setting, ~I40E_ITR_MASK)\n+#define ITR_IS_DYNAMIC(setting) (!!((setting) & I40E_ITR_DYNAMIC))\n+\n+#define I40E_ITR_RX_DEF (I40E_ITR_20K | I40E_ITR_DYNAMIC)\n+#define I40E_ITR_TX_DEF (I40E_ITR_20K | I40E_ITR_DYNAMIC)\n+\n /* 0x40 is the enable bit for interrupt rate limiting, and must be set if\n * the value of the rate limit is non-zero\n */\n #define INTRL_ENA BIT(6)\n+#define I40E_MAX_INTRL 0x3B /* reg uses 4 usec resolution */\n #define INTRL_REG_TO_USEC(intrl) ((intrl & ~INTRL_ENA) << 2)\n #define INTRL_USEC_TO_REG(set) ((set) ? ((set) >> 2) | INTRL_ENA : 0)\n #define I40E_INTRL_8K 125 /* 8000 ints/sec */\ndiff --git a/drivers/net/ethernet/intel/i40evf/i40evf_ethtool.c b/drivers/net/ethernet/intel/i40evf/i40evf_ethtool.c\nindex ed5b8ec..f5d3725 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40evf_ethtool.c\n+++ b/drivers/net/ethernet/intel/i40evf/i40evf_ethtool.c\n@@ -517,8 +517,8 @@ static void i40evf_set_itr_per_queue(struct i40evf_adapter *adapter,\n \tstruct i40e_hw *hw = &adapter->hw;\n \tstruct i40e_q_vector *q_vector;\n \n-\trx_ring->itr_setting = ec->rx_coalesce_usecs;\n-\ttx_ring->itr_setting = ec->tx_coalesce_usecs;\n+\trx_ring->itr_setting = ITR_REG_ALIGN(ec->rx_coalesce_usecs);\n+\ttx_ring->itr_setting = ITR_REG_ALIGN(ec->tx_coalesce_usecs);\n \n \trx_ring->itr_setting |= I40E_ITR_DYNAMIC;\n \tif (!ec->use_adaptive_rx_coalesce)\n@@ -563,8 +563,8 @@ static int __i40evf_set_coalesce(struct net_device *netdev,\n \tif (ec->rx_coalesce_usecs == 0) {\n \t\tif (ec->use_adaptive_rx_coalesce)\n \t\t\tnetif_info(adapter, drv, netdev, \"rx-usecs=0, need to disable adaptive-rx for a complete disable\\n\");\n-\t} else if ((ec->rx_coalesce_usecs < (I40E_MIN_ITR << 1)) ||\n-\t\t (ec->rx_coalesce_usecs > (I40E_MAX_ITR << 1))) {\n+\t} else if ((ec->rx_coalesce_usecs < I40E_MIN_ITR) ||\n+\t\t (ec->rx_coalesce_usecs > I40E_MAX_ITR)) {\n \t\tnetif_info(adapter, drv, netdev, \"Invalid value, rx-usecs range is 0-8160\\n\");\n \t\treturn -EINVAL;\n \t}\n@@ -573,8 +573,8 @@ static int __i40evf_set_coalesce(struct net_device *netdev,\n \tif (ec->tx_coalesce_usecs == 0) {\n \t\tif (ec->use_adaptive_tx_coalesce)\n \t\t\tnetif_info(adapter, drv, netdev, \"tx-usecs=0, need to disable adaptive-tx for a complete disable\\n\");\n-\t} else if ((ec->tx_coalesce_usecs < (I40E_MIN_ITR << 1)) ||\n-\t\t (ec->tx_coalesce_usecs > (I40E_MAX_ITR << 1))) {\n+\t} else if ((ec->tx_coalesce_usecs < I40E_MIN_ITR) ||\n+\t\t (ec->tx_coalesce_usecs > I40E_MAX_ITR)) {\n \t\tnetif_info(adapter, drv, netdev, \"Invalid value, tx-usecs range is 0-8160\\n\");\n \t\treturn -EINVAL;\n \t}\n", "prefixes": [ "next", "S85-V1", "11/14" ] }