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GET /api/patches/854010/?format=api
{ "id": 854010, "url": "http://patchwork.ozlabs.org/api/patches/854010/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20171229135055.14598-1-alice.michael@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20171229135055.14598-1-alice.michael@intel.com>", "list_archive_url": null, "date": "2017-12-29T13:50:55", "name": "[next,S85-V1,10/14] i40e/i40evf: Don't bother setting the CLEARPBA bit", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "9f6a0cccaf2e605fb52e8a8a1ce67951332479fe", "submitter": { "id": 71123, "url": "http://patchwork.ozlabs.org/api/people/71123/?format=api", "name": "Michael, Alice", "email": "alice.michael@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20171229135055.14598-1-alice.michael@intel.com/mbox/", "series": [ { "id": 20665, "url": "http://patchwork.ozlabs.org/api/series/20665/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=20665", "date": "2017-12-29T13:48:33", "name": "[next,S85-V1,01/14] i40e: fix typo in function description", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/20665/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/854010/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/854010/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=osuosl.org\n\t(client-ip=140.211.166.138; helo=whitealder.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3z7gSP003Mz9s7G\n\tfor <incoming@patchwork.ozlabs.org>;\n\tSat, 30 Dec 2017 08:57:56 +1100 (AEDT)", "from localhost (localhost [127.0.0.1])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 4399B87E97;\n\tFri, 29 Dec 2017 21:57:55 +0000 (UTC)", "from whitealder.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id msM6IVltfVkQ; Fri, 29 Dec 2017 21:57:54 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 5A917878E6;\n\tFri, 29 Dec 2017 21:57:54 +0000 (UTC)", "from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136])\n\tby ash.osuosl.org (Postfix) with ESMTP id 9E7751C0180\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tFri, 29 Dec 2017 21:57:52 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby silver.osuosl.org (Postfix) with ESMTP id 9A1E4292AA\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tFri, 29 Dec 2017 21:57:52 +0000 (UTC)", "from silver.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id Q2MAcHrNksKR for <intel-wired-lan@lists.osuosl.org>;\n\tFri, 29 Dec 2017 21:57:52 +0000 (UTC)", "from mga05.intel.com (mga05.intel.com [192.55.52.43])\n\tby silver.osuosl.org (Postfix) with ESMTPS id EE763253F9\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tFri, 29 Dec 2017 21:57:51 +0000 (UTC)", "from orsmga002.jf.intel.com ([10.7.209.21])\n\tby fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t29 Dec 2017 13:57:51 -0800", "from alicemic-2.jf.intel.com ([10.166.16.121])\n\tby orsmga002.jf.intel.com with ESMTP; 29 Dec 2017 13:57:51 -0800" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.45,478,1508828400\"; d=\"scan'208\";a=\"22483384\"", "From": "Alice Michael <alice.michael@intel.com>", "To": "alice.michael@intel.com,\n\tintel-wired-lan@lists.osuosl.org", "Date": "Fri, 29 Dec 2017 08:50:55 -0500", "Message-Id": "<20171229135055.14598-1-alice.michael@intel.com>", "X-Mailer": "git-send-email 2.9.5", "Subject": "[Intel-wired-lan] [next PATCH S85-V1 10/14] i40e/i40evf: Don't\n\tbother setting the CLEARPBA bit", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.24", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "From: Alexander Duyck <alexander.h.duyck@intel.com>\n\nThe CLEARPBA bit in the dynamic interrupt control register actually has\nno effect either way on the hardware. As per errata 28 in the XL710\nspecification update the interrupt is actually cleared any time the\nregister is written with the INTENA_MSK bit set to 0. As such the act of\ntoggling the enable bit actually will trigger the interrupt being\ncleared and could lead to potential lost events if auto-masking is\nnot enabled.\n\nSigned-off-by: Alexander Duyck <alexander.h.duyck@intel.com>\n---\n drivers/net/ethernet/intel/i40e/i40e_txrx.c | 11 ++++++++++-\n drivers/net/ethernet/intel/i40evf/i40e_txrx.c | 11 ++++++++++-\n 2 files changed, 20 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/i40e/i40e_txrx.c b/drivers/net/ethernet/intel/i40e/i40e_txrx.c\nindex 4e661ef..628ec59 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_txrx.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_txrx.c\n@@ -2267,8 +2267,17 @@ static u32 i40e_buildreg_itr(const int type, const u16 itr)\n {\n \tu32 val;\n \n+\t/* We don't bother with setting the CLEARPBA bit as the data sheet\n+\t * points out doing so is \"meaningless since it was already\n+\t * auto-cleared\". The auto-clearing happens when the interrupt is\n+\t * asserted.\n+\t *\n+\t * Hardware errata 28 for also indicates that writing to a\n+\t * xxINT_DYN_CTLx CSR with INTENA_MSK (bit 31) set to 0 will clear\n+\t * an event in the PBA anyway so we need to rely on the automask\n+\t * to hold pending events for us until the interrupt is re-enabled\n+\t */\n \tval = I40E_PFINT_DYN_CTLN_INTENA_MASK |\n-\t I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |\n \t (type << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |\n \t (itr << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT);\n \ndiff --git a/drivers/net/ethernet/intel/i40evf/i40e_txrx.c b/drivers/net/ethernet/intel/i40evf/i40e_txrx.c\nindex 3fd7e97..34d898f 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40e_txrx.c\n+++ b/drivers/net/ethernet/intel/i40evf/i40e_txrx.c\n@@ -1464,8 +1464,17 @@ static u32 i40e_buildreg_itr(const int type, const u16 itr)\n {\n \tu32 val;\n \n+\t/* We don't bother with setting the CLEARPBA bit as the data sheet\n+\t * points out doing so is \"meaningless since it was already\n+\t * auto-cleared\". The auto-clearing happens when the interrupt is\n+\t * asserted.\n+\t *\n+\t * Hardware errata 28 for also indicates that writing to a\n+\t * xxINT_DYN_CTLx CSR with INTENA_MSK (bit 31) set to 0 will clear\n+\t * an event in the PBA anyway so we need to rely on the automask\n+\t * to hold pending events for us until the interrupt is re-enabled\n+\t */\n \tval = I40E_VFINT_DYN_CTLN1_INTENA_MASK |\n-\t I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |\n \t (type << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |\n \t (itr << I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT);\n \n", "prefixes": [ "next", "S85-V1", "10/14" ] }