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GET /api/patches/854005/?format=api
{ "id": 854005, "url": "http://patchwork.ozlabs.org/api/patches/854005/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20171229134953.14355-1-alice.michael@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20171229134953.14355-1-alice.michael@intel.com>", "list_archive_url": null, "date": "2017-12-29T13:49:53", "name": "[next,S85-V1,05/14] i40e/i40evf: Clean up logic for adaptive ITR", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "41a3a1d78600ac935f65f191645d41371ed8e73e", "submitter": { "id": 71123, "url": "http://patchwork.ozlabs.org/api/people/71123/?format=api", "name": "Michael, Alice", "email": "alice.michael@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20171229134953.14355-1-alice.michael@intel.com/mbox/", "series": [ { "id": 20665, "url": "http://patchwork.ozlabs.org/api/series/20665/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=20665", "date": "2017-12-29T13:48:33", "name": "[next,S85-V1,01/14] i40e: fix typo in function description", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/20665/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/854005/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/854005/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=osuosl.org\n\t(client-ip=140.211.166.138; helo=whitealder.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3z7gRD19Zhz9s7G\n\tfor <incoming@patchwork.ozlabs.org>;\n\tSat, 30 Dec 2017 08:56:56 +1100 (AEDT)", "from localhost (localhost [127.0.0.1])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id A264684941;\n\tFri, 29 Dec 2017 21:56:54 +0000 (UTC)", "from whitealder.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id i3Brr5049t0R; Fri, 29 Dec 2017 21:56:53 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 302008065F;\n\tFri, 29 Dec 2017 21:56:53 +0000 (UTC)", "from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138])\n\tby ash.osuosl.org (Postfix) with ESMTP id 84E331C0180\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tFri, 29 Dec 2017 21:56:51 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 80585878E6\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tFri, 29 Dec 2017 21:56:51 +0000 (UTC)", "from whitealder.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id Y+XhkdqRewVo for <intel-wired-lan@lists.osuosl.org>;\n\tFri, 29 Dec 2017 21:56:50 +0000 (UTC)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n\tby whitealder.osuosl.org (Postfix) with ESMTPS id 7C05E878DB\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tFri, 29 Dec 2017 21:56:50 +0000 (UTC)", "from orsmga007.jf.intel.com ([10.7.209.58])\n\tby orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t29 Dec 2017 13:56:49 -0800", "from alicemic-2.jf.intel.com ([10.166.16.121])\n\tby orsmga007.jf.intel.com with ESMTP; 29 Dec 2017 13:56:49 -0800" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.45,478,1508828400\"; d=\"scan'208\";a=\"6368080\"", "From": "Alice Michael <alice.michael@intel.com>", "To": "alice.michael@intel.com,\n\tintel-wired-lan@lists.osuosl.org", "Date": "Fri, 29 Dec 2017 08:49:53 -0500", "Message-Id": "<20171229134953.14355-1-alice.michael@intel.com>", "X-Mailer": "git-send-email 2.9.5", "Subject": "[Intel-wired-lan] [next PATCH S85-V1 05/14] i40e/i40evf: Clean up\n\tlogic for adaptive ITR", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.24", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "From: Alexander Duyck <alexander.h.duyck@intel.com>\n\nThe logic for dynamic ITR update is confusing at best as there were odd\npaths chosen for how to find the rings associated with a given queue based\non the vector index and other inconsistencies throughout the code.\n\nThis patch is an attempt to clean up the logic so that we can more easily\nunderstand what is going on. Specifically if there is a Rx or Tx ring that\nis enabled in dynamic mode on the q_vector it is allowed to override the\nother side of the interrupt moderation. While it isn't correct all this\npatch is doing is cleaning up the logic for now so that when we come\nthrough and fix it we can more easily identify that this is wrong.\n\nThe other big change made here is that we replace references to:\n\tvsi->rx_rings[q_vector->v_idx]->itr_setting\nwith:\n\tq_vector->rx.ring->itr_setting\n\nThe general idea is we can avoid the long pointer chase since just\naccessing q_vector->rx.ring is a single pointer access versus having to\nchase down vsi->rx_rings, and then finding the pointer in the array, and\nfinally chasing down the itr_setting from there.\n\nSigned-off-by: Alexander Duyck <alexander.h.duyck@intel.com>\n---\n drivers/net/ethernet/intel/i40e/i40e_txrx.c | 55 +++++++------------------\n drivers/net/ethernet/intel/i40evf/i40e_txrx.c | 59 +++++++--------------------\n 2 files changed, 28 insertions(+), 86 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/i40e/i40e_txrx.c b/drivers/net/ethernet/intel/i40e/i40e_txrx.c\nindex 44d360e..4e661ef 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_txrx.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_txrx.c\n@@ -1015,6 +1015,9 @@ static bool i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)\n \tint bytes_per_usec;\n \tunsigned int usecs, estimated_usecs;\n \n+\tif (!rc->ring || !ITR_IS_DYNAMIC(rc->ring->itr_setting))\n+\t\treturn false;\n+\n \tif (rc->total_packets == 0 || !rc->itr)\n \t\treturn false;\n \n@@ -2274,15 +2277,6 @@ static u32 i40e_buildreg_itr(const int type, const u16 itr)\n \n /* a small macro to shorten up some long lines */\n #define INTREG I40E_PFINT_DYN_CTLN\n-static inline int get_rx_itr(struct i40e_vsi *vsi, int idx)\n-{\n-\treturn vsi->rx_rings[idx]->itr_setting;\n-}\n-\n-static inline int get_tx_itr(struct i40e_vsi *vsi, int idx)\n-{\n-\treturn vsi->tx_rings[idx]->itr_setting;\n-}\n \n /**\n * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt\n@@ -2295,9 +2289,7 @@ static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,\n {\n \tstruct i40e_hw *hw = &vsi->back->hw;\n \tbool rx = false, tx = false;\n-\tu32 rxval, txval;\n-\tint idx = q_vector->v_idx;\n-\tint rx_itr_setting, tx_itr_setting;\n+\tu32 txval;\n \n \t/* If we don't have MSIX, then we only need to re-enable icr0 */\n \tif (!(vsi->back->flags & I40E_FLAG_MSIX_ENABLED)) {\n@@ -2305,29 +2297,15 @@ static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,\n \t\treturn;\n \t}\n \n-\t/* avoid dynamic calculation if in countdown mode OR if\n-\t * all dynamic is disabled\n-\t */\n \ttxval = i40e_buildreg_itr(I40E_ITR_NONE, 0);\n \n-\trx_itr_setting = get_rx_itr(vsi, idx);\n-\ttx_itr_setting = get_tx_itr(vsi, idx);\n-\n-\tif (q_vector->itr_countdown > 0 ||\n-\t (!ITR_IS_DYNAMIC(rx_itr_setting) &&\n-\t !ITR_IS_DYNAMIC(tx_itr_setting))) {\n+\t/* avoid dynamic calculation if in countdown mode */\n+\tif (q_vector->itr_countdown > 0)\n \t\tgoto enable_int;\n-\t}\n \n-\tif (ITR_IS_DYNAMIC(rx_itr_setting)) {\n-\t\trx = i40e_set_new_dynamic_itr(&q_vector->rx);\n-\t\trxval = i40e_buildreg_itr(I40E_RX_ITR, q_vector->rx.itr);\n-\t}\n-\n-\tif (ITR_IS_DYNAMIC(tx_itr_setting)) {\n-\t\ttx = i40e_set_new_dynamic_itr(&q_vector->tx);\n-\t\ttxval = i40e_buildreg_itr(I40E_TX_ITR, q_vector->tx.itr);\n-\t}\n+\t/* these will return false if dynamic mode is disabled */\n+\trx = i40e_set_new_dynamic_itr(&q_vector->rx);\n+\ttx = i40e_set_new_dynamic_itr(&q_vector->tx);\n \n \tif (rx || tx) {\n \t\t/* get the higher of the two ITR adjustments and\n@@ -2335,25 +2313,20 @@ static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,\n \t\t * when in adaptive mode (Rx and/or Tx)\n \t\t */\n \t\tu16 itr = max(q_vector->tx.itr, q_vector->rx.itr);\n+\t\tu32 rxval;\n \n \t\tq_vector->tx.itr = q_vector->rx.itr = itr;\n-\t\ttxval = i40e_buildreg_itr(I40E_TX_ITR, itr);\n-\t\ttx = true;\n-\t\trxval = i40e_buildreg_itr(I40E_RX_ITR, itr);\n-\t\trx = true;\n-\t}\n \n-\t/* only need to enable the interrupt once, but need\n-\t * to possibly update both ITR values\n-\t */\n-\tif (rx) {\n \t\t/* set the INTENA_MSK_MASK so that this first write\n \t\t * won't actually enable the interrupt, instead just\n \t\t * updating the ITR (it's bit 31 PF and VF)\n \t\t */\n-\t\trxval |= BIT(31);\n+\t\trxval = i40e_buildreg_itr(I40E_RX_ITR, itr) | BIT(31);\n+\n \t\t/* don't check _DOWN because interrupt isn't being enabled */\n \t\twr32(hw, INTREG(q_vector->reg_idx), rxval);\n+\n+\t\ttxval = i40e_buildreg_itr(I40E_TX_ITR, itr);\n \t}\n \n enable_int:\ndiff --git a/drivers/net/ethernet/intel/i40evf/i40e_txrx.c b/drivers/net/ethernet/intel/i40evf/i40e_txrx.c\nindex 291130a..3fd7e97 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40e_txrx.c\n+++ b/drivers/net/ethernet/intel/i40evf/i40e_txrx.c\n@@ -413,6 +413,9 @@ static bool i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)\n \tint bytes_per_usec;\n \tunsigned int usecs, estimated_usecs;\n \n+\tif (!rc->ring || !ITR_IS_DYNAMIC(rc->ring->itr_setting))\n+\t\treturn false;\n+\n \tif (rc->total_packets == 0 || !rc->itr)\n \t\treturn false;\n \n@@ -1471,19 +1474,6 @@ static u32 i40e_buildreg_itr(const int type, const u16 itr)\n \n /* a small macro to shorten up some long lines */\n #define INTREG I40E_VFINT_DYN_CTLN1\n-static inline int get_rx_itr(struct i40e_vsi *vsi, int idx)\n-{\n-\tstruct i40evf_adapter *adapter = vsi->back;\n-\n-\treturn adapter->rx_rings[idx].itr_setting;\n-}\n-\n-static inline int get_tx_itr(struct i40e_vsi *vsi, int idx)\n-{\n-\tstruct i40evf_adapter *adapter = vsi->back;\n-\n-\treturn adapter->tx_rings[idx].itr_setting;\n-}\n \n /**\n * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt\n@@ -1496,33 +1486,17 @@ static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,\n {\n \tstruct i40e_hw *hw = &vsi->back->hw;\n \tbool rx = false, tx = false;\n-\tu32 rxval, txval;\n-\tint idx = q_vector->v_idx;\n-\tint rx_itr_setting, tx_itr_setting;\n+\tu32 txval;\n \n-\t/* avoid dynamic calculation if in countdown mode OR if\n-\t * all dynamic is disabled\n-\t */\n \ttxval = i40e_buildreg_itr(I40E_ITR_NONE, 0);\n \n-\trx_itr_setting = get_rx_itr(vsi, idx);\n-\ttx_itr_setting = get_tx_itr(vsi, idx);\n-\n-\tif (q_vector->itr_countdown > 0 ||\n-\t (!ITR_IS_DYNAMIC(rx_itr_setting) &&\n-\t !ITR_IS_DYNAMIC(tx_itr_setting))) {\n+\t/* avoid dynamic calculation if in countdown mode */\n+\tif (q_vector->itr_countdown > 0)\n \t\tgoto enable_int;\n-\t}\n \n-\tif (ITR_IS_DYNAMIC(rx_itr_setting)) {\n-\t\trx = i40e_set_new_dynamic_itr(&q_vector->rx);\n-\t\trxval = i40e_buildreg_itr(I40E_RX_ITR, q_vector->rx.itr);\n-\t}\n-\n-\tif (ITR_IS_DYNAMIC(tx_itr_setting)) {\n-\t\ttx = i40e_set_new_dynamic_itr(&q_vector->tx);\n-\t\ttxval = i40e_buildreg_itr(I40E_TX_ITR, q_vector->tx.itr);\n-\t}\n+\t/* these will return false if dynamic mode is disabled */\n+\trx = i40e_set_new_dynamic_itr(&q_vector->rx);\n+\ttx = i40e_set_new_dynamic_itr(&q_vector->tx);\n \n \tif (rx || tx) {\n \t\t/* get the higher of the two ITR adjustments and\n@@ -1530,25 +1504,20 @@ static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,\n \t\t * when in adaptive mode (Rx and/or Tx)\n \t\t */\n \t\tu16 itr = max(q_vector->tx.itr, q_vector->rx.itr);\n+\t\tu32 rxval;\n \n \t\tq_vector->tx.itr = q_vector->rx.itr = itr;\n-\t\ttxval = i40e_buildreg_itr(I40E_TX_ITR, itr);\n-\t\ttx = true;\n-\t\trxval = i40e_buildreg_itr(I40E_RX_ITR, itr);\n-\t\trx = true;\n-\t}\n \n-\t/* only need to enable the interrupt once, but need\n-\t * to possibly update both ITR values\n-\t */\n-\tif (rx) {\n \t\t/* set the INTENA_MSK_MASK so that this first write\n \t\t * won't actually enable the interrupt, instead just\n \t\t * updating the ITR (it's bit 31 PF and VF)\n \t\t */\n-\t\trxval |= BIT(31);\n+\t\trxval = i40e_buildreg_itr(I40E_RX_ITR, itr) | BIT(31);\n+\n \t\t/* don't check _DOWN because interrupt isn't being enabled */\n \t\twr32(hw, INTREG(q_vector->reg_idx), rxval);\n+\n+\t\ttxval = i40e_buildreg_itr(I40E_TX_ITR, itr);\n \t}\n \n enable_int:\n", "prefixes": [ "next", "S85-V1", "05/14" ] }