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GET /api/patches/847667/?format=api
{ "id": 847667, "url": "http://patchwork.ozlabs.org/api/patches/847667/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1513121823-27944-3-git-send-email-shannon.nelson@oracle.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1513121823-27944-3-git-send-email-shannon.nelson@oracle.com>", "list_archive_url": null, "date": "2017-12-12T23:36:55", "name": "[v2,next-queue,02/10] ixgbe: add ipsec register access routines", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "e2829459981afefc792abbbd916f80d466342af0", "submitter": { "id": 70766, "url": "http://patchwork.ozlabs.org/api/people/70766/?format=api", "name": "Shannon Nelson", "email": "shannon.nelson@oracle.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1513121823-27944-3-git-send-email-shannon.nelson@oracle.com/mbox/", "series": [ { "id": 18198, "url": "http://patchwork.ozlabs.org/api/series/18198/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=18198", "date": "2017-12-12T23:36:53", "name": "ixgbe: Add ipsec offload", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/18198/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/847667/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/847667/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=osuosl.org\n\t(client-ip=140.211.166.133; helo=hemlock.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=oracle.com header.i=@oracle.com\n\theader.b=\"mJWF1RsI\"; dkim-atps=neutral" ], "Received": [ "from hemlock.osuosl.org (smtp2.osuosl.org [140.211.166.133])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yxGT10PRSz9t3R\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 13 Dec 2017 10:37:25 +1100 (AEDT)", "from localhost (localhost [127.0.0.1])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id 9D023882F4;\n\tTue, 12 Dec 2017 23:37:23 +0000 (UTC)", "from hemlock.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id R9wdVnCdQT6q; Tue, 12 Dec 2017 23:37:21 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id 61A59882F3;\n\tTue, 12 Dec 2017 23:37:21 +0000 (UTC)", "from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136])\n\tby ash.osuosl.org (Postfix) with ESMTP id 214BC1BF54B\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tTue, 12 Dec 2017 23:37:20 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby silver.osuosl.org (Postfix) with ESMTP id 1C3052FC3C\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tTue, 12 Dec 2017 23:37:20 +0000 (UTC)", "from silver.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id EcAHC67PwvEn for <intel-wired-lan@lists.osuosl.org>;\n\tTue, 12 Dec 2017 23:37:18 +0000 (UTC)", "from aserp2130.oracle.com (aserp2130.oracle.com [141.146.126.79])\n\tby silver.osuosl.org (Postfix) with ESMTPS id CA3962FC67\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tTue, 12 Dec 2017 23:37:18 +0000 (UTC)", "from pps.filterd (aserp2130.oracle.com [127.0.0.1])\n\tby aserp2130.oracle.com (8.16.0.21/8.16.0.21) with SMTP id\n\tvBCNQaYM148530; Tue, 12 Dec 2017 23:37:17 GMT", "from userv0022.oracle.com (userv0022.oracle.com [156.151.31.74])\n\tby aserp2130.oracle.com with ESMTP id 2etrs8r2hy-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256\n\tverify=OK); Tue, 12 Dec 2017 23:37:16 +0000", "from aserv0122.oracle.com (aserv0122.oracle.com [141.146.126.236])\n\tby userv0022.oracle.com (8.14.4/8.14.4) with ESMTP id\n\tvBCNbFuo029255\n\t(version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256\n\tverify=OK); Tue, 12 Dec 2017 23:37:16 GMT", "from abhmp0001.oracle.com (abhmp0001.oracle.com [141.146.116.7])\n\tby aserv0122.oracle.com (8.14.4/8.14.4) with ESMTP id vBCNbEfx017410; \n\tTue, 12 Dec 2017 23:37:14 GMT", "from slnelson-mint18.us.oracle.com (/10.159.225.160)\n\tby default (Oracle Beehive Gateway v4.0)\n\twith ESMTP ; Tue, 12 Dec 2017 15:37:14 -0800" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references;\n\ts=corp-2017-10-26; \n\tbh=12JUM0HQLVtJxtKX//ZwlhCB2r38L57ssNVSIPUAQmY=;\n\tb=mJWF1RsIeu3kVqPRxRsqJnewOcnBGRczubsPoxinz7G/JQkLBHHfpqFlnFZXu0XXPILv\n\tFTchjEWjAu77nK3nhHN+a41gx7GEC7PTg22YJd8XxUlW3Snpl97jyCaMeipjdZhFVGLz\n\tIRIagnYUiMu/xe1/6SlU/Ps0y6q5bNipiN43ZJGzfpyDGwEGtDgT6nLTxnAgzPL9RP3k\n\t/eb1e/KTdQhDmpQMzpiNReTY+NxuyagtsVQaux/Bzubll8zYOBZhZmpwZFyA+g3PmJ3k\n\tv6Mjm7NryyzizLwirvsE3qgg7MuEQQaO35+eNIjnJQU4LI7pKvXapWzH8en/c7UYg3Hz\n\txg== ", "From": "Shannon Nelson <shannon.nelson@oracle.com>", "To": "intel-wired-lan@lists.osuosl.org, jeffrey.t.kirsher@intel.com", "Date": "Tue, 12 Dec 2017 15:36:55 -0800", "Message-Id": "<1513121823-27944-3-git-send-email-shannon.nelson@oracle.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1513121823-27944-1-git-send-email-shannon.nelson@oracle.com>", "References": "<1513121823-27944-1-git-send-email-shannon.nelson@oracle.com>", "X-Proofpoint-Virus-Version": "vendor=nai engine=5900 definitions=8743\n\tsignatures=668646", "X-Proofpoint-Spam-Details": "rule=notspam policy=default score=0 suspectscore=0\n\tmalwarescore=0\n\tphishscore=0 bulkscore=0 spamscore=0 mlxscore=0 mlxlogscore=999\n\tadultscore=0 classifier=spam adjust=0 reason=mlx scancount=1\n\tengine=8.0.1-1711220000 definitions=main-1712120331", "Subject": "[Intel-wired-lan] [PATCH v2 next-queue 02/10] ixgbe: add ipsec\n\tregister access routines", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.24", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "Cc": "steffen.klassert@secunet.com, netdev@vger.kernel.org,\n\tsowmini.varadhan@oracle.com", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "Add a few routines to make access to the ipsec registers just a little\neasier, and throw in the beginnings of an initialization.\n\nSigned-off-by: Shannon Nelson <shannon.nelson@oracle.com>\n---\nv2: Rx table selector becomes an enum with a shift\n Combine the clear table loops into one\n Name the table index shift value\n Use the addr as __be32\n\n drivers/net/ethernet/intel/ixgbe/Makefile | 1 +\n drivers/net/ethernet/intel/ixgbe/ixgbe.h | 6 +\n drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c | 161 +++++++++++++++++++++++++\n drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.h | 52 ++++++++\n drivers/net/ethernet/intel/ixgbe/ixgbe_main.c | 1 +\n 5 files changed, 221 insertions(+)\n create mode 100644 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c\n create mode 100644 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.h", "diff": "diff --git a/drivers/net/ethernet/intel/ixgbe/Makefile b/drivers/net/ethernet/intel/ixgbe/Makefile\nindex 35e6fa6..8319465 100644\n--- a/drivers/net/ethernet/intel/ixgbe/Makefile\n+++ b/drivers/net/ethernet/intel/ixgbe/Makefile\n@@ -42,3 +42,4 @@ ixgbe-$(CONFIG_IXGBE_DCB) += ixgbe_dcb.o ixgbe_dcb_82598.o \\\n ixgbe-$(CONFIG_IXGBE_HWMON) += ixgbe_sysfs.o\n ixgbe-$(CONFIG_DEBUG_FS) += ixgbe_debugfs.o\n ixgbe-$(CONFIG_FCOE:m=y) += ixgbe_fcoe.o\n+ixgbe-$(CONFIG_XFRM_OFFLOAD) += ixgbe_ipsec.o\ndiff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe.h b/drivers/net/ethernet/intel/ixgbe/ixgbe.h\nindex dd55787..1e11462 100644\n--- a/drivers/net/ethernet/intel/ixgbe/ixgbe.h\n+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe.h\n@@ -52,6 +52,7 @@\n #ifdef CONFIG_IXGBE_DCA\n #include <linux/dca.h>\n #endif\n+#include \"ixgbe_ipsec.h\"\n \n #include <net/busy_poll.h>\n \n@@ -1001,4 +1002,9 @@ void ixgbe_store_key(struct ixgbe_adapter *adapter);\n void ixgbe_store_reta(struct ixgbe_adapter *adapter);\n s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,\n \t\t u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm);\n+#ifdef CONFIG_XFRM_OFFLOAD\n+void ixgbe_init_ipsec_offload(struct ixgbe_adapter *adapter);\n+#else\n+static inline void ixgbe_init_ipsec_offload(struct ixgbe_adapter *adapter) { };\n+#endif /* CONFIG_XFRM_OFFLOAD */\n #endif /* _IXGBE_H_ */\ndiff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c\nnew file mode 100644\nindex 0000000..4d71517\n--- /dev/null\n+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c\n@@ -0,0 +1,161 @@\n+/*******************************************************************************\n+ *\n+ * Intel 10 Gigabit PCI Express Linux driver\n+ * Copyright(c) 2017 Oracle and/or its affiliates. All rights reserved.\n+ *\n+ * This program is free software; you can redistribute it and/or modify it\n+ * under the terms and conditions of the GNU General Public License,\n+ * version 2, as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope it will be useful, but WITHOUT\n+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n+ * more details.\n+ *\n+ * You should have received a copy of the GNU General Public License along with\n+ * this program. If not, see <http://www.gnu.org/licenses/>.\n+ *\n+ * The full GNU General Public License is included in this distribution in\n+ * the file called \"COPYING\".\n+ *\n+ * Contact Information:\n+ * Linux NICS <linux.nics@intel.com>\n+ * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>\n+ * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n+ *\n+ ******************************************************************************/\n+\n+#include \"ixgbe.h\"\n+\n+/**\n+ * ixgbe_ipsec_set_tx_sa - set the Tx SA registers\n+ * @hw: hw specific details\n+ * @idx: register index to write\n+ * @key: key byte array\n+ * @salt: salt bytes\n+ **/\n+static void ixgbe_ipsec_set_tx_sa(struct ixgbe_hw *hw, u16 idx,\n+\t\t\t\t u32 key[], u32 salt)\n+{\n+\tu32 reg;\n+\tint i;\n+\n+\tfor (i = 0; i < 4; i++)\n+\t\tIXGBE_WRITE_REG(hw, IXGBE_IPSTXKEY(i), cpu_to_be32(key[3-i]));\n+\tIXGBE_WRITE_REG(hw, IXGBE_IPSTXSALT, cpu_to_be32(salt));\n+\tIXGBE_WRITE_FLUSH(hw);\n+\n+\treg = IXGBE_READ_REG(hw, IXGBE_IPSTXIDX);\n+\treg &= IXGBE_RXTXIDX_IPS_EN;\n+\treg |= idx << IXGBE_RXTXIDX_IDX_SHIFT | IXGBE_RXTXIDX_WRITE;\n+\tIXGBE_WRITE_REG(hw, IXGBE_IPSTXIDX, reg);\n+\tIXGBE_WRITE_FLUSH(hw);\n+}\n+\n+/**\n+ * ixgbe_ipsec_set_rx_item - set an Rx table item\n+ * @hw: hw specific details\n+ * @idx: register index to write\n+ * @tbl: table selector\n+ *\n+ * Trigger the device to store into a particular Rx table the\n+ * data that has already been loaded into the input register\n+ **/\n+static void ixgbe_ipsec_set_rx_item(struct ixgbe_hw *hw, u16 idx,\n+\t\t\t\t enum ixgbe_ipsec_tbl_sel tbl)\n+{\n+\tu32 reg;\n+\n+\treg = IXGBE_READ_REG(hw, IXGBE_IPSRXIDX);\n+\treg &= IXGBE_RXTXIDX_IPS_EN;\n+\treg |= tbl << IXGBE_RXIDX_TBL_SHIFT |\n+\t idx << IXGBE_RXTXIDX_IDX_SHIFT |\n+\t IXGBE_RXTXIDX_WRITE;\n+\tIXGBE_WRITE_REG(hw, IXGBE_IPSRXIDX, reg);\n+\tIXGBE_WRITE_FLUSH(hw);\n+}\n+\n+/**\n+ * ixgbe_ipsec_set_rx_sa - set up the register bits to save SA info\n+ * @hw: hw specific details\n+ * @idx: register index to write\n+ * @spi: security parameter index\n+ * @key: key byte array\n+ * @salt: salt bytes\n+ * @mode: rx decrypt control bits\n+ * @ip_idx: index into IP table for related IP address\n+ **/\n+static void ixgbe_ipsec_set_rx_sa(struct ixgbe_hw *hw, u16 idx, __be32 spi,\n+\t\t\t\t u32 key[], u32 salt, u32 mode, u32 ip_idx)\n+{\n+\tint i;\n+\n+\t/* store the SPI (in bigendian) and IPidx */\n+\tIXGBE_WRITE_REG(hw, IXGBE_IPSRXSPI, spi);\n+\tIXGBE_WRITE_REG(hw, IXGBE_IPSRXIPIDX, ip_idx);\n+\tIXGBE_WRITE_FLUSH(hw);\n+\n+\tixgbe_ipsec_set_rx_item(hw, idx, ips_rx_spi_tbl);\n+\n+\t/* store the key, salt, and mode */\n+\tfor (i = 0; i < 4; i++)\n+\t\tIXGBE_WRITE_REG(hw, IXGBE_IPSRXKEY(i), cpu_to_be32(key[3-i]));\n+\tIXGBE_WRITE_REG(hw, IXGBE_IPSRXSALT, cpu_to_be32(salt));\n+\tIXGBE_WRITE_REG(hw, IXGBE_IPSRXMOD, mode);\n+\tIXGBE_WRITE_FLUSH(hw);\n+\n+\tixgbe_ipsec_set_rx_item(hw, idx, ips_rx_key_tbl);\n+}\n+\n+/**\n+ * ixgbe_ipsec_set_rx_ip - set up the register bits to save SA IP addr info\n+ * @hw: hw specific details\n+ * @idx: register index to write\n+ * @addr: IP address byte array\n+ **/\n+static void ixgbe_ipsec_set_rx_ip(struct ixgbe_hw *hw, u16 idx, __be32 addr[])\n+{\n+\tint i;\n+\n+\t/* store the ip address */\n+\tfor (i = 0; i < 4; i++)\n+\t\tIXGBE_WRITE_REG(hw, IXGBE_IPSRXIPADDR(i), addr[i]);\n+\tIXGBE_WRITE_FLUSH(hw);\n+\n+\tixgbe_ipsec_set_rx_item(hw, idx, ips_rx_ip_tbl);\n+}\n+\n+/**\n+ * ixgbe_ipsec_clear_hw_tables - because some tables don't get cleared on reset\n+ * @adapter: board private structure\n+ **/\n+void ixgbe_ipsec_clear_hw_tables(struct ixgbe_adapter *adapter)\n+{\n+\tstruct ixgbe_hw *hw = &adapter->hw;\n+\tu32 buf[4] = {0, 0, 0, 0};\n+\tu16 idx;\n+\n+\t/* disable Rx and Tx SA lookup */\n+\tIXGBE_WRITE_REG(hw, IXGBE_IPSRXIDX, 0);\n+\tIXGBE_WRITE_REG(hw, IXGBE_IPSTXIDX, 0);\n+\n+\t/* scrub the tables - split the loops for the max of the IP table */\n+\tfor (idx = 0; idx < IXGBE_IPSEC_MAX_RX_IP_COUNT; idx++) {\n+\t\tixgbe_ipsec_set_tx_sa(hw, idx, buf, 0);\n+\t\tixgbe_ipsec_set_rx_sa(hw, idx, 0, buf, 0, 0, 0);\n+\t\tixgbe_ipsec_set_rx_ip(hw, idx, (__be32 *)buf);\n+\t}\n+\tfor (; idx < IXGBE_IPSEC_MAX_RX_IP_COUNT; idx++) {\n+\t\tixgbe_ipsec_set_tx_sa(hw, idx, buf, 0);\n+\t\tixgbe_ipsec_set_rx_sa(hw, idx, 0, buf, 0, 0, 0);\n+\t}\n+}\n+\n+/**\n+ * ixgbe_init_ipsec_offload - initialize security registers for IPSec operation\n+ * @adapter: board private structure\n+ **/\n+void ixgbe_init_ipsec_offload(struct ixgbe_adapter *adapter)\n+{\n+\tixgbe_ipsec_clear_hw_tables(adapter);\n+}\ndiff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.h b/drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.h\nnew file mode 100644\nindex 0000000..341d3f0\n--- /dev/null\n+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.h\n@@ -0,0 +1,52 @@\n+/*******************************************************************************\n+\n+ Intel 10 Gigabit PCI Express Linux driver\n+ Copyright(c) 2017 Oracle and/or its affiliates. All rights reserved.\n+\n+ This program is free software; you can redistribute it and/or modify it\n+ under the terms and conditions of the GNU General Public License,\n+ version 2, as published by the Free Software Foundation.\n+\n+ This program is distributed in the hope it will be useful, but WITHOUT\n+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n+ more details.\n+\n+ You should have received a copy of the GNU General Public License along with\n+ this program. If not, see <http://www.gnu.org/licenses/>.\n+\n+ The full GNU General Public License is included in this distribution in\n+ the file called \"COPYING\".\n+\n+ Contact Information:\n+ Linux NICS <linux.nics@intel.com>\n+ e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>\n+ Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n+\n+*******************************************************************************/\n+\n+#ifndef _IXGBE_IPSEC_H_\n+#define _IXGBE_IPSEC_H_\n+\n+#define IXGBE_IPSEC_MAX_SA_COUNT\t1024\n+#define IXGBE_IPSEC_MAX_RX_IP_COUNT\t128\n+#define IXGBE_IPSEC_BASE_RX_INDEX\t0\n+#define IXGBE_IPSEC_BASE_TX_INDEX\tIXGBE_IPSEC_MAX_SA_COUNT\n+\n+#define IXGBE_RXTXIDX_IPS_EN\t\t0x00000001\n+#define IXGBE_RXIDX_TBL_SHIFT\t\t1\n+enum ixgbe_ipsec_tbl_sel {\n+\tips_rx_ip_tbl\t=\t0x01,\n+\tips_rx_spi_tbl\t=\t0x02,\n+\tips_rx_key_tbl\t=\t0x03,\n+};\n+#define IXGBE_RXTXIDX_IDX_SHIFT\t\t3\n+#define IXGBE_RXTXIDX_READ\t\t0x40000000\n+#define IXGBE_RXTXIDX_WRITE\t\t0x80000000\n+\n+#define IXGBE_RXMOD_VALID\t\t0x00000001\n+#define IXGBE_RXMOD_PROTO_ESP\t\t0x00000004\n+#define IXGBE_RXMOD_DECRYPT\t\t0x00000008\n+#define IXGBE_RXMOD_IPV6\t\t0x00000010\n+\n+#endif /* _IXGBE_IPSEC_H_ */\ndiff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c\nindex 6d5f31e..51fb3cf 100644\n--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c\n+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c\n@@ -10327,6 +10327,7 @@ static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)\n \t\t\t\t\t NETIF_F_FCOE_MTU;\n \t}\n #endif /* IXGBE_FCOE */\n+\tixgbe_init_ipsec_offload(adapter);\n \n \tif (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)\n \t\tnetdev->hw_features |= NETIF_F_LRO;\n", "prefixes": [ "v2", "next-queue", "02/10" ] }