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GET /api/patches/838024/?format=api
{ "id": 838024, "url": "http://patchwork.ozlabs.org/api/patches/838024/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20171114120052.86665-1-alice.michael@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20171114120052.86665-1-alice.michael@intel.com>", "list_archive_url": null, "date": "2017-11-14T12:00:44", "name": "[next,S82-V4,1/9] i40evf: Do not clear MSI-X PBA manually", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "f8cd7c11a6be2a15671ba31b314fea9651624a5d", "submitter": { "id": 71123, "url": "http://patchwork.ozlabs.org/api/people/71123/?format=api", "name": "Michael, Alice", "email": "alice.michael@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20171114120052.86665-1-alice.michael@intel.com/mbox/", "series": [ { "id": 13564, "url": "http://patchwork.ozlabs.org/api/series/13564/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=13564", "date": "2017-11-14T12:00:46", "name": "[next,S82-V4,1/9] i40evf: Do not clear MSI-X PBA manually", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/13564/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/838024/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/838024/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=osuosl.org\n\t(client-ip=140.211.166.138; helo=whitealder.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3ybzVm16yqz9sDB\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 15 Nov 2017 07:23:59 +1100 (AEDT)", "from localhost (localhost [127.0.0.1])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 935F4872B2;\n\tTue, 14 Nov 2017 20:23:58 +0000 (UTC)", "from whitealder.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id 6ocPTLxkIz4T; Tue, 14 Nov 2017 20:23:55 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 82D4F87302;\n\tTue, 14 Nov 2017 20:23:48 +0000 (UTC)", "from hemlock.osuosl.org (smtp2.osuosl.org [140.211.166.133])\n\tby ash.osuosl.org (Postfix) with ESMTP id B006C1BFC3F\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tTue, 14 Nov 2017 20:07:05 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id 9AFDE880E3\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tTue, 14 Nov 2017 20:07:05 +0000 (UTC)", "from hemlock.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id ss6Z3hG+9x-S for <intel-wired-lan@lists.osuosl.org>;\n\tTue, 14 Nov 2017 20:06:59 +0000 (UTC)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n\tby hemlock.osuosl.org (Postfix) with ESMTPS id 72435878B0\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tTue, 14 Nov 2017 20:06:59 +0000 (UTC)", "from fmsmga001.fm.intel.com ([10.253.24.23])\n\tby orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t14 Nov 2017 12:06:58 -0800", "from unknown (HELO localhost.jf.intel.com) ([10.166.16.121])\n\tby fmsmga001.fm.intel.com with ESMTP; 14 Nov 2017 12:06:58 -0800" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.44,396,1505804400\"; d=\"scan'208\";a=\"2651446\"", "From": "Alice Michael <alice.michael@intel.com>", "To": "alice.michael@intel.com,\n\tintel-wired-lan@lists.osuosl.org", "Date": "Tue, 14 Nov 2017 07:00:44 -0500", "Message-Id": "<20171114120052.86665-1-alice.michael@intel.com>", "X-Mailer": "git-send-email 2.9.5", "Subject": "[Intel-wired-lan] [next PATCH S82-V4 1/9] i40evf: Do not clear\n\tMSI-X PBA manually", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.24", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "From: Alexander Duyck <alexander.h.duyck@intel.com>\n\nWe should not be clearing the pending bit array for each vector manually.\nThe documentation for the hardware states that when in MSI-X mode the\npending bit array wil be cleared automatically. Us clearing it ourselves\njust results in multiple opportunities for us to drop an interrupt.\n\nSigned-off-by: Alexander Duyck <alexander.h.duyck@intel.com>\n---\n drivers/net/ethernet/intel/i40evf/i40evf_main.c | 18 +++++-------------\n 1 file changed, 5 insertions(+), 13 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/i40evf/i40evf_main.c b/drivers/net/ethernet/intel/i40evf/i40evf_main.c\nindex 75dc94f..4dd3149 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40evf_main.c\n+++ b/drivers/net/ethernet/intel/i40evf/i40evf_main.c\n@@ -276,8 +276,7 @@ void i40evf_irq_enable_queues(struct i40evf_adapter *adapter, u32 mask)\n \t\tif (mask & BIT(i - 1)) {\n \t\t\twr32(hw, I40E_VFINT_DYN_CTLN1(i - 1),\n \t\t\t I40E_VFINT_DYN_CTLN1_INTENA_MASK |\n-\t\t\t I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK |\n-\t\t\t I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK);\n+\t\t\t I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK);\n \t\t}\n \t}\n }\n@@ -296,16 +295,14 @@ static void i40evf_fire_sw_int(struct i40evf_adapter *adapter, u32 mask)\n \tif (mask & 1) {\n \t\tdyn_ctl = rd32(hw, I40E_VFINT_DYN_CTL01);\n \t\tdyn_ctl |= I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK |\n-\t\t\t I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK |\n-\t\t\t I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK;\n+\t\t\t I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK;\n \t\twr32(hw, I40E_VFINT_DYN_CTL01, dyn_ctl);\n \t}\n \tfor (i = 1; i < adapter->num_msix_vectors; i++) {\n \t\tif (mask & BIT(i)) {\n \t\t\tdyn_ctl = rd32(hw, I40E_VFINT_DYN_CTLN1(i - 1));\n \t\t\tdyn_ctl |= I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK |\n-\t\t\t\t I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK |\n-\t\t\t\t I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK;\n+\t\t\t\t I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK;\n \t\t\twr32(hw, I40E_VFINT_DYN_CTLN1(i - 1), dyn_ctl);\n \t\t}\n \t}\n@@ -337,15 +334,10 @@ static irqreturn_t i40evf_msix_aq(int irq, void *data)\n \tstruct net_device *netdev = data;\n \tstruct i40evf_adapter *adapter = netdev_priv(netdev);\n \tstruct i40e_hw *hw = &adapter->hw;\n-\tu32 val;\n \n \t/* handle non-queue interrupts, these reads clear the registers */\n-\tval = rd32(hw, I40E_VFINT_ICR01);\n-\tval = rd32(hw, I40E_VFINT_ICR0_ENA1);\n-\n-\tval = rd32(hw, I40E_VFINT_DYN_CTL01) |\n-\t I40E_VFINT_DYN_CTL01_CLEARPBA_MASK;\n-\twr32(hw, I40E_VFINT_DYN_CTL01, val);\n+\trd32(hw, I40E_VFINT_ICR01);\n+\trd32(hw, I40E_VFINT_ICR0_ENA1);\n \n \t/* schedule work on the private workqueue */\n \tschedule_work(&adapter->adminq_task);\n", "prefixes": [ "next", "S82-V4", "1/9" ] }