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GET /api/patches/819509/?format=api
{ "id": 819509, "url": "http://patchwork.ozlabs.org/api/patches/819509/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20170928095628.21966-9-thierry.reding@gmail.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170928095628.21966-9-thierry.reding@gmail.com>", "list_archive_url": null, "date": "2017-09-28T09:56:20", "name": "[v2,08/16] gpio: Move irq_nested into struct gpio_irq_chip", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "4e3904ebea4ca5768e5ed8f00c2c406413c62133", "submitter": { "id": 26234, "url": "http://patchwork.ozlabs.org/api/people/26234/?format=api", "name": "Thierry Reding", "email": "thierry.reding@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20170928095628.21966-9-thierry.reding@gmail.com/mbox/", "series": [ { "id": 5529, "url": "http://patchwork.ozlabs.org/api/series/5529/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=5529", "date": "2017-09-28T09:56:12", "name": "gpio: Tight IRQ chip integration and banked infrastructure", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/5529/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/819509/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/819509/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-gpio-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"SWiZ4awm\"; dkim-atps=neutral" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2qsc6rhrz9t5l\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 28 Sep 2017 19:59:16 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1753141AbdI1J7A (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tThu, 28 Sep 2017 05:59:00 -0400", "from mail-qk0-f194.google.com ([209.85.220.194]:33826 \"EHLO\n\tmail-qk0-f194.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752867AbdI1J4y (ORCPT\n\t<rfc822; linux-gpio@vger.kernel.org>); Thu, 28 Sep 2017 05:56:54 -0400", "by mail-qk0-f194.google.com with SMTP id d70so651217qkc.1;\n\tThu, 28 Sep 2017 02:56:54 -0700 (PDT)", "from localhost\n\t(p200300E41BCC8100EA54DC343767CF80.dip0.t-ipconnect.de.\n\t[2003:e4:1bcc:8100:ea54:dc34:3767:cf80])\n\tby smtp.gmail.com with ESMTPSA id\n\tt184sm720979qkc.74.2017.09.28.02.56.52\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tThu, 28 Sep 2017 02:56:53 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=gmail.com; s=20161025;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=lauJTMVnvUbbgRaHR4hOjI8pwXek0yeu+kiFChNq/+M=;\n\tb=SWiZ4awm/0GnKP1bBPM4IwApl99LUvRDLRdVyXRKgDIzXuNJ+dzYLe0r4Dsy3qjyKL\n\t2mBd2Xi7bjbPWi6ILj3DalanHKmvOMhnpGZX2jzZnDpXClzix3SVnHJGzLBWEo339vBa\n\tqSoq7mfGm93ipDaMW/3yO3x9nNEqywT7QJHeVbyglgQxIYQPhIoT8mDq/3yzOk5cXB0G\n\tX8qphqRKBCCDxUeem9F63h5OpkOqBiqy7KzD4KE5VPu80VE+ezdvCv9nnAy+VqlywuRF\n\tOLOhp9alHoCX5ciEIXGRNL7ToCxXBYiSfjDziWOgRm9dgRVzStrO9sn9cSP2E38Oywl/\n\t11zA==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=lauJTMVnvUbbgRaHR4hOjI8pwXek0yeu+kiFChNq/+M=;\n\tb=qDfYWYxeH912L82pwUFrPXaozfqjLh8MOv1TECpGPTjUWCE18B83oKNItYvjxt88T1\n\tu5OMuiTolvkjR+oXYcxXfKxR0PpGTCilei0VevuUYOD9A81DP5N/mEaqHwobPgbw7iOr\n\tJlCx4Pcm0LId0C4CQvGp7BvvY+UXe8jZcAJ4/oOnA2vaqbxqCL4XRpAXpy/ojIkb7GjJ\n\tjKUHFm8/zGyHONt5a6/LIFnF3/7tcZ0PmmTVvAIBH8heiOgdnepOKiiNbG1RGdTMwfqK\n\tO7+a8vXuB3ADKEOyQ8IbcnzrLyMmmeAWZHzN2YZr/duXn20e39jfDjeWKIwSJ9D2YtSD\n\t3TlQ==", "X-Gm-Message-State": "AHPjjUg3ldiRULnjpDjWgvQZhhbw6nDutduRmwF0nfLxGrq/PuGReDTf\n\tRz+OENsIcXnSSBxNHg8S+CM=", "X-Google-Smtp-Source": "AOwi7QCniPYDTAZOJ+rEay9VMEQYxmi9AV08uJ+/oUu868hwWCYHhk71Mzmi5Llsq7yhd9bndefUDQ==", "X-Received": "by 10.55.3.67 with SMTP id 64mr5806612qkd.307.1506592613630;\n\tThu, 28 Sep 2017 02:56:53 -0700 (PDT)", "From": "Thierry Reding <thierry.reding@gmail.com>", "To": "Linus Walleij <linus.walleij@linaro.org>", "Cc": "Jonathan Hunter <jonathanh@nvidia.com>, linux-gpio@vger.kernel.org,\n\tlinux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org", "Subject": "[PATCH v2 08/16] gpio: Move irq_nested into struct gpio_irq_chip", "Date": "Thu, 28 Sep 2017 11:56:20 +0200", "Message-Id": "<20170928095628.21966-9-thierry.reding@gmail.com>", "X-Mailer": "git-send-email 2.14.1", "In-Reply-To": "<20170928095628.21966-1-thierry.reding@gmail.com>", "References": "<20170928095628.21966-1-thierry.reding@gmail.com>", "Sender": "linux-gpio-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-gpio.vger.kernel.org>", "X-Mailing-List": "linux-gpio@vger.kernel.org" }, "content": "From: Thierry Reding <treding@nvidia.com>\n\nIn order to consolidate the multiple ways to associate an IRQ chip with\na GPIO chip, move more fields into the new struct gpio_irq_chip.\n\nSigned-off-by: Thierry Reding <treding@nvidia.com>\n---\n drivers/gpio/gpiolib.c | 12 ++++++------\n include/linux/gpio/driver.h | 9 +++++++--\n 2 files changed, 13 insertions(+), 8 deletions(-)", "diff": "diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c\nindex 7a62f4a63635..eaca1ccd2431 100644\n--- a/drivers/gpio/gpiolib.c\n+++ b/drivers/gpio/gpiolib.c\n@@ -1613,7 +1613,7 @@ void gpiochip_set_nested_irqchip(struct gpio_chip *gpiochip,\n \t\t\t\t struct irq_chip *irqchip,\n \t\t\t\t unsigned int parent_irq)\n {\n-\tif (!gpiochip->irq_nested) {\n+\tif (!gpiochip->irq.nested) {\n \t\tchip_err(gpiochip, \"tried to nest a chained gpiochip\\n\");\n \t\treturn;\n \t}\n@@ -1648,7 +1648,7 @@ int gpiochip_irq_map(struct irq_domain *d, unsigned int irq,\n \tirq_set_lockdep_class(irq, chip->lock_key);\n \tirq_set_chip_and_handler(irq, chip->irq.chip, chip->irq.handler);\n \t/* Chips that use nested thread handlers have them marked */\n-\tif (chip->irq_nested)\n+\tif (chip->irq.nested)\n \t\tirq_set_nested_thread(irq, 1);\n \tirq_set_noprobe(irq);\n \n@@ -1667,7 +1667,7 @@ void gpiochip_irq_unmap(struct irq_domain *d, unsigned int irq)\n {\n \tstruct gpio_chip *chip = d->host_data;\n \n-\tif (chip->irq_nested)\n+\tif (chip->irq.nested)\n \t\tirq_set_nested_thread(irq, 0);\n \tirq_set_chip_and_handler(irq, NULL, NULL);\n \tirq_set_chip_data(irq, NULL);\n@@ -1800,9 +1800,9 @@ static int gpiochip_add_irqchip(struct gpio_chip *gpiochip)\n \t\t\t\t\t\t\t data);\n \t\t}\n \n-\t\tgpiochip->irq_nested = false;\n+\t\tgpiochip->irq.nested = false;\n \t} else {\n-\t\tgpiochip->irq_nested = true;\n+\t\tgpiochip->irq.nested = true;\n \t}\n \n \t/*\n@@ -1919,7 +1919,7 @@ int gpiochip_irqchip_add_key(struct gpio_chip *gpiochip,\n \t\tpr_err(\"missing gpiochip .dev parent pointer\\n\");\n \t\treturn -EINVAL;\n \t}\n-\tgpiochip->irq_nested = nested;\n+\tgpiochip->irq.nested = nested;\n \tof_node = gpiochip->parent->of_node;\n #ifdef CONFIG_OF_GPIO\n \t/*\ndiff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h\nindex c3eafd874884..7d632a8932be 100644\n--- a/include/linux/gpio/driver.h\n+++ b/include/linux/gpio/driver.h\n@@ -107,6 +107,13 @@ struct gpio_irq_chip {\n \t * A list of interrupt parents for each line of a GPIO chip.\n \t */\n \tunsigned int *map;\n+\n+\t/**\n+\t * @nested:\n+\t *\n+\t * True if set the interrupt handling is nested.\n+\t */\n+\tbool nested;\n };\n \n static inline struct gpio_irq_chip *to_gpio_irq_chip(struct irq_chip *chip)\n@@ -176,7 +183,6 @@ static inline struct gpio_irq_chip *to_gpio_irq_chip(struct irq_chip *chip)\n *\tsafely.\n * @bgpio_dir: shadowed direction register for generic GPIO to clear/set\n *\tdirection safely.\n- * @irq_nested: True if set the interrupt handling is nested.\n * @irq_need_valid_mask: If set core allocates @irq_valid_mask with all\n *\tbits set to one\n * @irq_valid_mask: If not %NULL holds bitmask of GPIOs which are valid to\n@@ -248,7 +254,6 @@ struct gpio_chip {\n \t * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib\n \t * to handle IRQs for most practical cases.\n \t */\n-\tbool\t\t\tirq_nested;\n \tbool\t\t\tirq_need_valid_mask;\n \tunsigned long\t\t*irq_valid_mask;\n \tstruct lock_class_key\t*lock_key;\n", "prefixes": [ "v2", "08/16" ] }