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GET /api/patches/819489/?format=api
{ "id": 819489, "url": "http://patchwork.ozlabs.org/api/patches/819489/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20170928095628.21966-6-thierry.reding@gmail.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170928095628.21966-6-thierry.reding@gmail.com>", "list_archive_url": null, "date": "2017-09-28T09:56:17", "name": "[v2,05/16] gpio: Move irq_handler to struct gpio_irq_chip", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "8dbdc840e83bf1086c9e7f7d00f06335b3236b53", "submitter": { "id": 26234, "url": "http://patchwork.ozlabs.org/api/people/26234/?format=api", "name": "Thierry Reding", "email": "thierry.reding@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20170928095628.21966-6-thierry.reding@gmail.com/mbox/", "series": [ { "id": 5529, "url": "http://patchwork.ozlabs.org/api/series/5529/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=5529", "date": "2017-09-28T09:56:12", "name": "gpio: Tight IRQ chip integration and banked infrastructure", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/5529/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/819489/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/819489/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-gpio-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"LaSvYeVJ\"; dkim-atps=neutral" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2qpr5CSmz9t5l\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 28 Sep 2017 19:56:52 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752833AbdI1J4v (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tThu, 28 Sep 2017 05:56:51 -0400", "from mail-qk0-f194.google.com ([209.85.220.194]:33575 \"EHLO\n\tmail-qk0-f194.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752735AbdI1J4q (ORCPT\n\t<rfc822; linux-gpio@vger.kernel.org>); Thu, 28 Sep 2017 05:56:46 -0400", "by mail-qk0-f194.google.com with SMTP id g128so654237qke.0;\n\tThu, 28 Sep 2017 02:56:46 -0700 (PDT)", "from localhost\n\t(p200300E41BCC8100EA54DC343767CF80.dip0.t-ipconnect.de.\n\t[2003:e4:1bcc:8100:ea54:dc34:3767:cf80])\n\tby smtp.gmail.com with ESMTPSA id\n\td186sm726896qkg.46.2017.09.28.02.56.44\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tThu, 28 Sep 2017 02:56:45 -0700 (PDT)" ], "DKIM-Signature": "v=1; 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\n\tThu, 28 Sep 2017 02:56:45 -0700 (PDT)", "From": "Thierry Reding <thierry.reding@gmail.com>", "To": "Linus Walleij <linus.walleij@linaro.org>", "Cc": "Jonathan Hunter <jonathanh@nvidia.com>, linux-gpio@vger.kernel.org,\n\tlinux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org", "Subject": "[PATCH v2 05/16] gpio: Move irq_handler to struct gpio_irq_chip", "Date": "Thu, 28 Sep 2017 11:56:17 +0200", "Message-Id": "<20170928095628.21966-6-thierry.reding@gmail.com>", "X-Mailer": "git-send-email 2.14.1", "In-Reply-To": "<20170928095628.21966-1-thierry.reding@gmail.com>", "References": "<20170928095628.21966-1-thierry.reding@gmail.com>", "Sender": "linux-gpio-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-gpio.vger.kernel.org>", "X-Mailing-List": "linux-gpio@vger.kernel.org" }, "content": "From: Thierry Reding <treding@nvidia.com>\n\nIn order to consolidate the multiple ways to associate an IRQ chip with\na GPIO chip, move more fields into the new struct gpio_irq_chip.\n\nSigned-off-by: Thierry Reding <treding@nvidia.com>\n---\n drivers/gpio/gpiolib.c | 4 ++--\n include/linux/gpio/driver.h | 11 ++++++++---\n 2 files changed, 10 insertions(+), 5 deletions(-)", "diff": "diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c\nindex 2f0fa3d646d2..dc44f2c97498 100644\n--- a/drivers/gpio/gpiolib.c\n+++ b/drivers/gpio/gpiolib.c\n@@ -1645,7 +1645,7 @@ int gpiochip_irq_map(struct irq_domain *d, unsigned int irq,\n \t * category than their parents, so it won't report false recursion.\n \t */\n \tirq_set_lockdep_class(irq, chip->lock_key);\n-\tirq_set_chip_and_handler(irq, chip->irq.chip, chip->irq_handler);\n+\tirq_set_chip_and_handler(irq, chip->irq.chip, chip->irq.handler);\n \t/* Chips that use nested thread handlers have them marked */\n \tif (chip->irq_nested)\n \t\tirq_set_nested_thread(irq, 1);\n@@ -1949,7 +1949,7 @@ int gpiochip_irqchip_add_key(struct gpio_chip *gpiochip,\n \t}\n \n \tgpiochip->irq.chip = irqchip;\n-\tgpiochip->irq_handler = handler;\n+\tgpiochip->irq.handler = handler;\n \tgpiochip->irq_default_type = type;\n \tgpiochip->to_irq = gpiochip_to_irq;\n \tgpiochip->lock_key = lock_key;\ndiff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h\nindex 9389406df0b1..b1398ea0c32a 100644\n--- a/include/linux/gpio/driver.h\n+++ b/include/linux/gpio/driver.h\n@@ -54,6 +54,14 @@ struct gpio_irq_chip {\n \t */\n \tunsigned int first;\n \n+\t/**\n+\t * @handler:\n+\t *\n+\t * The IRQ handler to use (often a predefined IRQ core function) for\n+\t * GPIO IRQs, provided by GPIO driver.\n+\t */\n+\tirq_flow_handler_t handler;\n+\n \t/**\n \t * @parent_handler:\n \t *\n@@ -160,8 +168,6 @@ static inline struct gpio_irq_chip *to_gpio_irq_chip(struct irq_chip *chip)\n *\tsafely.\n * @bgpio_dir: shadowed direction register for generic GPIO to clear/set\n *\tdirection safely.\n- * @irq_handler: the irq handler to use (often a predefined irq core function)\n- *\tfor GPIO IRQs, provided by GPIO driver\n * @irq_default_type: default IRQ triggering type applied during GPIO driver\n *\tinitialization, provided by GPIO driver\n * @irq_chained_parent: GPIO IRQ chip parent/bank linux irq number,\n@@ -239,7 +245,6 @@ struct gpio_chip {\n \t * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib\n \t * to handle IRQs for most practical cases.\n \t */\n-\tirq_flow_handler_t\tirq_handler;\n \tunsigned int\t\tirq_default_type;\n \tunsigned int\t\tirq_chained_parent;\n \tbool\t\t\tirq_nested;\n", "prefixes": [ "v2", "05/16" ] }