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GET /api/patches/819250/?format=api
{ "id": 819250, "url": "http://patchwork.ozlabs.org/api/patches/819250/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1506533594-9741-2-git-send-email-chakra.divi@openedev.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1506533594-9741-2-git-send-email-chakra.divi@openedev.com>", "list_archive_url": null, "date": "2017-09-27T17:33:10", "name": "[U-Boot,v2,1/5] armv7: Move L2CTLR read/write to common", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "08aa035fe23fdf121fb075ec024d88e8510b6eb6", "submitter": { "id": 71741, "url": "http://patchwork.ozlabs.org/api/people/71741/?format=api", "name": "Chakra Divi", "email": "2chakrass@gmail.com" }, "delegate": { "id": 69486, "url": "http://patchwork.ozlabs.org/api/users/69486/?format=api", "username": "ptomsich", "first_name": "Philipp", "last_name": "Tomsich", "email": "philipp.tomsich@theobroma-systems.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1506533594-9741-2-git-send-email-chakra.divi@openedev.com/mbox/", "series": [ { "id": 5413, "url": "http://patchwork.ozlabs.org/api/series/5413/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=5413", "date": "2017-09-27T17:33:09", "name": "rk3288: Falcon mode support", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/5413/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/819250/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/819250/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"J5w4JKHg\"; dkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2Q8c567Hz9tY0\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 28 Sep 2017 03:40:48 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 62ED8C21D92; Wed, 27 Sep 2017 17:40:16 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 52795C21D9E;\n\tWed, 27 Sep 2017 17:40:10 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 6122FC21DD7; Wed, 27 Sep 2017 17:39:51 +0000 (UTC)", "from mail-pg0-f66.google.com (mail-pg0-f66.google.com\n\t[74.125.83.66])\n\tby lists.denx.de (Postfix) with ESMTPS id E739EC21DBB\n\tfor <u-boot@lists.denx.de>; Wed, 27 Sep 2017 17:39:46 +0000 (UTC)", "by mail-pg0-f66.google.com with SMTP id u136so96351pgc.0\n\tfor <u-boot@lists.denx.de>; Wed, 27 Sep 2017 10:39:46 -0700 (PDT)", "from localhost.localdomain ([115.97.184.62])\n\tby smtp.gmail.com with ESMTPSA id\n\tq7sm24609290pgn.56.2017.09.27.10.39.42\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128);\n\tWed, 27 Sep 2017 10:39:44 -0700 (PDT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.0 required=5.0 tests=FREEMAIL_FROM,\n\tRCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,\n\tT_DKIM_INVALID\n\tautolearn=unavailable autolearn_force=no version=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=cnYsaqmPTUHoSQYzwGc8JCYNAk3DR5qzdFMUR8VQhqQ=;\n\tb=J5w4JKHgngqSfVrZChVqjZzYFHmrLmrOqQK3ndiA0OEn/3KVxjHb9Tz5h1+btat1vf\n\tVxB5n74yPGlbOU/ppmO8HPbOnjC+y7OEHqztDPOFSucqg5ZbQVjvi73L8klhP5aU6HLu\n\twOJuKb8Gc2/mt4jZlCysktEnh14yj3EJXUfrLPu0LxhpsIk9EexQnLIavtIbqCNaedzZ\n\tjtEBqySO0I7qYHH4p0hruZeK4wracU2IXNg3pikp9E6OhYoPwPxmW+uMZ0zB26F1l6zr\n\txfrQeM4vOa4N8bXtpPTX0edAVyKLk66bHJPNcxmM/4hcgbJW6enzaeez4Ne/LMGzGGzJ\n\tFoMA==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=cnYsaqmPTUHoSQYzwGc8JCYNAk3DR5qzdFMUR8VQhqQ=;\n\tb=GDt2A8/9q8/YdjuxwdwpIsD616UL8QWrWkHOgmZmFZR+fSJYDDKxLgoggxO5v9pEpq\n\t2D7+dkh6pKymKm6qdzpZwcPHZ1A2XKveNPAU0Lp5kerqpHqT0CErOSpZ5hlSTDyy6kdk\n\t0CNQFWF3u7R6sN9HzEpckdTYMECuvzMR797rgBBovntCAgnNBGLiVV5MHUWFZB49RXi2\n\tpJrDLHbZQ0nifzQRsYkY0T5V3jDcd02+4aZTKCvu2M7T9MfCq7e9yVSl8CBp59TdP0lA\n\tr733lRxt4zXo0JzPm9StOkusmbwK3HstHQWegM2qvibWZF5CzxryAOYWS2ZefMi5paWz\n\tsJmg==", "X-Gm-Message-State": "AHPjjUjBMPtyucm93pGpzMUxqIueKEkBfOFudq2ttLzswPmmdIUgBIDZ\n\toq0Gnk3OWw6t5Ut85lQEMfY=", "X-Google-Smtp-Source": "AOwi7QD/70oXXippGvJd2ka35S9NzeQpccZtoj/z9l7nJhZ1IRzQAn66UpD2mXQo/M9yijjqN4xvtA==", "X-Received": "by 10.84.132.66 with SMTP id 60mr1862795ple.158.1506533985604;\n\tWed, 27 Sep 2017 10:39:45 -0700 (PDT)", "From": "Chakra Divi <2chakrass@gmail.com>", "X-Google-Original-From": "Chakra Divi <chakra.divi@openedev.com>", "To": "Philipp Tomsich <philipp.tomsich@theobroma-systems.com>", "Date": "Wed, 27 Sep 2017 23:03:10 +0530", "Message-Id": "<1506533594-9741-2-git-send-email-chakra.divi@openedev.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1506533594-9741-1-git-send-email-chakra.divi@openedev.com>", "References": "<1506533594-9741-1-git-send-email-chakra.divi@openedev.com>", "Cc": "u-boot@lists.denx.de, Tom Warren <twarren@nvidia.com>", "Subject": "[U-Boot] [PATCH v2 1/5] armv7: Move L2CTLR read/write to common", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "From: Jagan Teki <jagan@amarulasolutions.com>\n\nL2CTLR read/write functions are common to armv7 so, move\nthem in to include/asm/armv7.h and use them where ever it need.\n\nCc: Tom Warren <twarren@nvidia.com>\nSigned-off-by: Jagan Teki <jagan@amarulasolutions.com>\n---\nChanges for v2:\n- New patch\n\n arch/arm/include/asm/armv7.h | 21 +++++++++++++++++++++\n arch/arm/mach-rockchip/rk3288-board-spl.c | 22 +---------------------\n arch/arm/mach-tegra/cache.c | 5 +++--\n 3 files changed, 25 insertions(+), 23 deletions(-)", "diff": "diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h\nindex a20702e..efc515e 100644\n--- a/arch/arm/include/asm/armv7.h\n+++ b/arch/arm/include/asm/armv7.h\n@@ -61,6 +61,27 @@\n #include <asm/io.h>\n #include <asm/barriers.h>\n \n+/* read L2 control register (L2CTLR) */\n+static inline uint32_t read_l2ctlr(void)\n+{\n+\tuint32_t val = 0;\n+\n+\tasm volatile (\"mrc p15, 1, %0, c9, c0, 2\" : \"=r\" (val));\n+\n+\treturn val;\n+}\n+\n+/* write L2 control register (L2CTLR) */\n+static inline void write_l2ctlr(uint32_t val)\n+{\n+\t/*\n+\t * Note: L2CTLR can only be written when the L2 memory system\n+\t * is idle, ie before the MMU is enabled.\n+\t */\n+\tasm volatile(\"mcr p15, 1, %0, c9, c0, 2\" : : \"r\" (val) : \"memory\");\n+\tisb();\n+}\n+\n /*\n * Workaround for ARM errata # 798870\n * Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been\ndiff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c\nindex 6b7bf85..8a1066c 100644\n--- a/arch/arm/mach-rockchip/rk3288-board-spl.c\n+++ b/arch/arm/mach-rockchip/rk3288-board-spl.c\n@@ -13,6 +13,7 @@\n #include <malloc.h>\n #include <ram.h>\n #include <spl.h>\n+#include <asm/armv7.h>\n #include <asm/gpio.h>\n #include <asm/io.h>\n #include <asm/arch/bootrom.h>\n@@ -80,27 +81,6 @@ u32 spl_boot_mode(const u32 boot_device)\n \treturn MMCSD_MODE_RAW;\n }\n \n-/* read L2 control register (L2CTLR) */\n-static inline uint32_t read_l2ctlr(void)\n-{\n-\tuint32_t val = 0;\n-\n-\tasm volatile (\"mrc p15, 1, %0, c9, c0, 2\" : \"=r\" (val));\n-\n-\treturn val;\n-}\n-\n-/* write L2 control register (L2CTLR) */\n-static inline void write_l2ctlr(uint32_t val)\n-{\n-\t/*\n-\t * Note: L2CTLR can only be written when the L2 memory system\n-\t * is idle, ie before the MMU is enabled.\n-\t */\n-\tasm volatile(\"mcr p15, 1, %0, c9, c0, 2\" : : \"r\" (val) : \"memory\");\n-\tisb();\n-}\n-\n static void configure_l2ctlr(void)\n {\n \tuint32_t l2ctlr;\ndiff --git a/arch/arm/mach-tegra/cache.c b/arch/arm/mach-tegra/cache.c\nindex 6dad403..2f3f822 100644\n--- a/arch/arm/mach-tegra/cache.c\n+++ b/arch/arm/mach-tegra/cache.c\n@@ -7,6 +7,7 @@\n /* Tegra cache routines */\n \n #include <common.h>\n+#include <asm/armv7.h>\n #include <asm/io.h>\n #include <asm/arch-tegra/ap.h>\n #include <asm/arch/gp_padctrl.h>\n@@ -30,9 +31,9 @@ void config_cache(void)\n \t * Systems with an architectural L2 cache must not use the PL310.\n \t * Config L2CTLR here for a data RAM latency of 3 cycles.\n \t */\n-\tasm(\"mrc p15, 1, %0, c9, c0, 2\" : : \"r\" (reg));\n+\treg = read_l2ctlr();\n \treg &= ~7;\n \treg |= 2;\n-\tasm(\"mcr p15, 1, %0, c9, c0, 2\" : : \"r\" (reg));\n+\twrite_l2ctlr(reg);\n }\n #endif\n", "prefixes": [ "U-Boot", "v2", "1/5" ] }