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GET /api/patches/819164/?format=api
{ "id": 819164, "url": "http://patchwork.ozlabs.org/api/patches/819164/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1506519893-16509-5-git-send-email-patrice.chotard@st.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1506519893-16509-5-git-send-email-patrice.chotard@st.com>", "list_archive_url": null, "date": "2017-09-27T13:44:51", "name": "[U-Boot,v1,4/6] serial: stm32x7: add fifo support for STM32H7", "commit_ref": "2a7ecc536019066f77ff7b6e24cb3194ee0f65c0", "pull_url": null, "state": "accepted", "archived": false, "hash": "2eaff8afdabc2df233ae48b3cb2374a3e95cd6e4", "submitter": { "id": 63958, "url": "http://patchwork.ozlabs.org/api/people/63958/?format=api", "name": "Patrice CHOTARD", "email": "patrice.chotard@st.com" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1506519893-16509-5-git-send-email-patrice.chotard@st.com/mbox/", "series": [ { "id": 5372, "url": "http://patchwork.ozlabs.org/api/series/5372/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=5372", "date": "2017-09-27T13:44:48", "name": "Update stm32x7 serial driver", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/5372/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/819164/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/819164/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2Jxt1CY2z9sRm\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 27 Sep 2017 23:46:10 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid D1716C21D74; Wed, 27 Sep 2017 13:45:26 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 8D1C1C21D78;\n\tWed, 27 Sep 2017 13:45:07 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 1D05DC21C46; Wed, 27 Sep 2017 13:45:05 +0000 (UTC)", "from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com\n\t[62.209.51.94]) by lists.denx.de (Postfix) with ESMTPS id CA992C21C45\n\tfor <u-boot@lists.denx.de>; Wed, 27 Sep 2017 13:45:04 +0000 (UTC)", "from pps.filterd (m0046668.ppops.net [127.0.0.1])\n\tby mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv8RDiK8R021246; Wed, 27 Sep 2017 15:45:03 +0200", "from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35])\n\tby mx07-00178001.pphosted.com with ESMTP id 2d8b4n0x4s-1\n\t(version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT);\n\tWed, 27 Sep 2017 15:45:03 +0200", "from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9])\n\tby beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 0F1C531;\n\tWed, 27 Sep 2017 13:45:03 +0000 (GMT)", "from Webmail-eu.st.com (sfhdag6node3.st.com [10.75.127.18])\n\tby zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id D24E328F4;\n\tWed, 27 Sep 2017 13:45:02 +0000 (GMT)", "from localhost (10.75.127.48) by SFHDAG6NODE3.st.com (10.75.127.18)\n\twith Microsoft SMTP Server (TLS) id 15.0.1178.4;\n\tWed, 27 Sep 2017 15:45:02 +0200" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW\n\tautolearn=unavailable autolearn_force=no version=3.4.0", "From": "<patrice.chotard@st.com>", "To": "<u-boot@lists.denx.de>, <albert.u.boot@aribaud.net>, <sjg@chromium.org>, \n\t<vikas.manocha@st.com>", "Date": "Wed, 27 Sep 2017 15:44:51 +0200", "Message-ID": "<1506519893-16509-5-git-send-email-patrice.chotard@st.com>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1506519893-16509-1-git-send-email-patrice.chotard@st.com>", "References": "<1506519893-16509-1-git-send-email-patrice.chotard@st.com>", "MIME-Version": "1.0", "X-Originating-IP": "[10.75.127.48]", "X-ClientProxiedBy": "SFHDAG5NODE2.st.com (10.75.127.14) To SFHDAG6NODE3.st.com\n\t(10.75.127.18)", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-09-27_03:, , signatures=0", "Subject": "[U-Boot] [PATCH v1 4/6] serial: stm32x7: add fifo support for\n\tSTM32H7", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "From: Patrice Chotard <patrice.chotard@st.com>\n\nAdd fifo mode support for rx and tx.\nAs only STM32H7 supports this feature, add has_fifo flag\nto uart configuration to use fifo only when possible.\n\nSigned-off-by: Patrice Chotard <patrice.chotard@st.com>\n---\n drivers/serial/serial_stm32x7.c | 6 ++++--\n drivers/serial/serial_stm32x7.h | 12 +++++++++++-\n 2 files changed, 15 insertions(+), 3 deletions(-)", "diff": "diff --git a/drivers/serial/serial_stm32x7.c b/drivers/serial/serial_stm32x7.c\nindex 81a2308..19697e3 100644\n--- a/drivers/serial/serial_stm32x7.c\n+++ b/drivers/serial/serial_stm32x7.c\n@@ -117,6 +117,8 @@ static int stm32_serial_probe(struct udevice *dev)\n \t\t BIT(uart_enable_bit));\n \tif (plat->uart_info->has_overrun_disable)\n \t\tsetbits_le32(base + CR3_OFFSET(stm32f4), USART_CR3_OVRDIS);\n+\tif (plat->uart_info->has_fifo)\n+\t\tsetbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_FIFOEN);\n \tsetbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |\n \t\t BIT(uart_enable_bit));\n \n@@ -125,8 +127,8 @@ static int stm32_serial_probe(struct udevice *dev)\n \n #if CONFIG_IS_ENABLED(OF_CONTROL)\n static const struct udevice_id stm32_serial_id[] = {\n-\t{ .compatible = \"st,stm32f7-uart\", .data = (ulong)&stm32x7_info},\n-\t{ .compatible = \"st,stm32h7-uart\", .data = (ulong)&stm32x7_info},\n+\t{ .compatible = \"st,stm32f7-uart\", .data = (ulong)&stm32f7_info},\n+\t{ .compatible = \"st,stm32h7-uart\", .data = (ulong)&stm32h7_info},\n \t{}\n };\n \ndiff --git a/drivers/serial/serial_stm32x7.h b/drivers/serial/serial_stm32x7.h\nindex 4c6b7d4..ed8a3ee 100644\n--- a/drivers/serial/serial_stm32x7.h\n+++ b/drivers/serial/serial_stm32x7.h\n@@ -24,12 +24,21 @@ struct stm32_uart_info {\n \tu8 uart_enable_bit;\t/* UART_CR1_UE */\n \tbool stm32f4;\t\t/* true for STM32F4, false otherwise */\n \tbool has_overrun_disable;\n+\tbool has_fifo;\n };\n \n-struct stm32_uart_info stm32x7_info = {\n+struct stm32_uart_info stm32f7_info = {\n \t.uart_enable_bit = 0,\n \t.stm32f4 = false,\n \t.has_overrun_disable = true,\n+\t.has_fifo = false,\n+};\n+\n+struct stm32_uart_info stm32h7_info = {\n+\t.uart_enable_bit = 0,\n+\t.stm32f4 = false,\n+\t.has_overrun_disable = true,\n+\t.has_fifo = true,\n };\n \n /* Information about a serial port */\n@@ -39,6 +48,7 @@ struct stm32x7_serial_platdata {\n \tunsigned long int clock_rate;\n };\n \n+#define USART_CR1_FIFOEN\t\tBIT(29)\n #define USART_CR1_OVER8\t\t\tBIT(15)\n #define USART_CR1_TE\t\t\tBIT(3)\n #define USART_CR1_RE\t\t\tBIT(2)\n", "prefixes": [ "U-Boot", "v1", "4/6" ] }