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{
    "id": 819125,
    "url": "http://patchwork.ozlabs.org/api/patches/819125/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1506515969-1472-2-git-send-email-kever.yang@rock-chips.com/",
    "project": {
        "id": 18,
        "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api",
        "name": "U-Boot",
        "link_name": "uboot",
        "list_id": "u-boot.lists.denx.de",
        "list_email": "u-boot@lists.denx.de",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<1506515969-1472-2-git-send-email-kever.yang@rock-chips.com>",
    "list_archive_url": null,
    "date": "2017-09-27T12:39:22",
    "name": "[U-Boot,1/8] rockchip: rk3128: add device tree file",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": false,
    "hash": "7a79309e1aa62689b6181e6a9d5f24bb6985e34d",
    "submitter": {
        "id": 64532,
        "url": "http://patchwork.ozlabs.org/api/people/64532/?format=api",
        "name": "Kever Yang",
        "email": "kever.yang@rock-chips.com"
    },
    "delegate": {
        "id": 69486,
        "url": "http://patchwork.ozlabs.org/api/users/69486/?format=api",
        "username": "ptomsich",
        "first_name": "Philipp",
        "last_name": "Tomsich",
        "email": "philipp.tomsich@theobroma-systems.com"
    },
    "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1506515969-1472-2-git-send-email-kever.yang@rock-chips.com/mbox/",
    "series": [
        {
            "id": 5353,
            "url": "http://patchwork.ozlabs.org/api/series/5353/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=5353",
            "date": "2017-09-27T12:39:21",
            "name": "rockchip: add new SoC support for RK3128",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/5353/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/819125/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/819125/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Kever Yang <kever.yang@rock-chips.com>",
        "To": "u-boot@lists.denx.de",
        "Date": "Wed, 27 Sep 2017 20:39:22 +0800",
        "Message-Id": "<1506515969-1472-2-git-send-email-kever.yang@rock-chips.com>",
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        "References": "<1506515969-1472-1-git-send-email-kever.yang@rock-chips.com>",
        "Cc": "Jernej Skrabec <jernej.skrabec@siol.net>, Stefan Roese <sr@denx.de>,\n\tMaxime Ripard <maxime.ripard@free-electrons.com>",
        "Subject": "[U-Boot] [PATCH 1/8] rockchip: rk3128: add device tree file",
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    },
    "content": "Add dts binding header for rk3128, files origin from kernel.\n\nSigned-off-by: Kever Yang <kever.yang@rock-chips.com>\n---\n\n arch/arm/dts/Makefile                  |   1 +\n arch/arm/dts/rk3128-evb.dts            |  77 ++++\n arch/arm/dts/rk3128.dtsi               | 756 +++++++++++++++++++++++++++++++++\n include/dt-bindings/clock/rk3128-cru.h | 187 ++++++++\n 4 files changed, 1021 insertions(+)\n create mode 100644 arch/arm/dts/rk3128-evb.dts\n create mode 100644 arch/arm/dts/rk3128.dtsi\n create mode 100644 include/dt-bindings/clock/rk3128-cru.h",
    "diff": "diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile\nindex 762429c..9fc8127 100644\n--- a/arch/arm/dts/Makefile\n+++ b/arch/arm/dts/Makefile\n@@ -29,6 +29,7 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \\\n dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb\n dtb-$(CONFIG_ARCH_ROCKCHIP) += \\\n \trk3036-sdk.dtb \\\n+\trk3128-evb.dtb \\\n \trk3188-radxarock.dtb \\\n \trk3288-evb.dtb \\\n \trk3288-fennec.dtb \\\ndiff --git a/arch/arm/dts/rk3128-evb.dts b/arch/arm/dts/rk3128-evb.dts\nnew file mode 100644\nindex 0000000..5ef51c9\n--- /dev/null\n+++ b/arch/arm/dts/rk3128-evb.dts\n@@ -0,0 +1,77 @@\n+/*\n+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd\n+ *\n+ * SPDX-License-Identifier:     GPL-2.0+\n+ */\n+\n+/dts-v1/;\n+\n+#include \"rk3128.dtsi\"\n+\n+/ {\n+\tmodel = \"Rockchip RK3128 Evaluation board\";\n+\tcompatible = \"rockchip,rk3128-evb\", \"rockchip,rk3128\";\n+\n+\tchosen {\n+\t\tstdout-path = &uart2;\n+\t};\n+\n+\tvcc5v0_otg: vcc5v0-otg-drv {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"vcc5v0_otg\";\n+\t\tgpio = <&gpio0 26 GPIO_ACTIVE_HIGH>;\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&otg_vbus_drv>;\n+\t\tregulator-min-microvolt = <5000000>;\n+\t\tregulator-max-microvolt = <5000000>;\n+\t};\n+\n+\tvcc5v0_host: vcc5v0-host-drv {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"vcc5v0_host\";\n+\t\tgpio = <&gpio2 23 GPIO_ACTIVE_HIGH>;\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&host_vbus_drv>;\n+\t\tregulator-min-microvolt = <5000000>;\n+\t\tregulator-max-microvolt = <5000000>;\n+\t\tregulator-always-on;\n+\t};\n+};\n+\n+&i2c1 {\n+\tstatus = \"okay\";\n+\n+        hym8563: hym8563@51 {\n+\t\tcompatible = \"haoyu,hym8563\";\n+\t\treg = <0x51>;\n+\t\t#clock-cells = <0>;\n+\t\tclock-frequency = <32768>;\n+\t\tclock-output-names = \"xin32k\";\n+\t};\n+};\n+\n+&usb_host {\n+\tstatus = \"okay\";\n+};\n+\n+&usb_otg {\n+\tstatus = \"okay\";\n+};\n+\n+&emmc {\n+\tstatus = \"okay\";\n+};\n+\n+&pinctrl {\n+\tusb_otg {\n+\t\totg_vbus_drv: host-vbus-drv {\n+\t\t\trockchip,pins = <0 26 RK_FUNC_GPIO &pcfg_pull_none>;\n+\t\t};\n+\t};\n+\n+\tusb_host {\n+\t\thost_vbus_drv: host-vbus-drv {\n+\t\t\trockchip,pins = <2 23 RK_FUNC_GPIO &pcfg_pull_none>;\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/dts/rk3128.dtsi b/arch/arm/dts/rk3128.dtsi\nnew file mode 100644\nindex 0000000..e7710b7\n--- /dev/null\n+++ b/arch/arm/dts/rk3128.dtsi\n@@ -0,0 +1,756 @@\n+/*\n+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd\n+ *\n+ * SPDX-License-Identifier:     GPL-2.0+\n+ */\n+\n+#include <dt-bindings/gpio/gpio.h>\n+#include <dt-bindings/interrupt-controller/irq.h>\n+#include <dt-bindings/interrupt-controller/arm-gic.h>\n+#include <dt-bindings/pinctrl/rockchip.h>\n+#include <dt-bindings/clock/rk3128-cru.h>\n+#include \"skeleton.dtsi\"\n+\n+/ {\n+\tcompatible = \"rockchip,rk3128\";\n+\trockchip,sram = <&sram>;\n+\tinterrupt-parent = <&gic>;\n+\t#address-cells = <1>;\n+\t#size-cells = <1>;\n+\n+\taliases {\n+\t\tgpio0 = &gpio0;\n+\t\tgpio1 = &gpio1;\n+\t\tgpio2 = &gpio2;\n+\t\tgpio3 = &gpio3;\n+\t\ti2c0 = &i2c0;\n+\t\ti2c1 = &i2c1;\n+\t\ti2c2 = &i2c2;\n+\t\ti2c3 = &i2c3;\n+\t\tspi0 = &spi0;\n+\t\tserial0 = &uart0;\n+\t\tserial1 = &uart1;\n+\t\tserial2 = &uart2;\n+\t\tmmc0 = &emmc;\n+\t\tmmc1 = &sdmmc;\n+\t};\n+\n+\tmemory {\n+\t\tdevice_type = \"memory\";\n+\t\treg = <0x60000000 0x40000000>;\n+\t};\n+\n+        arm-pmu {\n+                compatible = \"arm,cortex-a7-pmu\";\n+                interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,\n+                             <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;\n+        };\n+\n+\tcpus {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tenable-method = \"rockchip,rk3128-smp\";\n+\n+\t\tcpu0:cpu@0x000 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"arm,cortex-a7\";\n+\t\t\treg = <0x000>;\n+\t\t\toperating-points = <\n+\t\t\t\t/* KHz    uV */\n+\t\t\t\t 816000 1000000\n+\t\t\t>;\n+\t\t\t#cooling-cells = <2>; /* min followed by max */\n+\t\t\tclock-latency = <40000>;\n+\t\t\tclocks = <&cru ARMCLK>;\n+\t\t};\n+\n+\t\tcpu1:cpu@0x001 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"arm,cortex-a7\";\n+\t\t\treg = <0x001>;\n+\t\t};\n+\n+\t\tcpu2:cpu@0x002 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"arm,cortex-a7\";\n+\t\t\treg = <0x002>;\n+\t\t};\n+\n+\t\tcpu3:cpu@0x003 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"arm,cortex-a7\";\n+\t\t\treg = <0x003>;\n+\t\t};\n+\t};\n+\n+\tcpu_axi_bus: cpu_axi_bus {\n+\t\tcompatible = \"rockchip,cpu_axi_bus\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tranges;\n+\n+\t\tqos {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\t\t\tranges;\n+\n+\t\t\tcrypto {\n+\t\t\t\treg = <0x10128080 0x20>;\n+\t\t\t};\n+\n+\t\t\tcore {\n+\t\t\t\treg = <0x1012a000 0x20>;\n+\t\t\t};\n+\n+\t\t\tperi {\n+\t\t\t\treg = <0x1012c000 0x20>;\n+\t\t\t};\n+\n+\t\t\tgpu {\n+\t\t\t\treg = <0x1012d000 0x20>;\n+\t\t\t};\n+\n+\t\t\tvpu {\n+\t\t\t\treg = <0x1012e000 0x20>;\n+\t\t\t};\n+\n+\t\t\trga {\n+\t\t\t\treg = <0x1012f000 0x20>;\n+\t\t\t};\n+\t\t\tebc {\n+\t\t\t\treg = <0x1012f080 0x20>;\n+\t\t\t};\n+\n+\t\t\tiep {\n+\t\t\t\treg = <0x1012f100 0x20>;\n+\t\t\t};\n+\n+\t\t\tlcdc {\n+\t\t\t\treg = <0x1012f180 0x20>;\n+\t\t\t\trockchip,priority = <3 3>;\n+\t\t\t};\n+\n+\t\t\tvip {\n+\t\t\t\treg = <0x1012f200 0x20>;\n+\t\t\t\trockchip,priority = <3 3>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tmsch {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\t\t\tranges;\n+\n+\t\t\tmsch@10128000 {\n+\t\t\t\treg = <0x10128000 0x20>;\n+\t\t\t\trockchip,read-latency = <0x3f>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tpsci {\n+\t\tcompatible      = \"arm,psci\";\n+\t\tmethod          = \"smc\";\n+\t\tcpu_suspend     = <0x84000001>;\n+\t\tcpu_off         = <0x84000002>;\n+\t\tcpu_on          = <0x84000003>;\n+\t\tmigrate         = <0x84000005>;\n+\t};\n+\n+\tamba {\n+\t\tcompatible = \"arm,amba-bus\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tinterrupt-parent = <&gic>;\n+\t\tranges;\n+\n+                pdma: pdma@20078000 {\n+                        compatible = \"arm,pl330\", \"arm,primecell\";\n+                        reg = <0x20078000 0x4000>;\n+                        arm,pl330-broken-no-flushp;//2\n+                        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,\n+                                     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;\n+                        #dma-cells = <1>;\n+                        clocks = <&cru ACLK_DMAC2>;\n+                        clock-names = \"apb_pclk\";\n+                };\n+\t};\n+\n+\txin24m: xin24m {\n+\t\tcompatible = \"fixed-clock\";\n+\t\tclock-frequency = <24000000>;\n+\t\tclock-output-names = \"xin24m\";\n+\t\t#clock-cells = <0>;\n+\t};\n+\n+\txin12m: xin12m {\n+\t\tcompatible = \"fixed-clock\";\n+\t\tclocks = <&xin24m>;\n+\t\tclock-frequency = <12000000>;\n+\t\tclock-output-names = \"xin12m\";\n+\t\t#clock-cells = <0>;\n+\t};\n+\n+\n+\ttimer {\n+\t\tcompatible = \"arm,armv7-timer\";\n+\t\tarm,cpu-registers-not-fw-configured;\n+\t\tinterrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,\n+\t\t\t     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;\n+\t\tclock-frequency = <24000000>;\n+\t};\n+\n+\ttimer@20044000 {\n+\t\tcompatible = \"arm,armv7-timer\";\n+\t\treg = <0x20044000 0xb8>;\n+\t\tinterrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;\n+\t\trockchip,broadcast = <1>;\n+\t};\n+\n+\twatchdog: wdt@2004c000 {\n+\t\tcompatible = \"rockchip,watch dog\";\n+\t\treg = <0x2004c000 0x100>;\n+\t\tclock-names = \"pclk_wdt\";\n+\t\tinterrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;\n+\t\trockchip,irq = <1>;\n+\t\trockchip,timeout = <60>;\n+\t\trockchip,atboot = <1>;\n+\t\trockchip,debug = <0>;\n+\t};\n+\n+\treset: reset@20000110 {\n+\t\tcompatible = \"rockchip,reset\";\n+\t\treg = <0x20000110 0x24>;\n+\t\t#reset-cells = <1>;\n+\t};\n+\n+\tnandc: nandc@10500000 {\n+\t\tcompatible = \"rockchip,rk-nandc\";\n+\t\treg = <0x10500000 0x4000>;\n+\t\tinterrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&nandc_ale &nandc_cle &nandc_wrn &nandc_rdn &nandc_rdy &nandc_cs0 &nandc_data>;\n+\t\tnandc_id = <0>;\n+\t\tclocks = <&cru SCLK_NANDC>,\n+\t\t\t <&cru HCLK_NANDC>,\n+\t\t\t <&cru SRST_NANDC>;\n+\t\tclock-names = \"clk_nandc\", \"g_clk_nandc\", \"hclk_nandc\";\n+\t};\n+\n+\tdmc: dmc@20004000 {\n+\t\tu-boot,dm-pre-reloc;\n+\t\tcompatible = \"rockchip,rk3128-dmc\", \"syscon\";\n+\t\treg = <0x0 0x20004000 0x0 0x1000>;\n+\t};\n+\n+\tcru: clock-controller@20000000 {\n+\t\tu-boot,dm-pre-reloc;\n+\t\tcompatible = \"rockchip,rk3128-cru\";\n+\t\treg = <0x20000000 0x1000>;\n+\t\trockchip,grf = <&grf>;\n+\t\t#clock-cells = <1>;\n+\t\t#reset-cells = <1>;\n+\t\tassigned-clocks = <&cru PLL_GPLL>;\n+\t\tassigned-clock-rates = <594000000>;\n+\t};\n+\n+\tuart0: serial0@20060000 {\n+\t\tcompatible = \"rockchip,rk3128-uart\", \"snps,dw-apb-uart\";\n+\t\treg = <0x20060000 0x100>;\n+\t\tinterrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;\n+\t\treg-shift = <2>;\n+\t\treg-io-width = <4>;\n+\t\tclock-frequency = <24000000>;\n+\t\tclocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;\n+\t\tclock-names = \"baudclk\", \"apb_pclk\";\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;\n+\t\tdmas = <&pdma 2>, <&pdma 3>;\n+\t\t#dma-cells = <2>;\n+\t};\n+\n+\tuart1: serial1@20064000 {\n+\t\tcompatible = \"rockchip,rk3128-uart\", \"snps,dw-apb-uart\";\n+\t\treg = <0x20064000 0x100>;\n+\t\tinterrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;\n+\t\treg-shift = <2>;\n+\t\treg-io-width = <4>;\n+\t\tclock-frequency = <24000000>;\n+\t\tclocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;\n+\t\tclock-names = \"baudclk\", \"apb_pclk\";\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&uart1_xfer>;\n+\t\tdmas = <&pdma 4>, <&pdma 5>;\n+\t\t#dma-cells = <2>;\n+\t};\n+\n+\tuart2: serial2@20068000 {\n+\t\tcompatible = \"rockchip,rk3128-uart\", \"snps,dw-apb-uart\";\n+\t\treg = <0x20068000 0x100>;\n+\t\tinterrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;\n+\t\treg-shift = <2>;\n+\t\treg-io-width = <4>;\n+\t\tclock-frequency = <24000000>;\n+\t\tclocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;\n+\t\tclock-names = \"baudclk\", \"apb_pclk\";\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&uart2_xfer>;\n+\t\tdmas = <&pdma 6>, <&pdma 7>;\n+\t\t#dma-cells = <2>;\n+\t};\n+\n+\tpwm0: pwm0@20050000 {\n+\t\tcompatible = \"rockchip,rk3128-pwm\", \"rockchip,rk3288-pwm\";\n+\t\treg = <0x20050000 0x10>;\n+\t\t#pwm-cells = <2>;\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&pwm0_pin>;\n+\t\tclocks = <&cru PCLK_PWM>;\n+\t\tclock-names = \"pwm\";\n+\t};\n+\n+\tpwm1: pwm1@20050010 {\n+\t\tcompatible = \"rockchip,rk3128-pwm\", \"rockchip,rk3288-pwm\";\n+\t\treg = <0x20050010 0x10>;\n+\t\t#pwm-cells = <2>;\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&pwm1_pin>;\n+\t\tclocks = <&cru PCLK_PWM>;\n+\t\tclock-names = \"pwm\";\n+\t};\n+\n+\tpwm2: pwm2@20050020 {\n+\t\tcompatible = \"rockchip,rk3128-pwm\", \"rockchip,rk3288-pwm\";\n+\t\treg = <0x20050020 0x10>;\n+\t\t#pwm-cells = <2>;\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&pwm2_pin>;\n+\t\tclocks = <&cru PCLK_PWM>;\n+\t\tclock-names = \"pwm\";\n+\t};\n+\n+\tpwm3: pwm3@20050030 {\n+\t\tcompatible = \"rockchip,rk3128-pwm\", \"rockchip,rk3288-pwm\";\n+\t\treg = <0x20050030 0x10>;\n+\t\t#pwm-cells = <2>;\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&pwm3_pin>;\n+\t\tclocks = <&cru PCLK_PWM>;\n+\t\tclock-names = \"pwm\";\n+\t};\n+\n+\tsram: sram@10080400 {\n+\t\tcompatible = \"rockchip,rk3128-smp-sram\", \"mmio-sram\";\n+\t\treg = <0x10080400 0x1C00>;\n+\t\tmap-exec;\n+\t\tmap-cacheable;\n+\t};\n+\n+\tpmu: syscon@100a0000 {\n+\t\tcompatible = \"rockchip,rk3128-pmu\", \"syscon\", \"simple-mfd\";\n+\t\treg = <0x100a0000 0x1000>;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t};\n+\n+\tgic: interrupt-controller@10139000 {\n+\t\tcompatible = \"arm,gic-400\";\n+\t\tinterrupt-controller;\n+\t\t#interrupt-cells = <3>;\n+\t\t#address-cells = <0>;\n+\t\treg = <0x10139000 0x1000>,\n+\t\t      <0x1013a000 0x1000>,\n+\t\t      <0x1013c000 0x2000>,\n+\t\t      <0x1013e000 0x2000>;\n+\t\tinterrupts = <GIC_PPI 9 0xf04>;\n+\t};\n+\n+\tusb_otg: usb@10180000 {\n+\t\tcompatible = \"rockchip,rk3288-usb\", \"rockchip,rk3066-usb\", \"snps,dwc2\";\n+\t\treg = <0x10180000 0x40000>;\n+\t\tinterrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;\n+\t\tclocks = <&cru HCLK_OTG0>;\n+\t\tclock-names = \"otg\";\n+\t\tdr_mode = \"otg\";\n+\t\tg-np-tx-fifo-size = <16>;\n+\t\tg-rx-fifo-size = <275>;\n+\t\tg-tx-fifo-size = <256 128 128 64 64 32>;\n+\t\tg-use-dma;\n+\t};\n+\n+\tusb_host: usb@101c0000 {\n+\t\tcompatible = \"rockchip,rk3288-usb\", \"rockchip,rk3066-usb\",\n+\t\t\t\t\"snps,dwc2\";\n+\t\treg = <0x101c0000 0x40000>;\n+\t\tinterrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;\n+\t\tclocks = <&cru HCLK_OTG1>;\n+\t\tclock-names = \"otg\";\n+\t\tdr_mode = \"host\";\n+\t};\n+\n+\tsdmmc: dwmmc@10214000 {\n+\t\tcompatible = \"rockchip,rk312x-dw-mshc\", \"rockchip,rk3288-dw-mshc\";\n+\t\treg = <0x10214000 0x4000>;\n+\t\tmax-frequency = <150000000>;\n+\t\tinterrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;\n+\t\tclocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,\n+\t\t\t <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;\n+\t\tclock-names = \"biu\", \"ciu\", \"ciu_drv\", \"ciu_sample\";\n+\t\tfifo-depth = <0x100>;\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;\n+\t\tbus-width = <4>;\n+\t\tstatus = \"disabled\";\n+\t};\n+\n+\temmc: dwmmc@1021c000 {\n+\t\tcompatible = \"rockchip,rk3128-dw-mshc\", \"rockchip,rk3288-dw-mshc\";\n+\t\treg = <0x1021c000 0x4000>;\n+\t\tmax-frequency = <150000000>;\n+\t\tinterrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;\n+\t\tclocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,\n+\t\t\t <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;\n+\t\tclock-names = \"biu\", \"ciu\", \"ciu_drv\", \"ciu_sample\";\n+\t\tbus-width = <8>;\n+\t\tdefault-sample-phase = <158>;\n+\t\tnum-slots = <1>;\n+\t\tfifo-depth = <0x100>;\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;\n+\t\tresets = <&cru SRST_EMMC>;\n+\t\treset-names = \"reset\";\n+\t\tstatus = \"disabled\";\n+\t};\n+\n+\ti2c0: i2c0@20070000 {\n+\t\tcompatible = \"rockchip,rk3128-i2c\", \"rockchip,rk3288-i2c\";\n+\t\treg = <0x20070000 0x1000>;\n+\t\tinterrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tclock-names = \"i2c\";\n+\t\tclocks = <&cru PCLK_I2C0>;\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&i2c0_xfer>;\n+\t};\n+\n+\ti2c1: i2c1@20054000 {\n+\t\tcompatible = \"rockchip,rk3128-i2c\", \"rockchip,rk3288-i2c\";\n+\t\treg = <0x20054000 0x1000>;\n+\t\tinterrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tclock-names = \"i2c\";\n+\t\tclocks = <&cru PCLK_I2C1>;\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&i2c1_xfer>;\n+\t};\n+\n+\ti2c2: i2c2@20058000 {\n+\t\tcompatible = \"rockchip,rk3128-i2c\", \"rockchip,rk3288-i2c\";\n+\t\treg = <0x20058000 0x1000>;\n+\t\tinterrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tclock-names = \"i2c\";\n+\t\tclocks = <&cru PCLK_I2C2>;\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&i2c0_xfer>;\n+\t};\n+\n+\ti2c3: i2c3@2005c000 {\n+\t\tcompatible = \"rockchip,rk3128-i2c\", \"rockchip,rk3288-i2c\";\n+\t\treg = <0x2005c000 0x1000>;\n+\t\tinterrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tclock-names = \"i2c\";\n+\t\tclocks = <&cru PCLK_I2C3>;\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&i2c0_xfer>;\n+\t};\n+\n+\tspi0: spi@20074000 {\n+\t\tcompatible = \"rockchip,rk3128-spi\", \"rockchip,rk3288-spi\";\n+\t\treg = <0x20074000 0x1000>;\n+\t\tinterrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&spi0_txd_mux0 &spi0_rxd_mux0 &spi0_clk_mux0 &spi0_cs0_mux0 &spi0_cs1_mux0>;\n+\t\trockchip,spi-src-clk = <0>;\n+\t\tnum-cs = <2>;\n+\t\tclocks =<&cru SCLK_SPI>, <&cru PCLK_SPI>;\n+\t\tclock-names = \"spi\",\"pclk_spi0\";\n+\t\tdmas = <&pdma 8>, <&pdma 9>;\n+\t\t#dma-cells = <2>;\n+\t\tdma-names = \"tx\", \"rx\";\n+\t};\n+\n+\tgrf: syscon@20008000 {\n+\t\tu-boot,dm-pre-reloc;\n+\t\tcompatible = \"rockchip,rk3128-grf\", \"syscon\";\n+\t\treg = <0x20008000 0x1000>;\n+\t};\n+\n+\tpinctrl: pinctrl@20008000 {\n+\t\tcompatible = \"rockchip,rk3128-pinctrl\";\n+\t\treg = <0x20008000 0xA8>,\n+\t\t      <0x200080A8 0x4C>,\n+\t\t      <0x20008118 0x20>,\n+\t\t      <0x20008100 0x04>;\n+\t\treg-names = \"base\", \"mux\", \"pull\", \"drv\";\n+\t\trockchip,grf = <&grf>;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tranges;\n+\n+\t\tgpio0: gpio0@2007c000 {\n+\t\t\tcompatible = \"rockchip,gpio-bank\";\n+\t\t\treg = <0x2007c000 0x100>;\n+\t\t\tinterrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&cru PCLK_GPIO0>;\n+\t\t\tgpio-controller;\n+\t\t\t#gpio-cells = <2>;\n+\t\t\tinterrupt-controller;\n+\t\t\t#interrupt-cells = <2>;\n+\t\t};\n+\n+\t\tgpio1: gpio1@20080000 {\n+\t\t\tcompatible = \"rockchip,gpio-bank\";\n+\t\t\treg = <0x20080000 0x100>;\n+\t\t\tinterrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&cru PCLK_GPIO1>;\n+\t\t\tgpio-controller;\n+\t\t\t#gpio-cells = <2>;\n+\t\t\tinterrupt-controller;\n+\t\t\t#interrupt-cells = <2>;\n+\t\t};\n+\n+\t\tgpio2: gpio2@20084000 {\n+\t\t\tcompatible = \"rockchip,gpio-bank\";\n+\t\t\treg = <0x20084000 0x100>;\n+\t\t\tinterrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&cru PCLK_GPIO2>;\n+\t\t\tgpio-controller;\n+\t\t\t#gpio-cells = <2>;\n+\t\t\tinterrupt-controller;\n+\t\t\t#interrupt-cells = <2>;\n+\t\t};\n+\n+\t\tgpio3: gpio2@20088000 {\n+\t\t\tcompatible = \"rockchip,gpio-bank\";\n+\t\t\treg = <0x20088000 0x100>;\n+\t\t\tinterrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&cru PCLK_GPIO3>;\n+\t\t\tgpio-controller;\n+\t\t\t#gpio-cells = <2>;\n+\t\t\tinterrupt-controller;\n+\t\t\t#interrupt-cells = <2>;\n+\t\t};\n+\n+\t\tpcfg_pull_up: pcfg-pull-up {\n+\t\t\tbias-pull-up;\n+\t\t};\n+\n+\t\tpcfg_pull_down: pcfg-pull-down {\n+\t\t\tbias-pull-down;\n+\t\t};\n+\n+\t\tpcfg_pull_none: pcfg-pull-none {\n+\t\t\tbias-disable;\n+\t\t};\n+\n+\t\temmc {\n+\t\t\t/*\n+\t\t\t * We run eMMC at max speed; bump up drive strength.\n+\t\t\t * We also have external pulls, so disable the internal ones.\n+\t\t\t */\n+\n+\t\t\temmc_clk: emmc-clk {\n+\t\t\t\trockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>;\n+\t\t\t};\n+\n+\t\t\temmc_cmd: emmc-cmd {\n+\t\t\t\trockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;\n+\t\t\t};\n+\n+\t\t\temmc_pwren: emmc-pwren {\n+\t\t\t\trockchip,pins = <2 5 RK_FUNC_2 &pcfg_pull_none>;\n+\t\t\t};\n+\n+\t\t\temmc_bus8: emmc-bus8 {\n+\t\t\t\trockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>,\n+\t\t\t\t\t\t<1 25 RK_FUNC_2 &pcfg_pull_none>,\n+\t\t\t\t\t\t<1 26 RK_FUNC_2 &pcfg_pull_none>,\n+\t\t\t\t\t\t<1 27 RK_FUNC_2 &pcfg_pull_none>,\n+\t\t\t\t\t\t<1 28 RK_FUNC_2 &pcfg_pull_none>,\n+\t\t\t\t\t\t<1 29 RK_FUNC_2 &pcfg_pull_none>,\n+\t\t\t\t\t\t<1 30 RK_FUNC_2 &pcfg_pull_none>,\n+\t\t\t\t\t\t<1 31 RK_FUNC_2 &pcfg_pull_none>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tnandc{\n+\t\t\tnandc_ale:nandc-ale {\n+\t\t\t\trockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;\n+\t\t\t};\n+\n+\t\t\tnandc_cle:nandc-cle {\n+\t\t\t\trockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;\n+\t\t\t};\n+\n+\t\t\tnandc_wrn:nandc-wrn {\n+\t\t\t\trockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;\n+\t\t\t};\n+\n+\t\t\tnandc_rdn:nandc-rdn {\n+\t\t\t\trockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;\n+\t\t\t};\n+\n+\t\t\tnandc_rdy:nandc-rdy {\n+\t\t\t\trockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;\n+\t\t\t};\n+\n+\t\t\tnandc_cs0:nandc-cs0 {\n+\t\t\t\trockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;\n+\t\t\t};\n+\n+\t\t\tnandc_data: nandc-data {\n+\t\t\t\trockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;\n+\t\t\t};\n+\t\t};\n+\n+\n+\t\tuart0 {\n+\t\t\tuart0_xfer: uart0-xfer {\n+\t\t\t\trockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_none>,\n+\t\t\t\t\t\t<0 17 RK_FUNC_1 &pcfg_pull_none>;\n+\t\t\t};\n+\n+\t\t\tuart0_cts: uart0-cts {\n+\t\t\t\trockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;\n+\t\t\t};\n+\n+\t\t\tuart0_rts: uart0-rts {\n+\t\t\t\trockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tuart1 {\n+\t\t\tuart1_xfer: uart1-xfer {\n+\t\t\t\trockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_none>,\n+\t\t\t\t\t\t<2 23 RK_FUNC_1 &pcfg_pull_none>;\n+\t\t\t};\n+\t\t};\n+\n+                uart2 {\n+                        uart2_xfer: uart2-xfer {\n+                                rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>,\n+                                                <1 19 RK_FUNC_2 &pcfg_pull_none>;\n+                        };\n+                };\n+\n+\t\tsdmmc {\n+\t\t\tsdmmc_clk: sdmmc-clk {\n+\t\t\t\trockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;\n+\t\t\t};\n+\n+\t\t\tsdmmc_cmd: sdmmc-cmd {\n+\t\t\t\trockchip,pins = <1 RK_PC1 1 &pcfg_pull_up>;\n+\t\t\t};\n+\n+\t\t\tsdmmc_wp: sdmmc-wp {\n+\t\t\t\trockchip,pins = <1 RK_PA7 1 &pcfg_pull_up>;\n+\t\t\t};\n+\n+\t\t\tsdmmc_pwren: sdmmc-pwren {\n+\t\t\t\trockchip,pins = <1 RK_PB6 1 &pcfg_pull_up>;\n+\t\t\t};\n+\n+\t\t\tsdmmc_bus4: sdmmc-bus4 {\n+\t\t\t\trockchip,pins = <1 RK_PC2 1 &pcfg_pull_up>,\n+\t\t\t\t\t\t<1 RK_PC3 1 &pcfg_pull_up>,\n+\t\t\t\t\t\t<1 RK_PC4 1 &pcfg_pull_up>,\n+\t\t\t\t\t\t<1 RK_PC5 1 &pcfg_pull_up>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tpwm0 {\n+\t\t\tpwm0_pin: pwm0-pin {\n+\t\t\t\trockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tpwm1 {\n+\t\t\tpwm1_pin: pwm1-pin {\n+\t\t\t\trockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tpwm2 {\n+\t\t\tpwm2_pin: pwm2-pin {\n+\t\t\t\trockchip,pins = <0 1 2 &pcfg_pull_none>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tpwm3 {\n+\t\t\tpwm3_pin: pwm3-pin {\n+\t\t\t\trockchip,pins = <0 27 1 &pcfg_pull_none>;\n+\t\t\t};\n+\t\t};\n+\n+\t\ti2c0 {\n+\t\t\ti2c0_xfer: i2c0-xfer {\n+\t\t\t\trockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,\n+\t\t\t\t\t\t<0 3 RK_FUNC_1 &pcfg_pull_none>;\n+\t\t\t};\n+\t\t};\n+\n+\t\ti2c1 {\n+\t\t\ti2c1_xfer: i2c1-xfer {\n+\t\t\t\trockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,\n+\t\t\t\t\t\t<0 3 RK_FUNC_1 &pcfg_pull_none>;\n+\t\t\t};\n+\t\t};\n+\n+\t\ti2c2 {\n+\t\t\ti2c2_xfer: i2c2-xfer {\n+\t\t\t\trockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,\n+\t\t\t\t\t\t<0 3 RK_FUNC_1 &pcfg_pull_none>;\n+\t\t\t};\n+\t\t};\n+\n+\t\ti2c3 {\n+\t\t\ti2c3_xfer: i2c3-xfer {\n+\t\t\t\trockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,\n+\t\t\t\t\t\t<0 3 RK_FUNC_1 &pcfg_pull_none>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tspi0 {\n+\t\t\tspi0_txd_mux0:spi0-txd-mux0 {\n+\t\t\t\trockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;\n+\t\t\t};\n+\n+\t\t\tspi0_rxd_mux0:spi0-rxd-mux0 {\n+\t\t\t\trockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;\n+\t\t\t};\n+\n+\t\t\tspi0_clk_mux0:spi0-clk-mux0 {\n+\t\t\t\trockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;\n+\t\t\t};\n+\n+\t\t\tspi0_cs0_mux0:spi0-cs0-mux0 {\n+\t\t\t\trockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;\n+\t\t\t};\n+\n+\t\t\tspi0_cs1_mux0:spi0-cs1-mux0 {\n+\t\t\t\trockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;\n+\t\t\t};\n+\t\t};\n+\n+\t};\n+};\ndiff --git a/include/dt-bindings/clock/rk3128-cru.h b/include/dt-bindings/clock/rk3128-cru.h\nnew file mode 100644\nindex 0000000..36c8006\n--- /dev/null\n+++ b/include/dt-bindings/clock/rk3128-cru.h\n@@ -0,0 +1,187 @@\n+/*\n+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd\n+ *\n+ * SPDX-License-Identifier:     GPL-2.0+\n+ */\n+\n+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H\n+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H\n+\n+/* core clocks */\n+#define PLL_APLL\t\t1\n+#define PLL_DPLL\t\t2\n+#define PLL_GPLL\t\t3\n+#define ARMCLK\t\t\t4\n+\n+/* sclk gates (special clocks) */\n+#define SCLK_GPU\t\t64\n+#define SCLK_SPI\t\t65\n+#define SCLK_SDMMC\t\t68\n+#define SCLK_SDIO\t\t69\n+#define SCLK_EMMC\t\t71\n+#define SCLK_NANDC\t\t76\n+#define SCLK_UART0\t\t77\n+#define SCLK_UART1\t\t78\n+#define SCLK_UART2\t\t79\n+#define SCLK_I2S\t\t82\n+#define SCLK_SPDIF\t\t83\n+#define SCLK_TIMER0\t\t85\n+#define SCLK_TIMER1\t\t86\n+#define SCLK_TIMER2\t\t87\n+#define SCLK_TIMER3\t\t88\n+#define SCLK_OTGPHY0\t\t93\n+#define SCLK_LCDC\t\t100\n+#define SCLK_HDMI\t\t109\n+#define SCLK_HEVC\t\t111\n+#define SCLK_I2S_OUT\t\t113\n+#define SCLK_SDMMC_DRV\t\t114\n+#define SCLK_SDIO_DRV\t\t115\n+#define SCLK_EMMC_DRV\t\t117\n+#define SCLK_SDMMC_SAMPLE\t118\n+#define SCLK_SDIO_SAMPLE\t119\n+#define SCLK_EMMC_SAMPLE\t121\n+#define SCLK_PVTM_CORE          123\n+#define SCLK_PVTM_GPU           124\n+#define SCLK_PVTM_VIDEO         125\n+#define SCLK_MAC\t\t151\n+#define SCLK_MACREF\t\t152\n+#define SCLK_SFC\t\t160\n+\n+#define DCLK_LCDC\t\t190\n+\n+/* aclk gates */\n+#define ACLK_DMAC2\t\t194\n+#define ACLK_LCDC\t\t197\n+#define ACLK_VIO\t\t203\n+#define ACLK_VCODEC\t\t208\n+#define ACLK_CPU\t\t209\n+#define ACLK_PERI\t\t210\n+\n+/* pclk gates */\n+#define PCLK_GPIO0\t\t320\n+#define PCLK_GPIO1\t\t321\n+#define PCLK_GPIO2\t\t322\n+#define PCLK_GPIO3\t\t323\n+#define PCLK_GRF\t\t329\n+#define PCLK_I2C0\t\t332\n+#define PCLK_I2C1\t\t333\n+#define PCLK_I2C2\t\t334\n+#define PCLK_I2C3\t\t335\n+#define PCLK_SPI\t\t338\n+#define PCLK_UART0\t\t341\n+#define PCLK_UART1\t\t342\n+#define PCLK_UART2\t\t343\n+#define PCLK_PWM\t\t350\n+#define PCLK_TIMER\t\t353\n+#define PCLK_HDMI\t\t360\n+#define PCLK_CPU\t\t362\n+#define PCLK_PERI\t\t363\n+#define PCLK_DDRUPCTL\t\t364\n+#define PCLK_WDT\t\t368\n+\n+/* hclk gates */\n+#define HCLK_OTG0\t\t449\n+#define HCLK_OTG1\t\t450\n+#define HCLK_NANDC\t\t453\n+#define HCLK_SDMMC\t\t456\n+#define HCLK_SDIO\t\t457\n+#define HCLK_EMMC\t\t459\n+#define HCLK_I2S\t\t462\n+#define HCLK_LCDC\t\t465\n+#define HCLK_ROM\t\t467\n+#define HCLK_VIO_BUS\t\t472\n+#define HCLK_VCODEC\t\t476\n+#define HCLK_CPU\t\t477\n+#define HCLK_PERI\t\t478\n+\n+#define CLK_NR_CLKS\t\t(HCLK_PERI + 1)\n+\n+/* soft-reset indices */\n+#define SRST_CORE0\t\t0\n+#define SRST_CORE1\t\t1\n+#define SRST_CORE0_DBG\t\t4\n+#define SRST_CORE1_DBG\t\t5\n+#define SRST_CORE0_POR\t\t8\n+#define SRST_CORE1_POR\t\t9\n+#define SRST_L2C\t\t12\n+#define SRST_TOPDBG\t\t13\n+#define SRST_STRC_SYS_A\t\t14\n+#define SRST_PD_CORE_NIU\t15\n+\n+#define SRST_TIMER2\t\t16\n+#define SRST_CPUSYS_H\t\t17\n+#define SRST_AHB2APB_H\t\t19\n+#define SRST_TIMER3\t\t20\n+#define SRST_INTMEM\t\t21\n+#define SRST_ROM\t\t22\n+#define SRST_PERI_NIU\t\t23\n+#define SRST_I2S\t\t24\n+#define SRST_DDR_PLL\t\t25\n+#define SRST_GPU_DLL\t\t26\n+#define SRST_TIMER0\t\t27\n+#define SRST_TIMER1\t\t28\n+#define SRST_CORE_DLL\t\t29\n+#define SRST_EFUSE_P\t\t30\n+#define SRST_ACODEC_P\t\t31\n+\n+#define SRST_GPIO0\t\t32\n+#define SRST_GPIO1\t\t33\n+#define SRST_GPIO2\t\t34\n+#define SRST_UART0\t\t39\n+#define SRST_UART1\t\t40\n+#define SRST_UART2\t\t41\n+#define SRST_I2C0\t\t43\n+#define SRST_I2C1\t\t44\n+#define SRST_I2C2\t\t45\n+#define SRST_SFC\t\t47\n+\n+#define SRST_PWM0\t\t48\n+#define SRST_DAP\t\t51\n+#define SRST_DAP_SYS\t\t52\n+#define SRST_GRF\t\t55\n+#define SRST_PERIPHSYS_A\t57\n+#define SRST_PERIPHSYS_H\t58\n+#define SRST_PERIPHSYS_P\t59\n+#define SRST_CPU_PERI\t\t61\n+#define SRST_EMEM_PERI\t\t62\n+#define SRST_USB_PERI\t\t63\n+\n+#define SRST_DMA2\t\t64\n+#define SRST_MAC\t\t66\n+#define SRST_NANDC\t\t68\n+#define SRST_USBOTG0\t\t69\n+#define SRST_OTGC0\t\t71\n+#define SRST_USBOTG1\t\t72\n+#define SRST_OTGC1\t\t74\n+#define SRST_DDRMSCH\t\t79\n+\n+#define SRST_MMC0\t\t81\n+#define SRST_SDIO\t\t82\n+#define SRST_EMMC\t\t83\n+#define SRST_SPI0\t\t84\n+#define SRST_WDT\t\t86\n+#define SRST_DDRPHY\t\t88\n+#define SRST_DDRPHY_P\t\t89\n+#define SRST_DDRCTRL\t\t90\n+#define SRST_DDRCTRL_P\t\t91\n+\n+#define SRST_HDMI_P\t\t96\n+#define SRST_VIO_BUS_H\t\t99\n+#define SRST_UTMI0\t\t103\n+#define SRST_UTMI1\t\t104\n+#define SRST_USBPOR\t\t105\n+\n+#define SRST_VCODEC_A\t\t112\n+#define SRST_VCODEC_H\t\t113\n+#define SRST_VIO1_A\t\t114\n+#define SRST_HEVC\t\t115\n+#define SRST_VCODEC_NIU_A\t116\n+#define SRST_LCDC1_A\t\t117\n+#define SRST_LCDC1_H\t\t118\n+#define SRST_LCDC1_D\t\t119\n+#define SRST_GPU\t\t120\n+#define SRST_GPU_NIU_A\t\t122\n+\n+#define SRST_DBG_P\t\t131\n+\n+#endif\n",
    "prefixes": [
        "U-Boot",
        "1/8"
    ]
}