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GET /api/patches/819109/?format=api
{ "id": 819109, "url": "http://patchwork.ozlabs.org/api/patches/819109/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/1506513517-25870-3-git-send-email-mmaddireddy@nvidia.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1506513517-25870-3-git-send-email-mmaddireddy@nvidia.com>", "list_archive_url": null, "date": "2017-09-27T11:58:35", "name": "[V2,2/4] PCI: tegra: Add Tegra186 PCIe support", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "081ee1ea8891211c3f3d75b6d59f3a6b5c58bb9e", "submitter": { "id": 72399, "url": "http://patchwork.ozlabs.org/api/people/72399/?format=api", "name": "Manikanta Maddireddy", "email": "mmaddireddy@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/1506513517-25870-3-git-send-email-mmaddireddy@nvidia.com/mbox/", "series": [ { "id": 5348, "url": "http://patchwork.ozlabs.org/api/series/5348/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=5348", "date": "2017-09-27T11:58:34", "name": "Add Tegra186 PCIe support", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/5348/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/819109/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/819109/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-pci-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2GcK0FlSz9tXC\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 27 Sep 2017 22:00:49 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752730AbdI0MAp (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tWed, 27 Sep 2017 08:00:45 -0400", "from hqemgate14.nvidia.com ([216.228.121.143]:14594 \"EHLO\n\thqemgate14.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752088AbdI0MAm (ORCPT\n\t<rfc822; linux-pci@vger.kernel.org>); Wed, 27 Sep 2017 08:00:42 -0400", "from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate14.nvidia.com\n\tid <B59cb92cf0000>; Wed, 27 Sep 2017 05:00:18 -0700", "from HQMAIL106.nvidia.com ([172.20.161.6])\n\tby hqpgpgate102.nvidia.com (PGP Universal service);\n\tWed, 27 Sep 2017 05:00:23 -0700", "from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL106.nvidia.com\n\t(172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1293.2;\n\tWed, 27 Sep 2017 11:59:51 +0000", "from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL111.nvidia.com\n\t(172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1293.2;\n\tWed, 27 Sep 2017 11:59:51 +0000", "from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL106.nvidia.com\n\t(172.18.146.12) with Microsoft SMTP Server id 15.0.1293.2 via\n\tFrontend Transport; Wed, 27 Sep 2017 11:59:51 +0000", "from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by\n\thqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 5, 8150)\n\tid <B59cb92b50000>; Wed, 27 Sep 2017 04:59:50 -0700" ], "X-PGP-Universal": "processed;\n\tby hqpgpgate102.nvidia.com on Wed, 27 Sep 2017 05:00:23 -0700", "From": "Manikanta Maddireddy <mmaddireddy@nvidia.com>", "To": "<bhelgaas@google.com>, <thierry.reding@gmail.com>, <jonathanh@nvidia.com>", "CC": "<linux-tegra@vger.kernel.org>, <linux-pci@vger.kernel.org>,\n\t<mperttunen@nvidia.com>, Manikanta Maddireddy <mmaddireddy@nvidia.com>", "Subject": "[PATCH V2 2/4] PCI: tegra: Add Tegra186 PCIe support", "Date": "Wed, 27 Sep 2017 17:28:35 +0530", "Message-ID": "<1506513517-25870-3-git-send-email-mmaddireddy@nvidia.com>", "X-Mailer": "git-send-email 2.1.4", "In-Reply-To": "<1506513517-25870-1-git-send-email-mmaddireddy@nvidia.com>", "References": "<1506513517-25870-1-git-send-email-mmaddireddy@nvidia.com>", "X-NVConfidentiality": "public", "MIME-Version": "1.0", "Content-Type": "text/plain", "Sender": "linux-pci-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-pci.vger.kernel.org>", "X-Mailing-List": "linux-pci@vger.kernel.org" }, "content": "UPHY programming is performed by BPMP, PHY enable calls are\nnot required for Tegra186 PCIe. Power partition ungate is\ndone by BPMP powergate driver.\n\nSigned-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>\nReviewed-by: Mikko Perttunen <mperttunen@nvidia.com>\nTested-by: Mikko Perttunen <mperttunen@nvidia.com>\n---\nV2: Add soc->program_uphy check for phy_exit call\n drivers/pci/host/pci-tegra.c | 132 +++++++++++++++++++++++++++++++++++--------\n 1 file changed, 108 insertions(+), 24 deletions(-)", "diff": "diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c\nindex 9c40da54f88a..96e8038c3019 100644\n--- a/drivers/pci/host/pci-tegra.c\n+++ b/drivers/pci/host/pci-tegra.c\n@@ -159,10 +159,13 @@\n #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE\t(0x0 << 20)\n #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420\t(0x0 << 20)\n #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1\t(0x0 << 20)\n+#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_401\t(0x0 << 20)\n #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL\t(0x1 << 20)\n #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222\t(0x1 << 20)\n #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1\t(0x1 << 20)\n+#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_211\t(0x1 << 20)\n #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411\t(0x2 << 20)\n+#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_111\t(0x2 << 20)\n \n #define AFI_FUSE\t\t\t0x104\n #define AFI_FUSE_PCIE_T0_GEN2_DIS\t(1 << 2)\n@@ -252,6 +255,7 @@ struct tegra_pcie_soc {\n \tbool has_cml_clk;\n \tbool has_gen2;\n \tbool force_pca_enable;\n+\tbool program_uphy;\n };\n \n static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip)\n@@ -1012,10 +1016,12 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)\n \t\tafi_writel(pcie, value, AFI_FUSE);\n \t}\n \n-\terr = tegra_pcie_phy_power_on(pcie);\n-\tif (err < 0) {\n-\t\tdev_err(dev, \"failed to power on PHY(s): %d\\n\", err);\n-\t\treturn err;\n+\tif (soc->program_uphy) {\n+\t\terr = tegra_pcie_phy_power_on(pcie);\n+\t\tif (err < 0) {\n+\t\t\tdev_err(dev, \"failed to power on PHY(s): %d\\n\", err);\n+\t\t\treturn err;\n+\t\t}\n \t}\n \n \t/* take the PCIe interface module out of reset */\n@@ -1048,19 +1054,23 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)\n static void tegra_pcie_power_off(struct tegra_pcie *pcie)\n {\n \tstruct device *dev = pcie->dev;\n+\tconst struct tegra_pcie_soc *soc = pcie->soc;\n \tint err;\n \n \t/* TODO: disable and unprepare clocks? */\n \n-\terr = tegra_pcie_phy_power_off(pcie);\n-\tif (err < 0)\n-\t\tdev_err(dev, \"failed to power off PHY(s): %d\\n\", err);\n+\tif (soc->program_uphy) {\n+\t\terr = tegra_pcie_phy_power_off(pcie);\n+\t\tif (err < 0)\n+\t\t\tdev_err(dev, \"failed to power off PHY(s): %d\\n\", err);\n+\t}\n \n \treset_control_assert(pcie->pcie_xrst);\n \treset_control_assert(pcie->afi_rst);\n \treset_control_assert(pcie->pex_rst);\n \n-\ttegra_powergate_power_off(TEGRA_POWERGATE_PCIE);\n+\tif (!dev->pm_domain)\n+\t\ttegra_powergate_power_off(TEGRA_POWERGATE_PCIE);\n \n \terr = regulator_bulk_disable(pcie->num_supplies, pcie->supplies);\n \tif (err < 0)\n@@ -1077,19 +1087,29 @@ static int tegra_pcie_power_on(struct tegra_pcie *pcie)\n \treset_control_assert(pcie->afi_rst);\n \treset_control_assert(pcie->pex_rst);\n \n-\ttegra_powergate_power_off(TEGRA_POWERGATE_PCIE);\n+\tif (!dev->pm_domain)\n+\t\ttegra_powergate_power_off(TEGRA_POWERGATE_PCIE);\n \n \t/* enable regulators */\n \terr = regulator_bulk_enable(pcie->num_supplies, pcie->supplies);\n \tif (err < 0)\n \t\tdev_err(dev, \"failed to enable regulators: %d\\n\", err);\n \n-\terr = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE,\n-\t\t\t\t\t\tpcie->pex_clk,\n-\t\t\t\t\t\tpcie->pex_rst);\n-\tif (err) {\n-\t\tdev_err(dev, \"powerup sequence failed: %d\\n\", err);\n-\t\treturn err;\n+\tif (dev->pm_domain) {\n+\t\terr = clk_prepare_enable(pcie->pex_clk);\n+\t\tif (err) {\n+\t\t\tdev_err(dev, \"failed to enable PEX clock: %d\\n\", err);\n+\t\t\treturn err;\n+\t\t}\n+\t\treset_control_deassert(pcie->pex_rst);\n+\t} else {\n+\t\terr = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE,\n+\t\t\t\t\t\t\tpcie->pex_clk,\n+\t\t\t\t\t\t\tpcie->pex_rst);\n+\t\tif (err) {\n+\t\t\tdev_err(dev, \"powerup sequence failed: %d\\n\", err);\n+\t\t\treturn err;\n+\t\t}\n \t}\n \n \treset_control_deassert(pcie->afi_rst);\n@@ -1262,6 +1282,7 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie)\n \tstruct device *dev = pcie->dev;\n \tstruct platform_device *pdev = to_platform_device(dev);\n \tstruct resource *pads, *afi, *res;\n+\tconst struct tegra_pcie_soc *soc = pcie->soc;\n \tint err;\n \n \terr = tegra_pcie_clocks_get(pcie);\n@@ -1276,10 +1297,12 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie)\n \t\treturn err;\n \t}\n \n-\terr = tegra_pcie_phys_get(pcie);\n-\tif (err < 0) {\n-\t\tdev_err(dev, \"failed to get PHYs: %d\\n\", err);\n-\t\treturn err;\n+\tif (soc->program_uphy) {\n+\t\terr = tegra_pcie_phys_get(pcie);\n+\t\tif (err < 0) {\n+\t\t\tdev_err(dev, \"failed to get PHYs: %d\\n\", err);\n+\t\t\treturn err;\n+\t\t}\n \t}\n \n \terr = tegra_pcie_power_on(pcie);\n@@ -1341,6 +1364,7 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie)\n static int tegra_pcie_put_resources(struct tegra_pcie *pcie)\n {\n \tstruct device *dev = pcie->dev;\n+\tconst struct tegra_pcie_soc *soc = pcie->soc;\n \tint err;\n \n \tif (pcie->irq > 0)\n@@ -1348,9 +1372,11 @@ static int tegra_pcie_put_resources(struct tegra_pcie *pcie)\n \n \ttegra_pcie_power_off(pcie);\n \n-\terr = phy_exit(pcie->phy);\n-\tif (err < 0)\n-\t\tdev_err(dev, \"failed to teardown PHY: %d\\n\", err);\n+\tif (soc->program_uphy) {\n+\t\terr = phy_exit(pcie->phy);\n+\t\tif (err < 0)\n+\t\t\tdev_err(dev, \"failed to teardown PHY: %d\\n\", err);\n+\t}\n \n \treturn 0;\n }\n@@ -1616,7 +1642,31 @@ static int tegra_pcie_get_xbar_config(struct tegra_pcie *pcie, u32 lanes,\n \tstruct device *dev = pcie->dev;\n \tstruct device_node *np = dev->of_node;\n \n-\tif (of_device_is_compatible(np, \"nvidia,tegra124-pcie\") ||\n+\tif (of_device_is_compatible(np, \"nvidia,tegra186-pcie\")) {\n+\t\tswitch (lanes) {\n+\t\tcase 0x010004:\n+\t\t\tdev_info(dev, \"4x1, 1x1 configuration\\n\");\n+\t\t\t*xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_401;\n+\t\t\treturn 0;\n+\n+\t\tcase 0x010102:\n+\t\t\tdev_info(dev, \"2x1, 1X1, 1x1 configuration\\n\");\n+\t\t\t*xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_211;\n+\t\t\treturn 0;\n+\n+\t\tcase 0x010101:\n+\t\t\tdev_info(dev, \"1x1, 1x1, 1x1 configuration\\n\");\n+\t\t\t*xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_111;\n+\t\t\treturn 0;\n+\n+\t\tdefault:\n+\t\t\tdev_info(dev, \"wrong configuration updated in DT, \"\n+\t\t\t\t \"switching to default 2x1, 1x1, 1x1 \"\n+\t\t\t\t \"configuration\\n\");\n+\t\t\t*xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_211;\n+\t\t\treturn 0;\n+\t\t}\n+\t} else if (of_device_is_compatible(np, \"nvidia,tegra124-pcie\") ||\n \t of_device_is_compatible(np, \"nvidia,tegra210-pcie\")) {\n \t\tswitch (lanes) {\n \t\tcase 0x0000104:\n@@ -1737,7 +1787,20 @@ static int tegra_pcie_get_regulators(struct tegra_pcie *pcie, u32 lane_mask)\n \tstruct device_node *np = dev->of_node;\n \tunsigned int i = 0;\n \n-\tif (of_device_is_compatible(np, \"nvidia,tegra210-pcie\")) {\n+\tif (of_device_is_compatible(np, \"nvidia,tegra186-pcie\")) {\n+\t\tpcie->num_supplies = 4;\n+\n+\t\tpcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies,\n+\t\t\t\t\t sizeof(*pcie->supplies),\n+\t\t\t\t\t GFP_KERNEL);\n+\t\tif (!pcie->supplies)\n+\t\t\treturn -ENOMEM;\n+\n+\t\tpcie->supplies[i++].supply = \"dvdd-pex\";\n+\t\tpcie->supplies[i++].supply = \"hvdd-pex-pll\";\n+\t\tpcie->supplies[i++].supply = \"hvdd-pex\";\n+\t\tpcie->supplies[i++].supply = \"vddio-pexctl-aud\";\n+\t} else if (of_device_is_compatible(np, \"nvidia,tegra210-pcie\")) {\n \t\tpcie->num_supplies = 6;\n \n \t\tpcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies,\n@@ -2076,6 +2139,7 @@ static const struct tegra_pcie_soc tegra20_pcie = {\n \t.has_cml_clk = false,\n \t.has_gen2 = false,\n \t.force_pca_enable = false,\n+\t.program_uphy = true,\n };\n \n static const struct tegra_pcie_soc tegra30_pcie = {\n@@ -2091,6 +2155,7 @@ static const struct tegra_pcie_soc tegra30_pcie = {\n \t.has_cml_clk = true,\n \t.has_gen2 = false,\n \t.force_pca_enable = false,\n+\t.program_uphy = true,\n };\n \n static const struct tegra_pcie_soc tegra124_pcie = {\n@@ -2105,6 +2170,7 @@ static const struct tegra_pcie_soc tegra124_pcie = {\n \t.has_cml_clk = true,\n \t.has_gen2 = true,\n \t.force_pca_enable = false,\n+\t.program_uphy = true,\n };\n \n static const struct tegra_pcie_soc tegra210_pcie = {\n@@ -2119,9 +2185,27 @@ static const struct tegra_pcie_soc tegra210_pcie = {\n \t.has_cml_clk = true,\n \t.has_gen2 = true,\n \t.force_pca_enable = true,\n+\t.program_uphy = true,\n+};\n+\n+static const struct tegra_pcie_soc tegra186_pcie = {\n+\t.num_ports = 3,\n+\t.msi_base_shift = 8,\n+\t.pads_pll_ctl = PADS_PLL_CTL_TEGRA30,\n+\t.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,\n+\t.pads_refclk_cfg0 = 0x80b880b8,\n+\t.pads_refclk_cfg1 = 0x000480b8,\n+\t.has_pex_clkreq_en = true,\n+\t.has_pex_bias_ctrl = true,\n+\t.has_intr_prsnt_sense = true,\n+\t.has_cml_clk = false,\n+\t.has_gen2 = true,\n+\t.force_pca_enable = false,\n+\t.program_uphy = false,\n };\n \n static const struct of_device_id tegra_pcie_of_match[] = {\n+\t{ .compatible = \"nvidia,tegra186-pcie\", .data = &tegra186_pcie },\n \t{ .compatible = \"nvidia,tegra210-pcie\", .data = &tegra210_pcie },\n \t{ .compatible = \"nvidia,tegra124-pcie\", .data = &tegra124_pcie },\n \t{ .compatible = \"nvidia,tegra30-pcie\", .data = &tegra30_pcie },\n", "prefixes": [ "V2", "2/4" ] }