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{
    "id": 818886,
    "url": "http://patchwork.ozlabs.org/api/patches/818886/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/netdev/patch/1506476732-128130-6-git-send-email-linyunsheng@huawei.com/",
    "project": {
        "id": 7,
        "url": "http://patchwork.ozlabs.org/api/projects/7/?format=api",
        "name": "Linux network development",
        "link_name": "netdev",
        "list_id": "netdev.vger.kernel.org",
        "list_email": "netdev@vger.kernel.org",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<1506476732-128130-6-git-send-email-linyunsheng@huawei.com>",
    "list_archive_url": null,
    "date": "2017-09-27T01:45:27",
    "name": "[v3,net-next,05/10] net: hns3: Add tc-based TM support for sriov enabled port",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "b8378833737a9d70ec8ddb6d81ae4aeeeaa0551e",
    "submitter": {
        "id": 71804,
        "url": "http://patchwork.ozlabs.org/api/people/71804/?format=api",
        "name": "Yunsheng Lin",
        "email": "linyunsheng@huawei.com"
    },
    "delegate": {
        "id": 34,
        "url": "http://patchwork.ozlabs.org/api/users/34/?format=api",
        "username": "davem",
        "first_name": "David",
        "last_name": "Miller",
        "email": "davem@davemloft.net"
    },
    "mbox": "http://patchwork.ozlabs.org/project/netdev/patch/1506476732-128130-6-git-send-email-linyunsheng@huawei.com/mbox/",
    "series": [
        {
            "id": 5263,
            "url": "http://patchwork.ozlabs.org/api/series/5263/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/netdev/list/?series=5263",
            "date": "2017-09-27T01:45:23",
            "name": "Add support for DCB feature in hns3 driver",
            "version": 3,
            "mbox": "http://patchwork.ozlabs.org/series/5263/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/818886/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/818886/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<netdev-owner@vger.kernel.org>",
        "X-Original-To": "patchwork-incoming@ozlabs.org",
        "Delivered-To": "patchwork-incoming@ozlabs.org",
        "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)",
        "Received": [
            "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y210G06wCz9t3m\n\tfor <patchwork-incoming@ozlabs.org>;\n\tWed, 27 Sep 2017 11:47:10 +1000 (AEST)",
            "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1033138AbdI0Bqf (ORCPT <rfc822;patchwork-incoming@ozlabs.org>);\n\tTue, 26 Sep 2017 21:46:35 -0400",
            "from szxga05-in.huawei.com ([45.249.212.191]:7036 \"EHLO\n\tszxga05-in.huawei.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1033086AbdI0BqG (ORCPT\n\t<rfc822;netdev@vger.kernel.org>); Tue, 26 Sep 2017 21:46:06 -0400",
            "from 172.30.72.59 (EHLO DGGEMS402-HUB.china.huawei.com)\n\t([172.30.72.59])\n\tby dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued)\n\twith ESMTP id DIC26243; Wed, 27 Sep 2017 09:46:03 +0800 (CST)",
            "from localhost.localdomain (10.67.212.75) by\n\tDGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP\n\tServer id 14.3.301.0; Wed, 27 Sep 2017 09:45:51 +0800"
        ],
        "From": "Yunsheng Lin <linyunsheng@huawei.com>",
        "To": "<davem@davemloft.net>",
        "CC": "<huangdaode@hisilicon.com>, <xuwei5@hisilicon.com>,\n\t<liguozhu@hisilicon.com>, <Yisen.Zhuang@huawei.com>,\n\t<gabriele.paoloni@huawei.com>, <john.garry@huawei.com>,\n\t<linuxarm@huawei.com>, <yisen.zhuang@huawei.com>,\n\t<salil.mehta@huawei.com>, <lipeng321@huawei.com>,\n\t<netdev@vger.kernel.org>, <linux-kernel@vger.kernel.org>",
        "Subject": "[PATCH v3 net-next 05/10] net: hns3: Add tc-based TM support for\n\tsriov enabled port",
        "Date": "Wed, 27 Sep 2017 09:45:27 +0800",
        "Message-ID": "<1506476732-128130-6-git-send-email-linyunsheng@huawei.com>",
        "X-Mailer": "git-send-email 1.9.1",
        "In-Reply-To": "<1506476732-128130-1-git-send-email-linyunsheng@huawei.com>",
        "References": "<1506476732-128130-1-git-send-email-linyunsheng@huawei.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
        "X-Originating-IP": "[10.67.212.75]",
        "X-CFilter-Loop": "Reflected",
        "X-Mirapoint-Virus-RAPID-Raw": "score=unknown(0),\n\trefid=str=0001.0A020203.59CB02DB.003B, ss=1, re=0.000, recu=0.000,\n\treip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0,\n\tso=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32",
        "X-Mirapoint-Loop-Id": "708476ef092c7c1af938c5e5207c583f",
        "Sender": "netdev-owner@vger.kernel.org",
        "Precedence": "bulk",
        "List-ID": "<netdev.vger.kernel.org>",
        "X-Mailing-List": "netdev@vger.kernel.org"
    },
    "content": "When sriov is enabled and TM is in tc-based mode, vf's TM\nparameters is not set in TM initialization process.\nThis patch add the tc_based TM support for sriov enabled\nusing the information in vport struct.\n\nSigned-off-by: Yunsheng Lin <linyunsheng@huawei.com>\n---\n .../net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c  | 49 ++++++++++++++--------\n 1 file changed, 31 insertions(+), 18 deletions(-)",
    "diff": "diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c\nindex f79cebd..ea94d23 100644\n--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c\n+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c\n@@ -388,13 +388,13 @@ static int hclge_tm_pri_schd_mode_cfg(struct hclge_dev *hdev, u8 pri_id)\n \treturn hclge_cmd_send(&hdev->hw, &desc, 1);\n }\n \n-static int hclge_tm_qs_schd_mode_cfg(struct hclge_dev *hdev, u16 qs_id)\n+static int hclge_tm_qs_schd_mode_cfg(struct hclge_dev *hdev, u16 qs_id, u8 mode)\n {\n \tstruct hclge_desc desc;\n \n \thclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_SCH_MODE_CFG, false);\n \n-\tif (hdev->tm_info.tc_info[qs_id].tc_sch_mode == HCLGE_SCH_MODE_DWRR)\n+\tif (mode == HCLGE_SCH_MODE_DWRR)\n \t\tdesc.data[1] = cpu_to_le32(HCLGE_TM_TX_SCHD_DWRR_MSK);\n \telse\n \t\tdesc.data[1] = 0;\n@@ -638,17 +638,18 @@ static int hclge_tm_pri_q_qs_cfg(struct hclge_dev *hdev)\n {\n \tstruct hclge_vport *vport = hdev->vport;\n \tint ret;\n-\tu32 i;\n+\tu32 i, k;\n \n \tif (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) {\n \t\t/* Cfg qs -> pri mapping, one by one mapping */\n-\t\tfor (i = 0; i < hdev->tm_info.num_tc; i++) {\n-\t\t\tret = hclge_tm_qs_to_pri_map_cfg(hdev, i, i);\n-\t\t\tif (ret)\n-\t\t\t\treturn ret;\n-\t\t}\n+\t\tfor (k = 0; k < hdev->num_alloc_vport; k++)\n+\t\t\tfor (i = 0; i < hdev->tm_info.num_tc; i++) {\n+\t\t\t\tret = hclge_tm_qs_to_pri_map_cfg(\n+\t\t\t\t\thdev, vport[k].qs_offset + i, i);\n+\t\t\t\tif (ret)\n+\t\t\t\t\treturn ret;\n+\t\t\t}\n \t} else if (hdev->tx_sch_mode == HCLGE_FLAG_VNET_BASE_SCH_MODE) {\n-\t\tint k;\n \t\t/* Cfg qs -> pri mapping,  qs = tc, pri = vf, 8 qs -> 1 pri */\n \t\tfor (k = 0; k < hdev->num_alloc_vport; k++)\n \t\t\tfor (i = 0; i < HNAE3_MAX_TC; i++) {\n@@ -797,10 +798,11 @@ static int hclge_tm_pri_shaper_cfg(struct hclge_dev *hdev)\n \n static int hclge_tm_pri_tc_base_dwrr_cfg(struct hclge_dev *hdev)\n {\n+\tstruct hclge_vport *vport = hdev->vport;\n \tstruct hclge_pg_info *pg_info;\n \tu8 dwrr;\n \tint ret;\n-\tu32 i;\n+\tu32 i, k;\n \n \tfor (i = 0; i < hdev->tm_info.num_tc; i++) {\n \t\tpg_info =\n@@ -811,9 +813,13 @@ static int hclge_tm_pri_tc_base_dwrr_cfg(struct hclge_dev *hdev)\n \t\tif (ret)\n \t\t\treturn ret;\n \n-\t\tret = hclge_tm_qs_weight_cfg(hdev, i, dwrr);\n-\t\tif (ret)\n-\t\t\treturn ret;\n+\t\tfor (k = 0; k < hdev->num_alloc_vport; k++) {\n+\t\t\tret = hclge_tm_qs_weight_cfg(\n+\t\t\t\thdev, vport[k].qs_offset + i,\n+\t\t\t\tvport[k].dwrr);\n+\t\t\tif (ret)\n+\t\t\t\treturn ret;\n+\t\t}\n \t}\n \n \treturn 0;\n@@ -944,7 +950,10 @@ static int hclge_tm_schd_mode_vnet_base_cfg(struct hclge_vport *vport)\n \t\treturn ret;\n \n \tfor (i = 0; i < kinfo->num_tc; i++) {\n-\t\tret = hclge_tm_qs_schd_mode_cfg(hdev, vport->qs_offset + i);\n+\t\tu8 sch_mode = hdev->tm_info.tc_info[i].tc_sch_mode;\n+\n+\t\tret = hclge_tm_qs_schd_mode_cfg(hdev, vport->qs_offset + i,\n+\t\t\t\t\t\tsch_mode);\n \t\tif (ret)\n \t\t\treturn ret;\n \t}\n@@ -956,7 +965,7 @@ static int hclge_tm_lvl34_schd_mode_cfg(struct hclge_dev *hdev)\n {\n \tstruct hclge_vport *vport = hdev->vport;\n \tint ret;\n-\tu8 i;\n+\tu8 i, k;\n \n \tif (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) {\n \t\tfor (i = 0; i < hdev->tm_info.num_tc; i++) {\n@@ -964,9 +973,13 @@ static int hclge_tm_lvl34_schd_mode_cfg(struct hclge_dev *hdev)\n \t\t\tif (ret)\n \t\t\t\treturn ret;\n \n-\t\t\tret = hclge_tm_qs_schd_mode_cfg(hdev, i);\n-\t\t\tif (ret)\n-\t\t\t\treturn ret;\n+\t\t\tfor (k = 0; k < hdev->num_alloc_vport; k++) {\n+\t\t\t\tret = hclge_tm_qs_schd_mode_cfg(\n+\t\t\t\t\thdev, vport[k].qs_offset + i,\n+\t\t\t\t\tHCLGE_SCH_MODE_DWRR);\n+\t\t\t\tif (ret)\n+\t\t\t\t\treturn ret;\n+\t\t\t}\n \t\t}\n \t} else {\n \t\tfor (i = 0; i < hdev->num_alloc_vport; i++) {\n",
    "prefixes": [
        "v3",
        "net-next",
        "05/10"
    ]
}