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{
    "id": 818658,
    "url": "http://patchwork.ozlabs.org/api/patches/818658/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20170926141720.25067-5-mika.westerberg@linux.intel.com/",
    "project": {
        "id": 28,
        "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api",
        "name": "Linux PCI development",
        "link_name": "linux-pci",
        "list_id": "linux-pci.vger.kernel.org",
        "list_email": "linux-pci@vger.kernel.org",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20170926141720.25067-5-mika.westerberg@linux.intel.com>",
    "list_archive_url": null,
    "date": "2017-09-26T14:17:17",
    "name": "[4/7] PCI: Distribute available resources to hotplug capable PCIe downstream ports",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": false,
    "hash": "d43e1c5da28f0ce48e48e9eb09affd61b1a97ee3",
    "submitter": {
        "id": 14534,
        "url": "http://patchwork.ozlabs.org/api/people/14534/?format=api",
        "name": "Mika Westerberg",
        "email": "mika.westerberg@linux.intel.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20170926141720.25067-5-mika.westerberg@linux.intel.com/mbox/",
    "series": [
        {
            "id": 5151,
            "url": "http://patchwork.ozlabs.org/api/series/5151/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=5151",
            "date": "2017-09-26T14:17:19",
            "name": "PCI: Improvements for native PCIe hotplug",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/5151/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/818658/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/818658/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<linux-pci-owner@vger.kernel.org>",
        "X-Original-To": "incoming@patchwork.ozlabs.org",
        "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org",
        "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)",
        "Received": [
            "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y1jjT38ybz9t43\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 27 Sep 2017 00:18:21 +1000 (AEST)",
            "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S968343AbdIZOR7 (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tTue, 26 Sep 2017 10:17:59 -0400",
            "from mga11.intel.com ([192.55.52.93]:2567 \"EHLO mga11.intel.com\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S935880AbdIZORz (ORCPT <rfc822;linux-pci@vger.kernel.org>);\n\tTue, 26 Sep 2017 10:17:55 -0400",
            "from orsmga001.jf.intel.com ([10.7.209.18])\n\tby fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t26 Sep 2017 07:17:54 -0700",
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            "by black.fi.intel.com (Postfix, from userid 1001)\n\tid 7114B384; Tue, 26 Sep 2017 17:17:20 +0300 (EEST)"
        ],
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.42,441,1500966000\"; d=\"scan'208\";a=\"1175944709\"",
        "From": "Mika Westerberg <mika.westerberg@linux.intel.com>",
        "To": "Bjorn Helgaas <bhelgaas@google.com>",
        "Cc": "Ashok Raj <ashok.raj@intel.com>, Keith Busch <keith.busch@intel.com>,\n\t\"Rafael J . Wysocki\" <rafael.j.wysocki@intel.com>,\n\tLukas Wunner <lukas@wunner.de>, Michael Jamet <michael.jamet@intel.com>,\n\tYehezkel Bernat <yehezkel.bernat@intel.com>, Mario.Limonciello@dell.com,\n\tMika Westerberg <mika.westerberg@linux.intel.com>,\n\tlinux-pci@vger.kernel.org, linux-kernel@vger.kernel.org",
        "Subject": "[PATCH 4/7] PCI: Distribute available resources to hotplug capable\n\tPCIe downstream ports",
        "Date": "Tue, 26 Sep 2017 17:17:17 +0300",
        "Message-Id": "<20170926141720.25067-5-mika.westerberg@linux.intel.com>",
        "X-Mailer": "git-send-email 2.14.1",
        "In-Reply-To": "<20170926141720.25067-1-mika.westerberg@linux.intel.com>",
        "References": "<20170926141720.25067-1-mika.westerberg@linux.intel.com>",
        "Sender": "linux-pci-owner@vger.kernel.org",
        "Precedence": "bulk",
        "List-ID": "<linux-pci.vger.kernel.org>",
        "X-Mailing-List": "linux-pci@vger.kernel.org"
    },
    "content": "The same problem that we have with bus space, applies to other resources\nas well. Linux only allocates the minimal amount of resources so that\nthe devices currently present barely fit there. This prevents extending\nthe chain later on because the resource windows allocated for hotplug\ndownstream ports are too small.\n\nHere we follow what we already did for bus number and assign all\navailable extra resources to hotplug capable PCIe downstream ports. This\nmakes it possible to extend the hierarchy later.\n\nSigned-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>\n---\n drivers/pci/setup-bus.c | 169 ++++++++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 169 insertions(+)",
    "diff": "diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c\nindex 958da7db9033..5df6cbcfbf54 100644\n--- a/drivers/pci/setup-bus.c\n+++ b/drivers/pci/setup-bus.c\n@@ -1853,6 +1853,167 @@ void __init pci_assign_unassigned_resources(void)\n \t}\n }\n \n+static void extend_bridge_window(struct pci_dev *bridge, struct resource *res,\n+\t\t\tstruct list_head *add_list, resource_size_t available)\n+{\n+\tstruct pci_dev_resource *dev_res;\n+\n+\tif (res->parent)\n+\t\treturn;\n+\n+\tif (resource_size(res) >= available)\n+\t\treturn;\n+\n+\tdev_res = res_to_dev_res(add_list, res);\n+\tif (!dev_res)\n+\t\treturn;\n+\n+\t/* Is there room to extend the window */\n+\tif (available - resource_size(res) <= dev_res->add_size)\n+\t\treturn;\n+\n+\tdev_res->add_size = available - resource_size(res);\n+\tdev_dbg(&bridge->dev, \"bridge window %pR extended by %pa\\n\", res,\n+\t\t&dev_res->add_size);\n+}\n+\n+static void pci_bus_distribute_available_resources(struct pci_bus *bus,\n+\tstruct list_head *add_list, resource_size_t available_io,\n+\tresource_size_t available_mmio, resource_size_t available_mmio_pref)\n+{\n+\tresource_size_t remaining_io, remaining_mmio, remaining_mmio_pref;\n+\tstruct resource *io_res, *mmio_res, *mmio_pref_res;\n+\tstruct pci_dev *dev, *bridge = bus->self;\n+\tunsigned int hotplug_bridges = 0;\n+\n+\tio_res = &bridge->resource[PCI_BRIDGE_RESOURCES + 0];\n+\tmmio_res = &bridge->resource[PCI_BRIDGE_RESOURCES + 1];\n+\tmmio_pref_res = &bridge->resource[PCI_BRIDGE_RESOURCES + 2];\n+\n+\t/*\n+\t * Update additional resource list (add_list) to fill all the\n+\t * extra resource space available for this port except the space\n+\t * calculated in __pci_bus_size_bridges() which covers all the\n+\t * devices currently connected to the port and below.\n+\t */\n+\textend_bridge_window(bridge, io_res, add_list, available_io);\n+\textend_bridge_window(bridge, mmio_res, add_list, available_mmio);\n+\textend_bridge_window(bridge, mmio_pref_res, add_list,\n+\t\t\t     available_mmio_pref);\n+\n+\t/*\n+\t * Calculate the total amount of extra resource space we can\n+\t * pass the to bridges below this one. This is basically the\n+\t * extra space substracted by the minimal required space for the\n+\t * non-hotplug bridges.\n+\t */\n+\tremaining_io = available_io;\n+\tremaining_mmio = available_mmio;\n+\tremaining_mmio_pref = available_mmio_pref;\n+\n+\tlist_for_each_entry(dev, &bus->devices, bus_list) {\n+\t\tconst struct resource *res;\n+\n+\t\tif (!pci_is_bridge(dev))\n+\t\t\tcontinue;\n+\n+\t\t/* Keep track how many hotplug bridges this bus has */\n+\t\tif (dev->is_hotplug_bridge) {\n+\t\t\thotplug_bridges++;\n+\t\t} else {\n+\t\t\t/*\n+\t\t\t * Reduce the available resource space by what\n+\t\t\t * the bridge and devices below it occupy.\n+\t\t\t */\n+\t\t\tres = &dev->resource[PCI_BRIDGE_RESOURCES + 0];\n+\t\t\tif (!res->parent && available_io > resource_size(res))\n+\t\t\t\tremaining_io -= resource_size(res);\n+\n+\t\t\tres = &dev->resource[PCI_BRIDGE_RESOURCES + 1];\n+\t\t\tif (!res->parent && available_mmio > resource_size(res))\n+\t\t\t\tremaining_mmio -= resource_size(res);\n+\n+\t\t\tres = &dev->resource[PCI_BRIDGE_RESOURCES + 2];\n+\t\t\tif (!res->parent &&\n+\t\t\t    available_mmio_pref > resource_size(res))\n+\t\t\t\tremaining_mmio_pref -= resource_size(res);\n+\t\t}\n+\t}\n+\n+\t/*\n+\t * Go over devices on this bus and distribute the remaining\n+\t * resource space between hotplug bridges.\n+\t */\n+\tlist_for_each_entry(dev, &bus->devices, bus_list) {\n+\t\tstruct pci_bus *b;\n+\n+\t\tb = dev->subordinate;\n+\t\tif (!b || !pci_is_bridge(dev))\n+\t\t\tcontinue;\n+\n+\t\tif (pcie_upstream_port(dev)) {\n+\t\t\t/*\n+\t\t\t * Upstream port gets all resources directly\n+\t\t\t * from the downstream port.\n+\t\t\t */\n+\t\t\tpci_bus_distribute_available_resources(b, add_list,\n+\t\t\t\tavailable_io, available_mmio,\n+\t\t\t\tavailable_mmio_pref);\n+\t\t} else if (dev->is_hotplug_bridge) {\n+\t\t\tresource_size_t align, io, mmio, mmio_pref;\n+\n+\t\t\t/*\n+\t\t\t * Distribute available extra resources equally\n+\t\t\t * between hotplug capable downstream ports\n+\t\t\t * taking alignment into account.\n+\t\t\t *\n+\t\t\t * Here hotplug_bridges is always != 0.\n+\t\t\t */\n+\t\t\talign = pci_resource_alignment(bridge, io_res);\n+\t\t\tio = div64_ul(available_io, hotplug_bridges);\n+\t\t\tio = min(ALIGN(io, align), remaining_io);\n+\t\t\tremaining_io -= io;\n+\n+\t\t\talign = pci_resource_alignment(bridge, mmio_res);\n+\t\t\tmmio = div64_ul(available_mmio, hotplug_bridges);\n+\t\t\tmmio = min(ALIGN(mmio, align), remaining_mmio);\n+\t\t\tremaining_mmio -= mmio;\n+\n+\t\t\talign = pci_resource_alignment(bridge, mmio_pref_res);\n+\t\t\tmmio_pref = div64_ul(available_mmio_pref,\n+\t\t\t\t\t     hotplug_bridges);\n+\t\t\tmmio_pref = min(ALIGN(mmio_pref, align),\n+\t\t\t\t\tremaining_mmio_pref);\n+\t\t\tremaining_mmio_pref -= mmio_pref;\n+\n+\t\t\tpci_bus_distribute_available_resources(b, add_list, io,\n+\t\t\t\t\t\t\t       mmio, mmio_pref);\n+\t\t}\n+\t}\n+}\n+\n+static void\n+pci_bridge_distribute_available_resources(struct pci_dev *bridge,\n+\t\t\t\t\t  struct list_head *add_list)\n+{\n+\tresource_size_t available_io, available_mmio, available_mmio_pref;\n+\tconst struct resource *res;\n+\n+\tif (!bridge->is_hotplug_bridge)\n+\t\treturn;\n+\n+\t/* Take the initial extra resources from the hotplug port */\n+\tres = &bridge->resource[PCI_BRIDGE_RESOURCES + 0];\n+\tavailable_io = resource_size(res);\n+\tres = &bridge->resource[PCI_BRIDGE_RESOURCES + 1];\n+\tavailable_mmio = resource_size(res);\n+\tres = &bridge->resource[PCI_BRIDGE_RESOURCES + 2];\n+\tavailable_mmio_pref = resource_size(res);\n+\n+\tpci_bus_distribute_available_resources(bridge->subordinate,\n+\t\tadd_list, available_io, available_mmio, available_mmio_pref);\n+}\n+\n void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)\n {\n \tstruct pci_bus *parent = bridge->subordinate;\n@@ -1867,6 +2028,14 @@ void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)\n \n again:\n \t__pci_bus_size_bridges(parent, &add_list);\n+\n+\t/*\n+\t * Distribute remaining resources (if any) equally between\n+\t * hotplug bridges below. This makes it possible to extend the\n+\t * hierarchy later without running out of resources.\n+\t */\n+\tpci_bridge_distribute_available_resources(bridge, &add_list);\n+\n \t__pci_bridge_assign_resources(bridge, &add_list, &fail_head);\n \tBUG_ON(!list_empty(&add_list));\n \ttried_times++;\n",
    "prefixes": [
        "4/7"
    ]
}