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GET /api/patches/818516/?format=api
{ "id": 818516, "url": "http://patchwork.ozlabs.org/api/patches/818516/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/20170926103751.21907-4-krebbel@linux.vnet.ibm.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170926103751.21907-4-krebbel@linux.vnet.ibm.com>", "list_archive_url": null, "date": "2017-09-26T10:37:46", "name": "[3/8] S/390: Add support for vec_shr", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "d1029d6bba90fb8928b88ab9da430078af3942fc", "submitter": { "id": 4421, "url": "http://patchwork.ozlabs.org/api/people/4421/?format=api", "name": "Andreas Krebbel", "email": "krebbel@linux.vnet.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/20170926103751.21907-4-krebbel@linux.vnet.ibm.com/mbox/", "series": [ { "id": 5096, "url": "http://patchwork.ozlabs.org/api/series/5096/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=5096", "date": "2017-09-26T10:37:43", "name": "S/390: Enable vect tests on S/390 + fixes and improvements", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/5096/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/818516/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/818516/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-return-462949-incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "mailing list gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=gcc-patches-return-462949-incoming=patchwork.ozlabs.org@gcc.gnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org\n\theader.b=\"ZdVsyuQp\"; dkim-atps=neutral", "sourceware.org; auth=none" ], "Received": [ "from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y1crR3h1Xz9tXc\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 26 Sep 2017 20:39:03 +1000 (AEST)", "(qmail 102591 invoked by alias); 26 Sep 2017 10:38:07 -0000", "(qmail 102478 invoked by uid 89); 26 Sep 2017 10:38:07 -0000", "from mx0b-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com)\n\t(148.163.158.5) by sourceware.org\n\t(qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP;\n\tTue, 26 Sep 2017 10:38:05 +0000", "from pps.filterd (m0098420.ppops.net [127.0.0.1])\tby\n\tmx0b-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv8QAY6fX064274\tfor <gcc-patches@gcc.gnu.org>;\n\tTue, 26 Sep 2017 06:37:58 -0400", "from e06smtp10.uk.ibm.com (e06smtp10.uk.ibm.com\n\t[195.75.94.106])\tby mx0b-001b2d01.pphosted.com with ESMTP id\n\t2d7k1m8tqp-1\t(version=TLSv1.2 cipher=AES256-SHA bits=256\n\tverify=NOT)\tfor <gcc-patches@gcc.gnu.org>;\n\tTue, 26 Sep 2017 06:37:58 -0400", "from localhost\tby e06smtp10.uk.ibm.com with IBM ESMTP SMTP\n\tGateway: Authorized Use Only! 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a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender:from\n\t:to:subject:date:in-reply-to:references:message-id; s=default;\n\tbh=kOppX6LxOEzhlw/fXgF/eI3DUAY=; b=ZdVsyuQpL5sHGGz1r6bCnaiiofU2\n\tcsGMo/OO5R4oEfWsBzTZCi6ak7B5reHAVrdRAIxNJ8qqvJVX5fi4gb/T4CbYhrk/\n\tXl6VRg/0qd/ljWFNUzOJ23yWvbxJtE/X78r6LEfXa9lWsi3wanN/J4q3/3OhYvyE\n\tah6zVGCvYxjUutE=", "Mailing-List": "contact gcc-patches-help@gcc.gnu.org; run by ezmlm", "Precedence": "bulk", "List-Id": "<gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<mailto:gcc-patches-unsubscribe-incoming=patchwork.ozlabs.org@gcc.gnu.org>", "List-Archive": "<http://gcc.gnu.org/ml/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-help@gcc.gnu.org>", "Sender": "gcc-patches-owner@gcc.gnu.org", "X-Virus-Found": "No", "X-Spam-SWARE-Status": "No, score=-24.6 required=5.0 tests=AWL, BAYES_00,\n\tGIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3,\n\tKAM_LAZY_DOMAIN_SECURITY,\n\tRCVD_IN_DNSWL_LOW autolearn=ham version=3.3.2 spammy=Turn", "X-HELO": "mx0a-001b2d01.pphosted.com", "From": "Andreas Krebbel <krebbel@linux.vnet.ibm.com>", "To": "gcc-patches@gcc.gnu.org", "Subject": "[PATCH 3/8] S/390: Add support for vec_shr", "Date": "Tue, 26 Sep 2017 12:37:46 +0200", "In-Reply-To": "<20170926103751.21907-1-krebbel@linux.vnet.ibm.com>", "References": "<20170926103751.21907-1-krebbel@linux.vnet.ibm.com>", "X-TM-AS-GCONF": "00", "x-cbid": "17092610-0040-0000-0000-000003DD25BD", "X-IBM-AV-DETECTION": "SAVI=unused REMOTE=unused XFE=unused", "x-cbparentid": "17092610-0041-0000-0000-000025DE6F3F", "Message-Id": "<20170926103751.21907-4-krebbel@linux.vnet.ibm.com>", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-09-26_03:, , signatures=0", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n\tspamscore=0 suspectscore=1 malwarescore=0 phishscore=0\n\tadultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx\n\tscancount=1 engine=8.0.1-1707230000\n\tdefinitions=main-1709260158", "X-IsSubscribed": "yes" }, "content": "gcc/ChangeLog:\n\n2017-09-26 Andreas Krebbel <krebbel@linux.vnet.ibm.com>\n\n\t* config/s390/predicates.md (\"const_shift_by_byte_operand\"): New\n\tpredicate.\n\t* config/s390/vector.md (\"*vec_srb<mode>\"): Change modes to V_128\n\tand V16QI.\n\t(\"*vec_slb<mode>\"): New insn pattern.\n\t(\"vec_shr_<mode>\"): New expander.\n\t* config/s390/vx-builtins.md (\"vec_slb<mode>\"): Turn into expander\n\tand force the shift count operand to V16QImode.\n\t(\"vec_srb<mode>\"): Set shift count mode to V16QI.\n---\n gcc/ChangeLog | 12 ++++++++++++\n gcc/config/s390/predicates.md | 7 +++++++\n gcc/config/s390/vector.md | 39 ++++++++++++++++++++++++++++++++-------\n gcc/config/s390/vx-builtins.md | 23 +++++++++++++----------\n 4 files changed, 64 insertions(+), 17 deletions(-)", "diff": "diff --git a/gcc/ChangeLog b/gcc/ChangeLog\nindex dcee7cb..7843857 100644\n--- a/gcc/ChangeLog\n+++ b/gcc/ChangeLog\n@@ -1,5 +1,17 @@\n 2017-09-26 Andreas Krebbel <krebbel@linux.vnet.ibm.com>\n \n+\t* config/s390/predicates.md (\"const_shift_by_byte_operand\"): New\n+\tpredicate.\n+\t* config/s390/vector.md (\"*vec_srb<mode>\"): Change modes to V_128\n+\tand V16QI.\n+\t(\"*vec_slb<mode>\"): New insn pattern.\n+\t(\"vec_shr_<mode>\"): New expander.\n+\t* config/s390/vx-builtins.md (\"vec_slb<mode>\"): Turn into expander\n+\tand force the shift count operand to V16QImode.\n+\t(\"vec_srb<mode>\"): Set shift count mode to V16QI.\n+\n+2017-09-26 Andreas Krebbel <krebbel@linux.vnet.ibm.com>\n+\n \t* config/s390/vector.md (\"vec_widen_umult_lo_<mode>\")\n \t(\"vec_widen_umult_hi_<mode>\", \"vec_widen_smult_lo_<mode>\")\n \t(\"vec_widen_smult_hi_<mode>\"): New expander definitions.\ndiff --git a/gcc/config/s390/predicates.md b/gcc/config/s390/predicates.md\nindex db966dd..bbff8d8 100644\n--- a/gcc/config/s390/predicates.md\n+++ b/gcc/config/s390/predicates.md\n@@ -508,3 +508,10 @@\n }\n return true;\n })\n+\n+(define_predicate \"const_shift_by_byte_operand\"\n+ (match_code \"const_int\")\n+{\n+ unsigned HOST_WIDE_INT val = INTVAL (op);\n+ return val <= 128 && val % 8 == 0;\n+})\ndiff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md\nindex 29131cd..e61bb88 100644\n--- a/gcc/config/s390/vector.md\n+++ b/gcc/config/s390/vector.md\n@@ -980,15 +980,43 @@\n \n ; Pattern used by e.g. popcount\n (define_insn \"*vec_srb<mode>\"\n- [(set (match_operand:V_HW 0 \"register_operand\" \"=v\")\n-\t(unspec:V_HW [(match_operand:V_HW 1 \"register_operand\" \"v\")\n-\t\t (match_operand:<tointvec> 2 \"register_operand\" \"v\")]\n-\t\t UNSPEC_VEC_SRLB))]\n+ [(set (match_operand:V_128 0 \"register_operand\" \"=v\")\n+\t(unspec:V_128 [(match_operand:V_128 1 \"register_operand\" \"v\")\n+\t\t (match_operand:V16QI 2 \"register_operand\" \"v\")]\n+\t\t UNSPEC_VEC_SRLB))]\n \"TARGET_VX\"\n \"vsrlb\\t%v0,%v1,%v2\"\n [(set_attr \"op_type\" \"VRR\")])\n \n \n+; Vector shift left by byte\n+\n+(define_insn \"*vec_slb<mode>\"\n+ [(set (match_operand:V_128 0 \"register_operand\" \"=v\")\n+\t(unspec:V_128 [(match_operand:V_128 1 \"register_operand\" \"v\")\n+\t\t (match_operand:V16QI 2 \"register_operand\" \"v\")]\n+\t\t UNSPEC_VEC_SLB))]\n+ \"TARGET_VX\"\n+ \"vslb\\t%v0,%v1,%v2\"\n+ [(set_attr \"op_type\" \"VRR\")])\n+\n+; vec_shr is defined as shift towards element 0\n+; this means it is a left shift on BE targets!\n+(define_expand \"vec_shr_<mode>\"\n+ [(set (match_dup 3)\n+\t(unspec:V16QI [(match_operand:SI 2 \"const_shift_by_byte_operand\" \"\")\n+\t\t (const_int 7)\n+\t\t (match_dup 3)]\n+\t\t UNSPEC_VEC_SET))\n+ (set (match_operand:V_128 0 \"register_operand\" \"\")\n+\t(unspec:V_128 [(match_operand:V_128 1 \"register_operand\" \"\")\n+\t\t (match_dup 3)]\n+\t\t UNSPEC_VEC_SLB))]\n+ \"TARGET_VX\"\n+ {\n+ operands[3] = gen_reg_rtx(V16QImode);\n+ })\n+\n ; vmnb, vmnh, vmnf, vmng\n (define_insn \"smin<mode>3\"\n [(set (match_operand:VI 0 \"register_operand\" \"=v\")\n@@ -1779,9 +1807,6 @@\n ; reduc_umin\n ; reduc_umax\n \n-; vec_shl vrep + vsl\n-; vec_shr\n-\n ; vec_pack_sfix_trunc: convert + pack ?\n ; vec_pack_ufix_trunc\n ; vec_unpacks_float_hi\ndiff --git a/gcc/config/s390/vx-builtins.md b/gcc/config/s390/vx-builtins.md\nindex 54796df..4c157e3 100644\n--- a/gcc/config/s390/vx-builtins.md\n+++ b/gcc/config/s390/vx-builtins.md\n@@ -1005,15 +1005,16 @@\n \n ; Vector shift left by byte\n \n-(define_insn \"vec_slb<mode>\"\n- [(set (match_operand:V_HW 0 \"register_operand\" \"=v\")\n-\t(unspec:V_HW [(match_operand:V_HW 1 \"register_operand\" \"v\")\n-\t\t (match_operand:<tointvec> 2 \"register_operand\" \"v\")]\n+; Pattern definition in vector.md, see vec_vslb\n+(define_expand \"vec_slb<mode>\"\n+ [(set (match_operand:V_HW 0 \"register_operand\" \"\")\n+\t(unspec:V_HW [(match_operand:V_HW 1 \"register_operand\" \"\")\n+\t\t (match_operand:<tointvec> 2 \"register_operand\" \"\")]\n \t\t UNSPEC_VEC_SLB))]\n \"TARGET_VX\"\n- \"vslb\\t%v0,%v1,%v2\"\n- [(set_attr \"op_type\" \"VRR\")])\n-\n+{\n+ PUT_MODE (operands[2], V16QImode);\n+})\n \n ; Vector shift left double by byte\n \n@@ -1076,14 +1077,16 @@\n \n ; Vector shift right logical by byte\n \n-; Pattern definition in vector.md\n+; Pattern definition in vector.md, see vec_vsrb\n (define_expand \"vec_srb<mode>\"\n [(set (match_operand:V_HW 0 \"register_operand\" \"\")\n \t(unspec:V_HW [(match_operand:V_HW 1 \"register_operand\" \"\")\n \t\t (match_operand:<tointvec> 2 \"register_operand\" \"\")]\n \t\t UNSPEC_VEC_SRLB))]\n- \"TARGET_VX\")\n-\n+ \"TARGET_VX\"\n+{\n+ PUT_MODE (operands[2], V16QImode);\n+})\n \n ; Vector subtract\n \n", "prefixes": [ "3/8" ] }