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GET /api/patches/818315/?format=api
{ "id": 818315, "url": "http://patchwork.ozlabs.org/api/patches/818315/?format=api", "web_url": "http://patchwork.ozlabs.org/project/sparclinux/patch/85aa907b56405a6a58a6d0f6935cd8cb473608a9.1506089472.git.khalid.aziz@oracle.com/", "project": { "id": 10, "url": "http://patchwork.ozlabs.org/api/projects/10/?format=api", "name": "Linux SPARC Development ", "link_name": "sparclinux", "list_id": "sparclinux.vger.kernel.org", "list_email": "sparclinux@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<85aa907b56405a6a58a6d0f6935cd8cb473608a9.1506089472.git.khalid.aziz@oracle.com>", "list_archive_url": null, "date": "2017-09-25T16:48:54", "name": "[v8,3/9] sparc64: Add support for ADI register fields, ASIs and traps", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "661ffc59defcb69adc4300f70bab14519311c090", "submitter": { "id": 42386, "url": "http://patchwork.ozlabs.org/api/people/42386/?format=api", "name": "Khalid Aziz", "email": "khalid.aziz@oracle.com" }, "delegate": { "id": 34, "url": "http://patchwork.ozlabs.org/api/users/34/?format=api", "username": "davem", "first_name": "David", "last_name": "Miller", "email": "davem@davemloft.net" }, "mbox": "http://patchwork.ozlabs.org/project/sparclinux/patch/85aa907b56405a6a58a6d0f6935cd8cb473608a9.1506089472.git.khalid.aziz@oracle.com/mbox/", "series": [ { "id": 4990, "url": "http://patchwork.ozlabs.org/api/series/4990/?format=api", "web_url": "http://patchwork.ozlabs.org/project/sparclinux/list/?series=4990", "date": "2017-09-25T16:48:55", "name": "Application Data Integrity feature introduced by SPARC M7", "version": 8, "mbox": "http://patchwork.ozlabs.org/series/4990/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/818315/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/818315/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<sparclinux-owner@vger.kernel.org>", "X-Original-To": "patchwork-incoming@ozlabs.org", "Delivered-To": "patchwork-incoming@ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=sparclinux-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y199p6b9Bz9t5c\n\tfor <patchwork-incoming@ozlabs.org>;\n\tTue, 26 Sep 2017 02:52:30 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S936190AbdIYQvr (ORCPT <rfc822;patchwork-incoming@ozlabs.org>);\n\tMon, 25 Sep 2017 12:51:47 -0400", "from userp1040.oracle.com ([156.151.31.81]:18694 \"EHLO\n\tuserp1040.oracle.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1754094AbdIYQvT (ORCPT\n\t<rfc822; sparclinux@vger.kernel.org>); Mon, 25 Sep 2017 12:51:19 -0400", "from aserv0022.oracle.com (aserv0022.oracle.com [141.146.126.234])\n\tby userp1040.oracle.com (Sentrion-MTA-4.3.2/Sentrion-MTA-4.3.2)\n\twith ESMTP id v8PGp8bW018302\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256\n\tverify=OK); Mon, 25 Sep 2017 16:51:08 GMT", "from aserv0121.oracle.com (aserv0121.oracle.com [141.146.126.235])\n\tby aserv0022.oracle.com (8.14.4/8.14.4) with ESMTP id\n\tv8PGp7fn018434\n\t(version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256\n\tverify=OK); Mon, 25 Sep 2017 16:51:07 GMT", "from abhmp0019.oracle.com (abhmp0019.oracle.com [141.146.116.25])\n\tby aserv0121.oracle.com (8.14.4/8.13.8) with ESMTP id\n\tv8PGp6Q3028500; Mon, 25 Sep 2017 16:51:06 GMT", "from concerto.us.oracle.com (/24.9.64.241)\n\tby default (Oracle Beehive Gateway v4.0)\n\twith ESMTP ; Mon, 25 Sep 2017 09:51:06 -0700" ], "From": "Khalid Aziz <khalid.aziz@oracle.com>", "To": "davem@davemloft.net, dave.hansen@linux.intel.com", "Cc": "Khalid Aziz <khalid.aziz@oracle.com>, mhocko@suse.com,\n\tchris.hyser@oracle.com, tushar.n.dave@oracle.com,\n\tsowmini.varadhan@oracle.com, mingo@kernel.org,\n\tkirill.shutemov@linux.intel.com, nitin.m.gupta@oracle.com,\n\ttom.hromatka@oracle.com, eric.saint.etienne@oracle.com,\n\tallen.pais@oracle.com, rob.gardner@oracle.com,\n\tdavid.j.aldridge@oracle.com, babu.moger@oracle.com,\n\tpaul.gortmaker@windriver.com, bob.picco@oracle.com,\n\tsteven.sistare@oracle.com, pasha.tatashin@oracle.com,\n\tLiam.Howlett@oracle.com, vegard.nossum@oracle.com,\n\tdan.carpenter@oracle.com, sparclinux@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, Khalid Aziz <khalid@gonehiking.org>", "Subject": "[PATCH v8 3/9] sparc64: Add support for ADI register fields,\n\tASIs and traps", "Date": "Mon, 25 Sep 2017 10:48:54 -0600", "Message-Id": "<85aa907b56405a6a58a6d0f6935cd8cb473608a9.1506089472.git.khalid.aziz@oracle.com>", "X-Mailer": "git-send-email 2.11.0", "In-Reply-To": [ "<cover.1506089472.git.khalid.aziz@oracle.com>", "<cover.1506089472.git.khalid.aziz@oracle.com>" ], "References": [ "<cover.1506089472.git.khalid.aziz@oracle.com>", "<cover.1506089472.git.khalid.aziz@oracle.com>" ], "X-Source-IP": "aserv0022.oracle.com [141.146.126.234]", "Sender": "sparclinux-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<sparclinux.vger.kernel.org>", "X-Mailing-List": "sparclinux@vger.kernel.org" }, "content": "SPARC M7 processor adds new control register fields, ASIs and a new\ntrap to support the ADI (Application Data Integrity) feature. This\npatch adds definitions for these register fields, ASIs and a handler\nfor the new precise memory corruption detected trap.\n\nSigned-off-by: Khalid Aziz <khalid.aziz@oracle.com>\nCc: Khalid Aziz <khalid@gonehiking.org>\n---\nv8:\n\t- Minor print formatting change as suggested by checkpatch\nv6:\n\t- Added a missing nop in the delay slot in sun4v_mcd_detect_precise\n\nv5:\n\t- Fixed indentation issues in assembly code\n\nv4:\n\t- Broke patch up into smaller patches\n\nv3:\n\t- Removed CONFIG_SPARC_ADI\n\t- Replaced prctl commands with mprotect\n\t- Added auxiliary vectors for ADI parameters\n\t- Enabled ADI for swappable pages\n\nv2:\n\t- Fixed a build error\n\n arch/sparc/include/asm/hypervisor.h | 2 ++\n arch/sparc/include/asm/pgtable_64.h | 2 ++\n arch/sparc/include/asm/ttable.h | 10 +++++++\n arch/sparc/include/uapi/asm/asi.h | 5 ++++\n arch/sparc/include/uapi/asm/pstate.h | 10 +++++++\n arch/sparc/kernel/entry.h | 3 ++\n arch/sparc/kernel/head_64.S | 1 +\n arch/sparc/kernel/sun4v_mcd.S | 17 ++++++++++++\n arch/sparc/kernel/traps_64.c | 54 ++++++++++++++++++++++++++++++++++++\n arch/sparc/kernel/ttable_64.S | 6 ++--\n 10 files changed, 108 insertions(+), 2 deletions(-)\n create mode 100644 arch/sparc/kernel/sun4v_mcd.S", "diff": "diff --git a/arch/sparc/include/asm/hypervisor.h b/arch/sparc/include/asm/hypervisor.h\nindex 73cb8978df58..31782f7996b3 100644\n--- a/arch/sparc/include/asm/hypervisor.h\n+++ b/arch/sparc/include/asm/hypervisor.h\n@@ -547,6 +547,8 @@ struct hv_fault_status {\n #define HV_FAULT_TYPE_RESV1\t13\n #define HV_FAULT_TYPE_UNALIGNED\t14\n #define HV_FAULT_TYPE_INV_PGSZ\t15\n+#define HV_FAULT_TYPE_MCD\t17\n+#define HV_FAULT_TYPE_MCD_DIS\t18\n /* Values 16 --> -2 are reserved. */\n #define HV_FAULT_TYPE_MULTIPLE\t-1\n \ndiff --git a/arch/sparc/include/asm/pgtable_64.h b/arch/sparc/include/asm/pgtable_64.h\nindex 6fbd931f0570..af045061f41e 100644\n--- a/arch/sparc/include/asm/pgtable_64.h\n+++ b/arch/sparc/include/asm/pgtable_64.h\n@@ -163,6 +163,8 @@ bool kern_addr_valid(unsigned long addr);\n #define _PAGE_E_4V\t _AC(0x0000000000000800,UL) /* side-Effect */\n #define _PAGE_CP_4V\t _AC(0x0000000000000400,UL) /* Cacheable in P-Cache */\n #define _PAGE_CV_4V\t _AC(0x0000000000000200,UL) /* Cacheable in V-Cache */\n+/* Bit 9 is used to enable MCD corruption detection instead on M7 */\n+#define _PAGE_MCD_4V _AC(0x0000000000000200,UL) /* Memory Corruption */\n #define _PAGE_P_4V\t _AC(0x0000000000000100,UL) /* Privileged Page */\n #define _PAGE_EXEC_4V\t _AC(0x0000000000000080,UL) /* Executable Page */\n #define _PAGE_W_4V\t _AC(0x0000000000000040,UL) /* Writable */\ndiff --git a/arch/sparc/include/asm/ttable.h b/arch/sparc/include/asm/ttable.h\nindex 82e7df296abc..d6510ab8fa4d 100644\n--- a/arch/sparc/include/asm/ttable.h\n+++ b/arch/sparc/include/asm/ttable.h\n@@ -218,6 +218,16 @@\n \tnop;\t\t\t\t\t\t\\\n \tnop;\n \n+#define SUN4V_MCD_PRECISE\t\t\t\t\\\n+\tldxa\t[%g0] ASI_SCRATCHPAD, %g2;\t\t\\\n+\tldx\t[%g2 + HV_FAULT_D_ADDR_OFFSET], %g4;\t\\\n+\tldx\t[%g2 + HV_FAULT_D_CTX_OFFSET], %g5;\t\\\n+\tba,pt\t%xcc, etrap;\t\t\t\t\\\n+\t rd\t%pc, %g7;\t\t\t\t\\\n+\tba,pt\t%xcc, sun4v_mcd_detect_precise;\t\t\\\n+\t nop;\t\t\t\t\t\t\\\n+\tnop;\n+\n /* Before touching these macros, you owe it to yourself to go and\n * see how arch/sparc64/kernel/winfixup.S works... -DaveM\n *\ndiff --git a/arch/sparc/include/uapi/asm/asi.h b/arch/sparc/include/uapi/asm/asi.h\nindex 7ad7203deaec..2bcdaa5321d3 100644\n--- a/arch/sparc/include/uapi/asm/asi.h\n+++ b/arch/sparc/include/uapi/asm/asi.h\n@@ -144,6 +144,8 @@\n * ASIs, \"(4V)\" designates SUN4V specific ASIs. \"(NG4)\" designates SPARC-T4\n * and later ASIs.\n */\n+#define ASI_MCD_PRIV_PRIMARY\t0x02 /* (NG7) Privileged MCD version VA\t*/\n+#define ASI_MCD_REAL\t\t0x05 /* (NG7) Privileged MCD version PA\t*/\n #define ASI_PHYS_USE_EC\t\t0x14 /* PADDR, E-cachable\t\t*/\n #define ASI_PHYS_BYPASS_EC_E\t0x15 /* PADDR, E-bit\t\t\t*/\n #define ASI_BLK_AIUP_4V\t\t0x16 /* (4V) Prim, user, block ld/st\t*/\n@@ -244,6 +246,9 @@\n #define ASI_UDBL_CONTROL_R\t0x7f /* External UDB control regs rd low*/\n #define ASI_INTR_R\t\t0x7f /* IRQ vector dispatch read\t*/\n #define ASI_INTR_DATAN_R\t0x7f /* (III) In irq vector data reg N\t*/\n+#define ASI_MCD_PRIMARY\t\t0x90 /* (NG7) MCD version load/store\t*/\n+#define ASI_MCD_ST_BLKINIT_PRIMARY\t\\\n+\t\t\t\t0x92 /* (NG7) MCD store BLKINIT primary\t*/\n #define ASI_PIC\t\t\t0xb0 /* (NG4) PIC registers\t\t*/\n #define ASI_PST8_P\t\t0xc0 /* Primary, 8 8-bit, partial\t*/\n #define ASI_PST8_S\t\t0xc1 /* Secondary, 8 8-bit, partial\t*/\ndiff --git a/arch/sparc/include/uapi/asm/pstate.h b/arch/sparc/include/uapi/asm/pstate.h\nindex cf832e14aa05..d0521db9bb6f 100644\n--- a/arch/sparc/include/uapi/asm/pstate.h\n+++ b/arch/sparc/include/uapi/asm/pstate.h\n@@ -10,7 +10,12 @@\n * -----------------------------------------------------------------------\n * 63 12 11 10 9 8 7 6 5 4 3 2 1 0\n */\n+/* IG on V9 conflicts with MCDE on M7. PSTATE_MCDE will only be used on\n+ * processors that support ADI which do not use IG, hence there is no\n+ * functional conflict\n+ */\n #define PSTATE_IG _AC(0x0000000000000800,UL) /* Interrupt Globals.\t*/\n+#define PSTATE_MCDE _AC(0x0000000000000800,UL) /* MCD Enable\t\t*/\n #define PSTATE_MG _AC(0x0000000000000400,UL) /* MMU Globals.\t\t*/\n #define PSTATE_CLE _AC(0x0000000000000200,UL) /* Current Little Endian.*/\n #define PSTATE_TLE _AC(0x0000000000000100,UL) /* Trap Little Endian.\t*/\n@@ -47,7 +52,12 @@\n #define TSTATE_ASI\t_AC(0x00000000ff000000,UL) /* AddrSpace ID.\t*/\n #define TSTATE_PIL\t_AC(0x0000000000f00000,UL) /* %pil (Linux traps)*/\n #define TSTATE_PSTATE\t_AC(0x00000000000fff00,UL) /* PSTATE.\t\t*/\n+/* IG on V9 conflicts with MCDE on M7. TSTATE_MCDE will only be used on\n+ * processors that support ADI which do not support IG, hence there is\n+ * no functional conflict\n+ */\n #define TSTATE_IG\t_AC(0x0000000000080000,UL) /* Interrupt Globals.*/\n+#define TSTATE_MCDE\t_AC(0x0000000000080000,UL) /* MCD enable. */\n #define TSTATE_MG\t_AC(0x0000000000040000,UL) /* MMU Globals.\t*/\n #define TSTATE_CLE\t_AC(0x0000000000020000,UL) /* CurrLittleEndian.\t*/\n #define TSTATE_TLE\t_AC(0x0000000000010000,UL) /* TrapLittleEndian.\t*/\ndiff --git a/arch/sparc/kernel/entry.h b/arch/sparc/kernel/entry.h\nindex 0f679421b468..207846855a4d 100644\n--- a/arch/sparc/kernel/entry.h\n+++ b/arch/sparc/kernel/entry.h\n@@ -159,6 +159,9 @@ void sun4v_resum_overflow(struct pt_regs *regs);\n void sun4v_nonresum_error(struct pt_regs *regs,\n \t\t\t unsigned long offset);\n void sun4v_nonresum_overflow(struct pt_regs *regs);\n+void sun4v_mem_corrupt_detect_precise(struct pt_regs *regs,\n+\t\t\t\t unsigned long addr,\n+\t\t\t\t unsigned long context);\n \n extern unsigned long sun4v_err_itlb_vaddr;\n extern unsigned long sun4v_err_itlb_ctx;\ndiff --git a/arch/sparc/kernel/head_64.S b/arch/sparc/kernel/head_64.S\nindex 78e0211753d2..0bd326b6ca58 100644\n--- a/arch/sparc/kernel/head_64.S\n+++ b/arch/sparc/kernel/head_64.S\n@@ -883,6 +883,7 @@ sparc64_boot_end:\n #include \"helpers.S\"\n #include \"hvcalls.S\"\n #include \"sun4v_tlb_miss.S\"\n+#include \"sun4v_mcd.S\"\n #include \"sun4v_ivec.S\"\n #include \"ktlb.S\"\n #include \"tsb.S\"\ndiff --git a/arch/sparc/kernel/sun4v_mcd.S b/arch/sparc/kernel/sun4v_mcd.S\nnew file mode 100644\nindex 000000000000..92afb6248dbc\n--- /dev/null\n+++ b/arch/sparc/kernel/sun4v_mcd.S\n@@ -0,0 +1,17 @@\n+/* sun4v_mcd.S: Sun4v memory corruption detected precise exception handler\n+ *\n+ * Copyright (C) 2015 Bob Picco <bob.picco@oracle.com>\n+ * Copyright (C) 2015 Khalid Aziz <khalid.aziz@oracle.com>\n+ *\n+ * This work is licensed under the terms of the GNU GPL, version 2.\n+ */\n+\t.text\n+\t.align 32\n+\n+sun4v_mcd_detect_precise:\n+\tmov\t%l4, %o1\n+\tmov \t%l5, %o2\n+\tcall\tsun4v_mem_corrupt_detect_precise\n+\t add\t%sp, PTREGS_OFF, %o0\n+\tba,a,pt\t%xcc, rtrap\n+\t nop\ndiff --git a/arch/sparc/kernel/traps_64.c b/arch/sparc/kernel/traps_64.c\nindex ad31af1dd726..0fe0eed3cecb 100644\n--- a/arch/sparc/kernel/traps_64.c\n+++ b/arch/sparc/kernel/traps_64.c\n@@ -2605,6 +2605,60 @@ void sun4v_do_mna(struct pt_regs *regs, unsigned long addr, unsigned long type_c\n \tforce_sig_info(SIGBUS, &info, current);\n }\n \n+/* sun4v_mem_corrupt_detect_precise() - Handle precise exception on an ADI\n+ * tag mismatch.\n+ *\n+ * ADI version tag mismatch on a load from memory always results in a\n+ * precise exception. Tag mismatch on a store to memory will result in\n+ * precise exception if MCDPER or PMCDPER is set to 1.\n+ */\n+void sun4v_mem_corrupt_detect_precise(struct pt_regs *regs, unsigned long addr,\n+\t\t\t\t unsigned long context)\n+{\n+\tsiginfo_t info;\n+\n+\tif (notify_die(DIE_TRAP, \"memory corruption precise exception\", regs,\n+\t\t 0, 0x8, SIGSEGV) == NOTIFY_STOP)\n+\t\treturn;\n+\n+\tif (regs->tstate & TSTATE_PRIV) {\n+\t\t/* MCD exception could happen because the task was running\n+\t\t * a system call with MCD enabled and passed a non-versioned\n+\t\t * pointer or pointer with bad version tag to the system\n+\t\t * call.\n+\t\t */\n+\t\tconst struct exception_table_entry *entry;\n+\n+\t\tentry = search_exception_tables(regs->tpc);\n+\t\tif (entry) {\n+\t\t\t/* Looks like a bad syscall parameter */\n+#ifdef DEBUG_EXCEPTIONS\n+\t\t\tpr_emerg(\"Exception: PC<%016lx> faddr<UNKNOWN>\\n\",\n+\t\t\t\t regs->tpc);\n+\t\t\tpr_emerg(\"EX_TABLE: insn<%016lx> fixup<%016lx>\\n\",\n+\t\t\t\t regs->tpc, entry->fixup);\n+#endif\n+\t\t\tregs->tpc = entry->fixup;\n+\t\t\tregs->tnpc = regs->tpc + 4;\n+\t\t\treturn;\n+\t\t}\n+\t\tpr_emerg(\"%s: ADDR[%016lx] CTX[%lx], going.\\n\",\n+\t\t\t __func__, addr, context);\n+\t\tdie_if_kernel(\"MCD precise\", regs);\n+\t}\n+\n+\tif (test_thread_flag(TIF_32BIT)) {\n+\t\tregs->tpc &= 0xffffffff;\n+\t\tregs->tnpc &= 0xffffffff;\n+\t}\n+\tinfo.si_signo = SIGSEGV;\n+\tinfo.si_code = SEGV_ADIPERR;\n+\tinfo.si_errno = 0;\n+\tinfo.si_addr = (void __user *) addr;\n+\tinfo.si_trapno = 0;\n+\tforce_sig_info(SIGSEGV, &info, current);\n+}\n+\n void do_privop(struct pt_regs *regs)\n {\n \tenum ctx_state prev_state = exception_enter();\ndiff --git a/arch/sparc/kernel/ttable_64.S b/arch/sparc/kernel/ttable_64.S\nindex efe93ab4a9c0..36a9708f93d9 100644\n--- a/arch/sparc/kernel/ttable_64.S\n+++ b/arch/sparc/kernel/ttable_64.S\n@@ -25,8 +25,10 @@ tl0_ill:\tmembar #Sync\n \t\tTRAP_7INSNS(do_illegal_instruction)\n tl0_privop:\tTRAP(do_privop)\n tl0_resv012:\tBTRAP(0x12) BTRAP(0x13) BTRAP(0x14) BTRAP(0x15) BTRAP(0x16) BTRAP(0x17)\n-tl0_resv018:\tBTRAP(0x18) BTRAP(0x19) BTRAP(0x1a) BTRAP(0x1b) BTRAP(0x1c) BTRAP(0x1d)\n-tl0_resv01e:\tBTRAP(0x1e) BTRAP(0x1f)\n+tl0_resv018:\tBTRAP(0x18) BTRAP(0x19)\n+tl0_mcd:\tSUN4V_MCD_PRECISE\n+tl0_resv01b:\tBTRAP(0x1b)\n+tl0_resv01c:\tBTRAP(0x1c) BTRAP(0x1d)\tBTRAP(0x1e) BTRAP(0x1f)\n tl0_fpdis:\tTRAP_NOSAVE(do_fpdis)\n tl0_fpieee:\tTRAP_SAVEFPU(do_fpieee)\n tl0_fpother:\tTRAP_NOSAVE(do_fpother_check_fitos)\n", "prefixes": [ "v8", "3/9" ] }