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GET /api/patches/818277/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
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{
    "id": 818277,
    "url": "http://patchwork.ozlabs.org/api/patches/818277/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-mtd/patch/20170925145352.13145-3-miquel.raynal@free-electrons.com/",
    "project": {
        "id": 3,
        "url": "http://patchwork.ozlabs.org/api/projects/3/?format=api",
        "name": "Linux MTD development",
        "link_name": "linux-mtd",
        "list_id": "linux-mtd.lists.infradead.org",
        "list_email": "linux-mtd@lists.infradead.org",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20170925145352.13145-3-miquel.raynal@free-electrons.com>",
    "list_archive_url": null,
    "date": "2017-09-25T14:53:51",
    "name": "[2/3] mtd: nand: pxa3xx: enable NAND controller if the SoC needs it",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": false,
    "hash": "706db5abf535338a6616e8b46684fe67c8f2cc8d",
    "submitter": {
        "id": 71917,
        "url": "http://patchwork.ozlabs.org/api/people/71917/?format=api",
        "name": "Miquel Raynal",
        "email": "miquel.raynal@free-electrons.com"
    },
    "delegate": {
        "id": 58324,
        "url": "http://patchwork.ozlabs.org/api/users/58324/?format=api",
        "username": "bbrezillon",
        "first_name": "Boris",
        "last_name": "Brezillon",
        "email": "boris.brezillon@free-electrons.com"
    },
    "mbox": "http://patchwork.ozlabs.org/project/linux-mtd/patch/20170925145352.13145-3-miquel.raynal@free-electrons.com/mbox/",
    "series": [
        {
            "id": 4976,
            "url": "http://patchwork.ozlabs.org/api/series/4976/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/linux-mtd/list/?series=4976",
            "date": "2017-09-25T14:53:50",
            "name": "Enable NAND on Armada-7040-DB board",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/4976/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/818277/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/818277/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org>",
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        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe:\n\tList-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References:\n\tIn-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID:\n\tContent-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc\n\t:Resent-Message-ID:List-Owner;\n\tbh=f9ZPorFjA95U07MiWeXE8d5UuqNWshTUb8CNmRL+I/w=;\n\tb=LOZNGVr9W640q6KGl5e+RtFKml\n\t/iVjDXmSCPwmxDltoN6VjNgkp6E98aLaW+0PBerynJTaDX1+HLXLzihJxdxMZ49SJJQgptOHmmvwK\n\tiPnHaoGTI+y1fAvZ6QiV+o3XBPqda84ejQqpxLBueyXkMeyHrBO5i6/WJD5WxjWPDux9/7u6x5Otx\n\tfMrb868tsSqZvgpAlC41QhfMWM7FLqHsB3oYYnXCPn/hQ82MufIR/uRERe1Hk/q1orRN3eMpbIitM\n\taPPhEU+CcCWjglZ0Xhb02nI30tGkEZ4uL29DxAQTeWfvabk7Eg/b1mmLVYneK+gxTmn25ljHsiXNo\n\tEJj7vtEQ==;",
        "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com",
        "X-Spam-Level": "",
        "X-Spam-Status": "No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT,\n\tURIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0",
        "From": "Miquel Raynal <miquel.raynal@free-electrons.com>",
        "To": "David Woodhouse <dwmw2@infradead.org>,\n\tBrian Norris <computersforpeace@gmail.com>,\n\tBoris Brezillon <boris.brezillon@free-electrons.com>,\n\tMarek Vasut <marek.vasut@gmail.com>,\n\tRichard Weinberger <richard@nod.at>, \n\tCyrille Pitchen <cyrille.pitchen@wedev4u.fr>,\n\tJason Cooper <jason@lakedaemon.net>, Andrew Lunn <andrew@lunn.ch>,\n\tGregory Clement <gregory.clement@free-electrons.com>,\n\tSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,\n\tEzequiel Garcia <ezequiel.garcia@free-electrons.com>,\n\tlinux-mtd@lists.infradead.org, devicetree@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org",
        "Subject": "[PATCH 2/3] mtd: nand: pxa3xx: enable NAND controller if the SoC\n\tneeds it",
        "Date": "Mon, 25 Sep 2017 16:53:51 +0200",
        "Message-Id": "<20170925145352.13145-3-miquel.raynal@free-electrons.com>",
        "X-Mailer": "git-send-email 2.11.0",
        "In-Reply-To": "<20170925145352.13145-1-miquel.raynal@free-electrons.com>",
        "References": "<20170925145352.13145-1-miquel.raynal@free-electrons.com>",
        "X-CRM114-Version": "20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ",
        "X-CRM114-CacheID": "sfid-20170925_075457_582829_D5447198 ",
        "X-CRM114-Status": "GOOD (  16.06  )",
        "X-Spam-Score": "-1.9 (-)",
        "X-Spam-Report": "SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details:   (-1.9 points)\n\tpts rule name              description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 SPF_PASS               SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00               BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]",
        "X-BeenThere": "linux-mtd@lists.infradead.org",
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        "Precedence": "list",
        "List-Id": "Linux MTD discussion mailing list <linux-mtd.lists.infradead.org>",
        "List-Unsubscribe": "<http://lists.infradead.org/mailman/options/linux-mtd>,\n\t<mailto:linux-mtd-request@lists.infradead.org?subject=unsubscribe>",
        "List-Archive": "<http://lists.infradead.org/pipermail/linux-mtd/>",
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        "List-Subscribe": "<http://lists.infradead.org/mailman/listinfo/linux-mtd>,\n\t<mailto:linux-mtd-request@lists.infradead.org?subject=subscribe>",
        "Cc": "Thomas Petazzoni <thomas.petazzoni@free-electrons.com>,\n\tNadav Haklai <nadavh@marvell.com>,\n\tAntoine Tenart <antoine.tenart@free-electrons.com>,\n\tMiquel Raynal <miquel.raynal@free-electrons.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain; charset=\"us-ascii\"",
        "Content-Transfer-Encoding": "7bit",
        "Sender": "\"linux-mtd\" <linux-mtd-bounces@lists.infradead.org>",
        "Errors-To": "linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org"
    },
    "content": "Marvell recent SoCs like A7k/A8k do not boot with NAND flash\ncontroller activated by default. Enabling the controller is a matter of\nwriting in a system controller register that may also be used for other\nNAND related choices.\n\nThis change is needed to stay bootloader independent.\n\nSigned-off-by: Miquel Raynal <miquel.raynal@free-electrons.com>\n---\n drivers/mtd/nand/pxa3xx_nand.c | 41 +++++++++++++++++++++++++++++++++++++----\n 1 file changed, 37 insertions(+), 4 deletions(-)",
    "diff": "diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c\nindex 85cff68643e0..90b9a9ccbe60 100644\n--- a/drivers/mtd/nand/pxa3xx_nand.c\n+++ b/drivers/mtd/nand/pxa3xx_nand.c\n@@ -30,6 +30,8 @@\n #include <linux/of.h>\n #include <linux/of_device.h>\n #include <linux/platform_data/mtd-nand-pxa3xx.h>\n+#include <linux/mfd/syscon.h>\n+#include <linux/regmap.h>\n \n #define\tCHIP_DELAY_TIMEOUT\tmsecs_to_jiffies(200)\n #define NAND_STOP_DELAY\t\tmsecs_to_jiffies(40)\n@@ -45,6 +47,10 @@\n  */\n #define INIT_BUFFER_SIZE\t2048\n \n+/* System control register and bit to enable NAND on some SoCs */\n+#define GENCONF_SOC_DEVICE_MUX\t0x208\n+#define GENCONF_SOC_DEVICE_MUX_NFC_EN BIT(0)\n+\n /* registers and bit definitions */\n #define NDCR\t\t(0x00) /* Control register */\n #define NDTR0CS0\t(0x04) /* Timing Parameter 0 for CS0 */\n@@ -174,6 +180,7 @@ enum {\n enum pxa3xx_nand_variant {\n \tPXA3XX_NAND_VARIANT_PXA,\n \tPXA3XX_NAND_VARIANT_ARMADA370,\n+\tPXA3XX_NAND_VARIANT_ARMADA_8K,\n };\n \n struct pxa3xx_nand_host {\n@@ -425,6 +432,10 @@ static const struct of_device_id pxa3xx_nand_dt_ids[] = {\n \t\t.compatible = \"marvell,armada370-nand\",\n \t\t.data       = (void *)PXA3XX_NAND_VARIANT_ARMADA370,\n \t},\n+\t{\n+\t\t.compatible = \"marvell,armada-8k-nand\",\n+\t\t.data       = (void *)PXA3XX_NAND_VARIANT_ARMADA_8K,\n+\t},\n \t{}\n };\n MODULE_DEVICE_TABLE(of, pxa3xx_nand_dt_ids);\n@@ -825,7 +836,8 @@ static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)\n \t\tinfo->retcode = ERR_UNCORERR;\n \tif (status & NDSR_CORERR) {\n \t\tinfo->retcode = ERR_CORERR;\n-\t\tif (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 &&\n+\t\tif ((info->variant == PXA3XX_NAND_VARIANT_ARMADA370 ||\n+\t\t     info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K) &&\n \t\t    info->ecc_bch)\n \t\t\tinfo->ecc_err_cnt = NDSR_ERR_CNT(status);\n \t\telse\n@@ -888,7 +900,8 @@ static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)\n \t\tnand_writel(info, NDCB0, info->ndcb2);\n \n \t\t/* NDCB3 register is available in NFCv2 (Armada 370/XP SoC) */\n-\t\tif (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)\n+\t\tif (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 ||\n+\t\t    info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K)\n \t\t\tnand_writel(info, NDCB0, info->ndcb3);\n \t}\n \n@@ -1671,7 +1684,8 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)\n \t\tchip->options |= NAND_BUSWIDTH_16;\n \n \t/* Device detection must be done with ECC disabled */\n-\tif (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)\n+\tif (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 ||\n+\t    info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K)\n \t\tnand_writel(info, NDECCCTRL, 0x0);\n \n \tif (pdata->flash_bbt)\n@@ -1709,7 +1723,8 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)\n \t * (aka splitted) command handling,\n \t */\n \tif (mtd->writesize > PAGE_CHUNK_SIZE) {\n-\t\tif (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) {\n+\t\tif (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 ||\n+\t\t    info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K) {\n \t\t\tchip->cmdfunc = nand_cmdfunc_extended;\n \t\t} else {\n \t\t\tdev_err(&info->pdev->dev,\n@@ -1928,6 +1943,24 @@ static int pxa3xx_nand_probe_dt(struct platform_device *pdev)\n \tif (!of_id)\n \t\treturn 0;\n \n+\t/*\n+\t * Some SoCs like A7k/A8k need to enable manually the NAND\n+\t * controller to avoid being bootloader dependent. This is done\n+\t * through the use of a single bit in the System Functions registers.\n+\t */\n+\tif (pxa3xx_nand_get_variant(pdev) == PXA3XX_NAND_VARIANT_ARMADA_8K) {\n+\t\tstruct regmap *sysctrl_base = syscon_regmap_lookup_by_phandle(\n+\t\t\tpdev->dev.of_node, \"marvell,system-controller\");\n+\t\tu32 reg;\n+\n+\t\tif (IS_ERR(sysctrl_base))\n+\t\t\treturn PTR_ERR(sysctrl_base);\n+\n+\t\tregmap_read(sysctrl_base, GENCONF_SOC_DEVICE_MUX, &reg);\n+\t\treg |= GENCONF_SOC_DEVICE_MUX_NFC_EN;\n+\t\tregmap_write(sysctrl_base, GENCONF_SOC_DEVICE_MUX, reg);\n+\t}\n+\n \tpdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);\n \tif (!pdata)\n \t\treturn -ENOMEM;\n",
    "prefixes": [
        "2/3"
    ]
}