Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/818139/?format=api
{ "id": 818139, "url": "http://patchwork.ozlabs.org/api/patches/818139/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-imx/patch/1506330344-31556-7-git-send-email-vladimir.murzin@arm.com/", "project": { "id": 19, "url": "http://patchwork.ozlabs.org/api/projects/19/?format=api", "name": "Linux IMX development", "link_name": "linux-imx", "list_id": "linux-imx-kernel.lists.patchwork.ozlabs.org", "list_email": "linux-imx-kernel@lists.patchwork.ozlabs.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1506330344-31556-7-git-send-email-vladimir.murzin@arm.com>", "list_archive_url": null, "date": "2017-09-25T09:05:42", "name": "[v3,6/8] ARM: V7M: Add support for MPU to M-class", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "81438e0f57bb092b43c08f83aa0bf8b7d3c318cc", "submitter": { "id": 65248, "url": "http://patchwork.ozlabs.org/api/people/65248/?format=api", "name": "Vladimir Murzin", "email": "vladimir.murzin@arm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-imx/patch/1506330344-31556-7-git-send-email-vladimir.murzin@arm.com/mbox/", "series": [ { "id": 4911, "url": "http://patchwork.ozlabs.org/api/series/4911/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-imx/list/?series=4911", "date": "2017-09-25T09:05:36", "name": "ARM: NOMMU: MPU updates", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/4911/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/818139/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/818139/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org>", "X-Original-To": "incoming-imx@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming-imx@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"gtHXgIvQ\"; dkim-atps=neutral" ], "Received": [ "from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y0yvP4cjBz9s7f\n\tfor <incoming-imx@patchwork.ozlabs.org>;\n\tMon, 25 Sep 2017 19:09:21 +1000 (AEST)", "from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dwPO8-00041r-LF; Mon, 25 Sep 2017 09:09:16 +0000", "from foss.arm.com ([217.140.101.70])\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dwPLi-0001XP-Ip for linux-arm-kernel@lists.infradead.org;\n\tMon, 25 Sep 2017 09:07:05 +0000", "from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249])\n\tby usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8B305174E;\n\tMon, 25 Sep 2017 02:06:15 -0700 (PDT)", "from bc-c11-3-12.euhpc.arm.com. (bc-c11-3-12.euhpc.arm.com\n\t[10.6.2.250])\n\tby usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id\n\t12BFB3F3E1; Mon, 25 Sep 2017 02:06:13 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:\n\tMessage-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=z4iL9+A1Hx1hWMCOLSLVzdHUVmsjImTDuwQv233k57g=;\n\tb=gtHXgIvQ4TFqiO\n\t8MCEZbcPXSthbE2sPtCau8y/06+fih0XNdtXiWPu2YMYqh66oAg+XMPYHubWMhMX2+aIkuQSvbZYg\n\tcraeCwXfZZjJ2QNwF1P0cJRE4gqQuItm8TDNMmthY4U+0OYkapGAHyCEFJgbU7Rf7OQ6+/+uMuEQH\n\task+hefUGy2Ppfbm1ESNv9Kvd1ZUTcKEpAWeqcGbsAZO+yHKKuj0JUNfO+Rqa/yGy0S+KiQ+2NwGx\n\tjz7JuRn6ZDWo7Yr7KEw1NHIeMJqLm/sX/jldZ6kN9fxmgnjdmRmD1+9/AtvxLaNOHmrN2TiNAqiUi\n\txXhmyn46nvd28HnKpQyw==;", "From": "Vladimir Murzin <vladimir.murzin@arm.com>", "To": "linux-arm-kernel@lists.infradead.org", "Subject": "[PATCH v3 6/8] ARM: V7M: Add support for MPU to M-class", "Date": "Mon, 25 Sep 2017 10:05:42 +0100", "Message-Id": "<1506330344-31556-7-git-send-email-vladimir.murzin@arm.com>", "X-Mailer": "git-send-email 2.0.0", "In-Reply-To": "<1506330344-31556-1-git-send-email-vladimir.murzin@arm.com>", "References": "<1506330344-31556-1-git-send-email-vladimir.murzin@arm.com>", "MIME-Version": "1.0", "X-CRM114-Version": "20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ", "X-CRM114-CacheID": "sfid-20170925_020647_346960_60006076 ", "X-CRM114-Status": "GOOD ( 16.48 )", "X-Spam-Score": "-6.9 (------)", "X-Spam-Report": "SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-6.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/,\n\thigh trust [217.140.101.70 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]", "X-BeenThere": "linux-arm-kernel@lists.infradead.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Unsubscribe": "<http://lists.infradead.org/mailman/options/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe>", "List-Archive": "<http://lists.infradead.org/pipermail/linux-arm-kernel/>", "List-Post": "<mailto:linux-arm-kernel@lists.infradead.org>", "List-Help": "<mailto:linux-arm-kernel-request@lists.infradead.org?subject=help>", "List-Subscribe": "<http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe>", "Cc": "alexandre.torgue@st.com, manabian@gmail.com, linux@armlinux.org.uk,\n\tstefan@agner.ch, kbuild-all@01.org, u.kleine-koenig@pengutronix.de,\n\tsza@esh.hu", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Sender": "\"linux-arm-kernel\" <linux-arm-kernel-bounces@lists.infradead.org>", "Errors-To": "linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org", "List-Id": "linux-imx-kernel.lists.patchwork.ozlabs.org" }, "content": "This patch makes it possible to use MPU with v7M cores.\n\nTested-by: Szemző András <sza@esh.hu>\nTested-by: Alexandre TORGUE <alexandre.torgue@st.com>\nSigned-off-by: Vladimir Murzin <vladimir.murzin@arm.com>\n---\n arch/arm/Kconfig-nommu | 4 +--\n arch/arm/include/asm/cputype.h | 10 ++++++++\n arch/arm/include/asm/v7m.h | 10 ++++++++\n arch/arm/kernel/head-nommu.S | 56 ++++++++++++++++++++++++++++++------------\n arch/arm/mm/pmsa-v7.c | 53 +++++++++++++++++++++++++++++++++++++--\n 5 files changed, 113 insertions(+), 20 deletions(-)", "diff": "diff --git a/arch/arm/Kconfig-nommu b/arch/arm/Kconfig-nommu\nindex 6d18395..930e000 100644\n--- a/arch/arm/Kconfig-nommu\n+++ b/arch/arm/Kconfig-nommu\n@@ -52,8 +52,8 @@ config REMAP_VECTORS_TO_RAM\n \n config ARM_MPU\n bool 'Use the ARM v7 PMSA Compliant MPU'\n- depends on !XIP_KERNEL && CPU_V7\n- default y\n+ depends on !XIP_KERNEL && (CPU_V7 || CPU_V7M)\n+ default y if CPU_V7\n help\n Some ARM systems without an MMU have instead a Memory Protection\n Unit (MPU) that defines the type and permissions for regions of\ndiff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h\nindex b62eaeb..abaac5e 100644\n--- a/arch/arm/include/asm/cputype.h\n+++ b/arch/arm/include/asm/cputype.h\n@@ -173,6 +173,11 @@ static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)\n \treturn read_cpuid(CPUID_CACHETYPE);\n }\n \n+static inline unsigned int __attribute_const__ read_cpuid_mputype(void)\n+{\n+\treturn read_cpuid(CPUID_MPUIR);\n+}\n+\n #elif defined(CONFIG_CPU_V7M)\n \n static inline unsigned int __attribute_const__ read_cpuid_id(void)\n@@ -185,6 +190,11 @@ static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)\n \treturn readl(BASEADDR_V7M_SCB + V7M_SCB_CTR);\n }\n \n+static inline unsigned int __attribute_const__ read_cpuid_mputype(void)\n+{\n+\treturn readl(BASEADDR_V7M_SCB + MPU_TYPE);\n+}\n+\n #else /* ifdef CONFIG_CPU_CP15 / elif defined(CONFIG_CPU_V7M) */\n \n static inline unsigned int __attribute_const__ read_cpuid_id(void)\ndiff --git a/arch/arm/include/asm/v7m.h b/arch/arm/include/asm/v7m.h\nindex 1fd775c..5de776c 100644\n--- a/arch/arm/include/asm/v7m.h\n+++ b/arch/arm/include/asm/v7m.h\n@@ -57,6 +57,16 @@\n #define\tV7M_SCB_CCSIDR\t\t0x80\t/* Cache size ID register */\n #define\tV7M_SCB_CSSELR\t\t0x84\t/* Cache size selection register */\n \n+/* Memory-mapped MPU registers for M-class */\n+#define MPU_TYPE\t\t0x90\n+#define MPU_CTRL\t\t0x94\n+#define MPU_CTRL_ENABLE\t\t1\n+#define MPU_CTRL_PRIVDEFENA\t(1 << 2)\n+\n+#define MPU_RNR\t\t\t0x98\n+#define MPU_RBAR\t\t0x9c\n+#define MPU_RASR\t\t0xa0\n+\n /* Cache opeartions */\n #define\tV7M_SCB_ICIALLU\t\t0x250\t/* I-cache invalidate all to PoU */\n #define\tV7M_SCB_ICIMVAU\t\t0x258\t/* I-cache invalidate by MVA to PoU */\ndiff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S\nindex f242ae5..8a0718f 100644\n--- a/arch/arm/kernel/head-nommu.S\n+++ b/arch/arm/kernel/head-nommu.S\n@@ -197,19 +197,33 @@ ENDPROC(__after_proc_init)\n #ifdef CONFIG_ARM_MPU\n \n \n+#ifndef CONFIG_CPU_V7M\n /* Set which MPU region should be programmed */\n-.macro set_region_nr tmp, rgnr\n+.macro set_region_nr tmp, rgnr, unused\n \tmov\t\\tmp, \\rgnr\t\t\t@ Use static region numbers\n \tmcr\tp15, 0, \\tmp, c6, c2, 0\t\t@ Write RGNR\n .endm\n \n /* Setup a single MPU region, either D or I side (D-side for unified) */\n-.macro setup_region bar, acr, sr, side = MPU_DATA_SIDE\n+.macro setup_region bar, acr, sr, side = MPU_DATA_SIDE, unused\n \tmcr\tp15, 0, \\bar, c6, c1, (0 + \\side)\t@ I/DRBAR\n \tmcr\tp15, 0, \\acr, c6, c1, (4 + \\side)\t@ I/DRACR\n \tmcr\tp15, 0, \\sr, c6, c1, (2 + \\side)\t\t@ I/DRSR\n .endm\n+#else\n+.macro set_region_nr tmp, rgnr, base\n+\tmov\t\\tmp, \\rgnr\n+\tstr \\tmp, [\\base, #MPU_RNR]\n+.endm\n+\n+.macro setup_region bar, acr, sr, unused, base\n+\tlsl \\acr, \\acr, #16\n+\torr \\acr, \\acr, \\sr\n+\tstr \\bar, [\\base, #MPU_RBAR]\n+\tstr \\acr, [\\base, #MPU_RASR]\n+.endm\n \n+#endif\n /*\n * Setup the MPU and initial MPU Regions. We create the following regions:\n * Region 0: Use this for probing the MPU details, so leave disabled.\n@@ -223,48 +237,58 @@ ENDPROC(__after_proc_init)\n ENTRY(__setup_mpu)\n \n \t/* Probe for v7 PMSA compliance */\n-\tmrc\tp15, 0, r0, c0, c1, 4\t\t@ Read ID_MMFR0\n+M_CLASS(movw\tr12, #:lower16:BASEADDR_V7M_SCB)\n+M_CLASS(movt\tr12, #:upper16:BASEADDR_V7M_SCB)\n+\n+AR_CLASS(mrc\tp15, 0, r0, c0, c1, 4)\t\t@ Read ID_MMFR0\n+M_CLASS(ldr\tr0, [r12, 0x50])\n \tand\tr0, r0, #(MMFR0_PMSA)\t\t@ PMSA field\n \tteq\tr0, #(MMFR0_PMSAv7)\t\t@ PMSA v7\n \tbxne\tlr\n \n \t/* Determine whether the D/I-side memory map is unified. We set the\n \t * flags here and continue to use them for the rest of this function */\n-\tmrc\tp15, 0, r0, c0, c0, 4\t\t@ MPUIR\n+AR_CLASS(mrc\tp15, 0, r0, c0, c0, 4)\t\t@ MPUIR\n+M_CLASS(ldr r0, [r12, #MPU_TYPE])\n \tands\tr5, r0, #MPUIR_DREGION_SZMASK\t@ 0 size d region => No MPU\n \tbxeq\tlr\n \ttst\tr0, #MPUIR_nU\t\t\t@ MPUIR_nU = 0 for unified\n \n \t/* Setup second region first to free up r6 */\n-\tset_region_nr r0, #MPU_RAM_REGION\n+\tset_region_nr r0, #MPU_RAM_REGION, r12\n \tisb\n \t/* Full access from PL0, PL1, shared for CONFIG_SMP, cacheable */\n \tldr\tr0, =PLAT_PHYS_OFFSET\t\t@ RAM starts at PHYS_OFFSET\n \tldr\tr5,=(MPU_AP_PL1RW_PL0RW | MPU_RGN_NORMAL)\n \n-\tsetup_region r0, r5, r6, MPU_DATA_SIDE\t@ PHYS_OFFSET, shared, enabled\n-\tbeq\t1f\t\t\t\t@ Memory-map not unified\n-\tsetup_region r0, r5, r6, MPU_INSTR_SIDE @ PHYS_OFFSET, shared, enabled\n+\tsetup_region r0, r5, r6, MPU_DATA_SIDE, r12\t@ PHYS_OFFSET, shared, enabled\n+\tbeq\t1f\t\t\t\t\t@ Memory-map not unified\n+\tsetup_region r0, r5, r6, MPU_INSTR_SIDE, r12\t@ PHYS_OFFSET, shared, enabled\n 1:\tisb\n \n \t/* First/background region */\n-\tset_region_nr r0, #MPU_BG_REGION\n+\tset_region_nr r0, #MPU_BG_REGION, r12\n \tisb\n \t/* Execute Never, strongly ordered, inaccessible to PL0, rw PL1 */\n \tmov\tr0, #0\t\t\t\t@ BG region starts at 0x0\n \tldr\tr5,=(MPU_ACR_XN | MPU_RGN_STRONGLY_ORDERED | MPU_AP_PL1RW_PL0NA)\n \tmov\tr6, #MPU_RSR_ALL_MEM\t\t@ 4GB region, enabled\n \n-\tsetup_region r0, r5, r6, MPU_DATA_SIDE\t@ 0x0, BG region, enabled\n-\tbeq\t2f\t\t\t\t@ Memory-map not unified\n-\tsetup_region r0, r5, r6, MPU_INSTR_SIDE @ 0x0, BG region, enabled\n+\tsetup_region r0, r5, r6, MPU_DATA_SIDE, r12\t@ 0x0, BG region, enabled\n+\tbeq\t2f\t\t\t\t\t@ Memory-map not unified\n+\tsetup_region r0, r5, r6, MPU_INSTR_SIDE r12\t@ 0x0, BG region, enabled\n 2:\tisb\n \n \t/* Enable the MPU */\n-\tmrc\tp15, 0, r0, c1, c0, 0\t\t@ Read SCTLR\n-\tbic\tr0, r0, #CR_BR\t\t\t@ Disable the 'default mem-map'\n-\torr\tr0, r0, #CR_M\t\t\t@ Set SCTRL.M (MPU on)\n-\tmcr\tp15, 0, r0, c1, c0, 0\t\t@ Enable MPU\n+AR_CLASS(mrc\tp15, 0, r0, c1, c0, 0)\t\t@ Read SCTLR\n+AR_CLASS(bic\tr0, r0, #CR_BR)\t\t\t@ Disable the 'default mem-map'\n+AR_CLASS(orr\tr0, r0, #CR_M)\t\t\t@ Set SCTRL.M (MPU on)\n+AR_CLASS(mcr\tp15, 0, r0, c1, c0, 0)\t\t@ Enable MPU\n+\n+M_CLASS(ldr\tr0, [r12, #MPU_CTRL])\n+M_CLASS(bic\tr0, #MPU_CTRL_PRIVDEFENA)\n+M_CLASS(orr\tr0, #MPU_CTRL_ENABLE)\n+M_CLASS(str\tr0, [r12, #MPU_CTRL])\n \tisb\n \n \tret\tlr\ndiff --git a/arch/arm/mm/pmsa-v7.c b/arch/arm/mm/pmsa-v7.c\nindex 029d204..72f1a9f 100644\n--- a/arch/arm/mm/pmsa-v7.c\n+++ b/arch/arm/mm/pmsa-v7.c\n@@ -15,6 +15,8 @@\n static unsigned int __initdata mpu_min_region_order;\n static unsigned int __initdata mpu_max_regions;\n \n+#ifndef CONFIG_CPU_V7M\n+\n #define DRBAR\t__ACCESS_CP15(c6, 0, c1, 0)\n #define IRBAR\t__ACCESS_CP15(c6, 0, c1, 1)\n #define DRSR\t__ACCESS_CP15(c6, 0, c1, 2)\n@@ -78,6 +80,51 @@ static inline u32 irbar_read(void)\n \treturn read_sysreg(IRBAR);\n }\n \n+#else\n+\n+static inline void rgnr_write(u32 v)\n+{\n+\twritel_relaxed(v, BASEADDR_V7M_SCB + MPU_RNR);\n+}\n+\n+/* Data-side / unified region attributes */\n+\n+/* Region access control register */\n+static inline void dracr_write(u32 v)\n+{\n+\tu32 rsr = readl_relaxed(BASEADDR_V7M_SCB + MPU_RASR) & GENMASK(15, 0);\n+\n+\twritel_relaxed((v << 16) | rsr, BASEADDR_V7M_SCB + MPU_RASR);\n+}\n+\n+/* Region size register */\n+static inline void drsr_write(u32 v)\n+{\n+\tu32 racr = readl_relaxed(BASEADDR_V7M_SCB + MPU_RASR) & GENMASK(31, 16);\n+\n+\twritel_relaxed(v | racr, BASEADDR_V7M_SCB + MPU_RASR);\n+}\n+\n+/* Region base address register */\n+static inline void drbar_write(u32 v)\n+{\n+\twritel_relaxed(v, BASEADDR_V7M_SCB + MPU_RBAR);\n+}\n+\n+static inline u32 drbar_read(void)\n+{\n+\treturn readl_relaxed(BASEADDR_V7M_SCB + MPU_RBAR);\n+}\n+\n+/* ARMv7-M only supports a unified MPU, so I-side operations are nop */\n+\n+static inline void iracr_write(u32 v) {}\n+static inline void irsr_write(u32 v) {}\n+static inline void irbar_write(u32 v) {}\n+static inline unsigned long irbar_read(void) {return 0;}\n+\n+#endif\n+\n static int __init mpu_present(void)\n {\n \treturn ((read_cpuid_ext(CPUID_EXT_MMFR0) & MMFR0_PMSA) == MMFR0_PMSAv7);\n@@ -166,7 +213,7 @@ static int __init __mpu_max_regions(void)\n \t */\n \tu32 dregions, iregions, mpuir;\n \n-\tmpuir = read_cpuid(CPUID_MPUIR);\n+\tmpuir = read_cpuid_mputype();\n \n \tdregions = iregions = (mpuir & MPUIR_DREGION_SZMASK) >> MPUIR_DREGION;\n \n@@ -181,7 +228,7 @@ static int __init __mpu_max_regions(void)\n static int __init mpu_iside_independent(void)\n {\n \t/* MPUIR.nU specifies whether there is *not* a unified memory map */\n-\treturn read_cpuid(CPUID_MPUIR) & MPUIR_nU;\n+\treturn read_cpuid_mputype() & MPUIR_nU;\n }\n \n static int __init __mpu_min_region_order(void)\n@@ -284,9 +331,11 @@ void __init mpu_setup(void)\n \t\t\t\tMPU_AP_PL1RW_PL0RW | MPU_RGN_NORMAL);\n \n \t/* Vectors */\n+#ifndef CONFIG_CPU_V7M\n \terr |= mpu_setup_region(region++, vectors_base,\n \t\t\t\tilog2(2 * PAGE_SIZE),\n \t\t\t\tMPU_AP_PL1RW_PL0NA | MPU_RGN_NORMAL);\n+#endif\n \tif (err) {\n \t\tpanic(\"MPU region initialization failure! %d\", err);\n \t} else {\n", "prefixes": [ "v3", "6/8" ] }