Patch Detail

HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 817890,
    "url": "http://patchwork.ozlabs.org/api/patches/817890/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20170924105924.23923-4-vigneshr@ti.com/",
    "project": {
        "id": 37,
        "url": "http://patchwork.ozlabs.org/api/projects/37/?format=api",
        "name": "Devicetree Bindings",
        "link_name": "devicetree-bindings",
        "list_id": "devicetree.vger.kernel.org",
        "list_email": "devicetree@vger.kernel.org",
        "web_url": "",
        "scm_url": "",
        "webscm_url": "",
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20170924105924.23923-4-vigneshr@ti.com>",
    "list_archive_url": null,
    "date": "2017-09-24T10:59:22",
    "name": "[v3,3/5] mtd: spi-nor: cadence-quadspi: Add new binding to enable loop-back circuit",
    "commit_ref": null,
    "pull_url": null,
    "state": "not-applicable",
    "archived": true,
    "hash": "7772878ebe166d2d0d7e4ea978d29421dd51db0a",
    "submitter": {
        "id": 65039,
        "url": "http://patchwork.ozlabs.org/api/people/65039/?format=api",
        "name": "Raghavendra, Vignesh",
        "email": "vigneshr@ti.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20170924105924.23923-4-vigneshr@ti.com/mbox/",
    "series": [
        {
            "id": 4810,
            "url": "http://patchwork.ozlabs.org/api/series/4810/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=4810",
            "date": "2017-09-24T10:59:20",
            "name": "K2G: Add QSPI support",
            "version": 3,
            "mbox": "http://patchwork.ozlabs.org/series/4810/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/817890/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/817890/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<devicetree-owner@vger.kernel.org>",
        "X-Original-To": "incoming-dt@patchwork.ozlabs.org",
        "Delivered-To": "patchwork-incoming-dt@bilbo.ozlabs.org",
        "Authentication-Results": [
            "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=<UNKNOWN>)",
            "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=ti.com header.i=@ti.com header.b=\"HxxPpuvw\"; \n\tdkim-atps=neutral"
        ],
        "Received": [
            "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y0PRJ6q6Fz9sDB\n\tfor <incoming-dt@patchwork.ozlabs.org>;\n\tSun, 24 Sep 2017 21:01:32 +1000 (AEST)",
            "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752100AbdIXLAN (ORCPT\n\t<rfc822;incoming-dt@patchwork.ozlabs.org>);\n\tSun, 24 Sep 2017 07:00:13 -0400",
            "from fllnx210.ext.ti.com ([198.47.19.17]:15813 \"EHLO\n\tfllnx210.ext.ti.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752097AbdIXLAL (ORCPT\n\t<rfc822; devicetree@vger.kernel.org>); Sun, 24 Sep 2017 07:00:11 -0400",
            "from dflxv15.itg.ti.com ([128.247.5.124])\n\tby fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id v8OAxIth016750; \n\tSun, 24 Sep 2017 05:59:18 -0500",
            "from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35])\n\tby dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8OAxI6v016093;\n\tSun, 24 Sep 2017 05:59:18 -0500",
            "from DFLE108.ent.ti.com (10.64.6.29) by DFLE114.ent.ti.com\n\t(10.64.6.35) with Microsoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34;\n\tSun, 24 Sep 2017 05:59:17 -0500",
            "from dflp33.itg.ti.com (10.64.6.16) by DFLE108.ent.ti.com\n\t(10.64.6.29) with Microsoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend\n\tTransport; Sun, 24 Sep 2017 05:59:18 -0500",
            "from a0132425.india.ti.com (ileax41-snat.itg.ti.com\n\t[10.172.224.153])\n\tby dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8OAx4DG027688;\n\tSun, 24 Sep 2017 05:59:15 -0500"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com;\n\ts=ti-com-17Q1; t=1506250758;\n\tbh=uI+4+QRwxXE07v/9ifxsyixDo7u2QnF00OF4Wf40I3o=;\n\th=From:To:CC:Subject:Date:In-Reply-To:References;\n\tb=HxxPpuvw/e7NJX5rcIm2t8c6eQveQB58xsFCaBWrkWMXBVyYhSGolUbx/ReHtF/Jm\n\tFK9vz6jpo0C3QNxlk1kqqDqGUaxk9moBnH4K76F5RemUXrYr7Fhes4vOC15NrO5y8i\n\tY7GH3E4zXx13MgWZ809YKoDghG30j0bPX/Uf8DYY=",
        "From": "Vignesh R <vigneshr@ti.com>",
        "To": "Marek Vasut <marek.vasut@gmail.com>,\n\tCyrille Pitchen <cyrille.pitchen@wedev4u.fr>",
        "CC": "David Woodhouse <dwmw2@infradead.org>,\n\tBrian Norris <computersforpeace@gmail.com>,\n\tBoris Brezillon <boris.brezillon@free-electrons.com>,\n\tRob Herring <robh+dt@kernel.org>,\n\t<linux-mtd@lists.infradead.org>, <devicetree@vger.kernel.org>,\n\t<linux-kernel@vger.kernel.org>, Vignesh R <vigneshr@ti.com>,\n\tlinux-arm-kernel <linux-arm-kernel@lists.infradead.org>",
        "Subject": "[PATCH v3 3/5] mtd: spi-nor: cadence-quadspi: Add new binding to\n\tenable loop-back circuit",
        "Date": "Sun, 24 Sep 2017 16:29:22 +0530",
        "Message-ID": "<20170924105924.23923-4-vigneshr@ti.com>",
        "X-Mailer": "git-send-email 2.14.1",
        "In-Reply-To": "<20170924105924.23923-1-vigneshr@ti.com>",
        "References": "<20170924105924.23923-1-vigneshr@ti.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
        "X-EXCLAIMER-MD-CONFIG": "e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180",
        "Sender": "devicetree-owner@vger.kernel.org",
        "Precedence": "bulk",
        "List-ID": "<devicetree.vger.kernel.org>",
        "X-Mailing-List": "devicetree@vger.kernel.org"
    },
    "content": "Cadence QSPI IP has a adapted loop-back circuit which can be enabled by\nsetting BYPASS field to 0 in READCAPTURE register. It enables use of\nQSPI return clock to latch the data rather than the internal QSPI\nreference clock. For high speed operations, adapted loop-back circuit\nusing QSPI return clock helps to increase data valid window.\n\nAdd DT parameter cdns,rclk-en to help enable adapted loop-back circuit\nfor boards which do have QSPI return clock provided. Update binding\ndocumentation for the same.\n\nSigned-off-by: Vignesh R <vigneshr@ti.com>\nAcked-by: Rob Herring <robh@kernel.org>\n---\n Documentation/devicetree/bindings/mtd/cadence-quadspi.txt | 3 +++\n 1 file changed, 3 insertions(+)",
    "diff": "diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt\nindex 7dbe3bd9ac56..bb2075df9b38 100644\n--- a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt\n+++ b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt\n@@ -16,6 +16,9 @@ Required properties:\n \n Optional properties:\n - cdns,is-decoded-cs : Flag to indicate whether decoder is used or not.\n+- cdns,rclk-en : Flag to indicate that QSPI return clock is used to latch\n+  the read data rather than the QSPI clock. Make sure that QSPI return\n+  clock is populated on the board before using this property.\n \n Optional subnodes:\n Subnodes of the Cadence Quad SPI controller are spi slave nodes with additional\n",
    "prefixes": [
        "v3",
        "3/5"
    ]
}