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GET /api/patches/817865/?format=api
{ "id": 817865, "url": "http://patchwork.ozlabs.org/api/patches/817865/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1506232825-27448-3-git-send-email-uri.mashiach@compulab.co.il/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1506232825-27448-3-git-send-email-uri.mashiach@compulab.co.il>", "list_archive_url": null, "date": "2017-09-24T06:00:23", "name": "[U-Boot,2/4] imx: mx7: DDR controller configuration for the i.MX7 architecture", "commit_ref": "258bad41aca541cdfb78aab7142aaf5b72a2dfe9", "pull_url": null, "state": "accepted", "archived": false, "hash": "a5655000d502876f8f5fe2914b3833684d40e80a", "submitter": { "id": 67462, "url": "http://patchwork.ozlabs.org/api/people/67462/?format=api", "name": "Uri Mashiach", "email": "uri.mashiach@compulab.co.il" }, "delegate": { "id": 1693, "url": "http://patchwork.ozlabs.org/api/users/1693/?format=api", "username": "sbabic", "first_name": "Stefano", "last_name": "Babic", "email": "sbabic@denx.de" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1506232825-27448-3-git-send-email-uri.mashiach@compulab.co.il/mbox/", "series": [ { "id": 4801, "url": "http://patchwork.ozlabs.org/api/series/4801/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=4801", "date": "2017-09-24T06:00:21", "name": "cl-som-imx7: initial support", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/4801/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/817865/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/817865/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"key not found in DNS\" (0-bit key;\n\tunprotected) header.d=compulab.co.il header.i=@compulab.co.il\n\theader.b=\"U18e5QpR\"; dkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y0GpN3vWfz9tX6\n\tfor <incoming@patchwork.ozlabs.org>;\n\tSun, 24 Sep 2017 16:02:36 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 539E6C2206E; Sun, 24 Sep 2017 06:02:17 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 62BE9C22058;\n\tSun, 24 Sep 2017 06:01:56 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 98D1EC2207F; Sun, 24 Sep 2017 06:01:41 +0000 (UTC)", "from compulab.co.il (softlayer.compulab.co.il [50.23.254.55])\n\tby lists.denx.de (Postfix) with ESMTPS id B260CC2203C\n\tfor <u-boot@lists.denx.de>; Sun, 24 Sep 2017 06:01:40 +0000 (UTC)", "from [37.142.126.90] (port=36963 helo=zimbra-mta.compulab.co.il)\n\tby softlayer.compulab.co.il with esmtp (Exim 4.87)\n\t(envelope-from <uri.mashiach@compulab.co.il>)\n\tid 1dvzz0-0002w4-1E; Sun, 24 Sep 2017 09:01:38 +0300", "from localhost (localhost [127.0.0.1])\n\tby zimbra-mta.compulab.co.il (Postfix) with ESMTP id 2BF0F48109D;\n\tSun, 24 Sep 2017 09:01:37 +0300 (IDT)", "from zimbra-mta.compulab.co.il ([127.0.0.1])\n\tby localhost (zimbra-mta.compulab.co.il [127.0.0.1]) (amavisd-new,\n\tport 10032)\n\twith ESMTP id ZyyTX-K98rDF; Sun, 24 Sep 2017 09:01:36 +0300 (IDT)", "from localhost (localhost [127.0.0.1])\n\tby zimbra-mta.compulab.co.il (Postfix) with ESMTP id 633AB4810B1;\n\tSun, 24 Sep 2017 09:01:36 +0300 (IDT)", "from zimbra-mta.compulab.co.il ([127.0.0.1])\n\tby localhost (zimbra-mta.compulab.co.il [127.0.0.1]) (amavisd-new,\n\tport 10026)\n\twith ESMTP id bYWt36Eudmlp; Sun, 24 Sep 2017 09:01:36 +0300 (IDT)", "from urim-desk.compulab.local (uri-ipc.compulab.local\n\t[192.168.11.218])\n\tby zimbra-mta.compulab.co.il (Postfix) with ESMTP id 3DA3448109D;\n\tSun, 24 Sep 2017 09:01:36 +0300 (IDT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=0.0 required=5.0 tests=SPF_HELO_PASS, T_DKIM_INVALID\n\tautolearn=unavailable autolearn_force=no version=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=compulab.co.il; s=default;\n\th=References:In-Reply-To:Message-Id:Date:Subject\n\t:Cc:To:From:Sender:Reply-To:MIME-Version:Content-Type:\n\tContent-Transfer-Encoding:Content-ID:Content-Description:Resent-Date:\n\tResent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:\n\tList-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive;\n\tbh=i/eC4zxQSLy/vYWrwBs8uEmlRrroYE3nfwr6BLUesYY=;\n\tb=U18e5QpRscVTpXyxVr+dWeUIJ\n\thCSizC+KBOq8esQHF5jD8G5N4HEyNBscZP3O+3ZIxvdfwljHxAZAncOlGc8D5gTSyl+DmflRjmWpQ\n\ty8EA+XxI3CvS366kZyD0BenkWlY7PEYEplx770n/VNVN5SiwR5mW2Kj5AHG+4lbLsFo48k3LRI0ya\n\tdAq1q/E++5qoYp5LZrEL2GilpP+XlQgjJteFxz3c3kgJhRy8+jiDLBgp9vErs/KtaeL5o1nfGui0c\n\tyAyezbSi/MF8LL+tByXRnrRMppTPq9nMaHesZvdc+j9gw6iFx8TIskYxV/YGqRCkTtCFvZeoSWguy\n\tY+DsN5B+Q==;", "X-Virus-Scanned": "amavisd-new at zimbra-mta.compulab.co.il", "From": "Uri Mashiach <uri.mashiach@compulab.co.il>", "To": "Stefano Babic <sbabic@denx.de>", "Date": "Sun, 24 Sep 2017 09:00:23 +0300", "Message-Id": "<1506232825-27448-3-git-send-email-uri.mashiach@compulab.co.il>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1506232825-27448-1-git-send-email-uri.mashiach@compulab.co.il>", "References": "<1506232825-27448-1-git-send-email-uri.mashiach@compulab.co.il>", "X-AntiAbuse": [ "This header was added to track abuse,\n\tplease include it with any abuse report", "Primary Hostname - softlayer.compulab.co.il", "Original Domain - lists.denx.de", "Originator/Caller UID/GID - [47 12] / [47 12]", "Sender Address Domain - compulab.co.il" ], "X-Get-Message-Sender-Via": "softlayer.compulab.co.il: acl_c_recent_authed_mail_ips_text_entry:\n\turi.mashiach@compulab.co.il|compulab.co.il", "X-Authenticated-Sender": "softlayer.compulab.co.il: uri.mashiach@compulab.co.il", "Cc": "Fabio Estevam <fabio.estevam@nxp.com>, u-boot@lists.denx.de", "Subject": "[U-Boot] [PATCH 2/4] imx: mx7: DDR controller configuration for the\n\ti.MX7 architecture", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "The configuration files imximage.cfg are used for the DDR controller\nconfiguration.\nAdd DDR configuration function to replace the DDR controller\nconfiguration in the imximage.cfg file. The function can be used for\nDDR size detection.\n\nSigned-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>\n---\n arch/arm/include/asm/arch-mx7/crm_regs.h | 5 +\n arch/arm/include/asm/arch-mx7/imx-regs.h | 2 +\n arch/arm/include/asm/arch-mx7/mx7-ddr.h | 155 ++++++++++++++++++++++++\n arch/arm/mach-imx/mx7/Makefile | 2 +-\n arch/arm/mach-imx/mx7/ddr.c | 201 +++++++++++++++++++++++++++++++\n 5 files changed, 364 insertions(+), 1 deletion(-)\n create mode 100644 arch/arm/include/asm/arch-mx7/mx7-ddr.h\n create mode 100644 arch/arm/mach-imx/mx7/ddr.c", "diff": "diff --git a/arch/arm/include/asm/arch-mx7/crm_regs.h b/arch/arm/include/asm/arch-mx7/crm_regs.h\nindex e54a254..611190e 100644\n--- a/arch/arm/include/asm/arch-mx7/crm_regs.h\n+++ b/arch/arm/include/asm/arch-mx7/crm_regs.h\n@@ -2055,6 +2055,11 @@ struct mxc_ccm_anatop_reg {\n #define HW_CCM_ROOT_TARGET_TOGGLE(i, v)\twritel((v), CCM_ROOT_TARGET_TOGGLE(i))\n \n #define CCM_CLK_ON_MSK\t0x03\n+#define CCM_CLK_ON_N_N\t0x00 /* Domain clocks not needed */\n+#define CCM_CLK_ON_R_W\t0x02 /* Domain clocks needed when in RUN and WAIT */\n+\n+/* CCGR Mapping */\n+#define CCGR_IDX_DDR 19 /* CCM_CCGR19 */\n \n #define CCM_ROOT_TGT_POST_DIV_SHIFT\t0\n #define CCM_ROOT_TGT_PRE_DIV_SHIFT\t15\ndiff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h\nindex aab3a9a..f0693f9 100644\n--- a/arch/arm/include/asm/arch-mx7/imx-regs.h\n+++ b/arch/arm/include/asm/arch-mx7/imx-regs.h\n@@ -268,6 +268,8 @@ struct src {\n #define SRC_M4RCR_M4C_NON_SCLR_RST_MASK\t\t(1 << 0)\n #define SRC_M4RCR_ENABLE_M4_OFFSET\t\t3\n #define SRC_M4RCR_ENABLE_M4_MASK\t\t(1 << 3)\n+#define SRC_DDRC_RCR_DDRC_CORE_RST_OFFSET\t1\n+#define SRC_DDRC_RCR_DDRC_CORE_RST_MASK\t\t(1 << 1)\n \n /* GPR0 Bit Fields */\n #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_MASK 0x1u\ndiff --git a/arch/arm/include/asm/arch-mx7/mx7-ddr.h b/arch/arm/include/asm/arch-mx7/mx7-ddr.h\nnew file mode 100644\nindex 0000000..3a4841c\n--- /dev/null\n+++ b/arch/arm/include/asm/arch-mx7/mx7-ddr.h\n@@ -0,0 +1,155 @@\n+/*\n+ * DDR controller registers of the i.MX7 architecture\n+ *\n+ * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com\n+ *\n+ * Author: Uri Mashiach <uri.mashiach@compulab.co.il>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __ASM_ARCH_MX7_DDR_H__\n+#define __ASM_ARCH_MX7_DDR_H__\n+\n+/* DDRC Registers (DDRC_IPS_BASE_ADDR) */\n+struct ddrc {\n+\tu32 mstr;\t\t/* 0x0000 */\n+\tu32 reserved1[0x18];\n+\tu32 rfshtmg;\t\t/* 0x0064 */\n+\tu32 reserved2[0x1a];\n+\tu32 init0;\t\t/* 0x00d0 */\n+\tu32 init1;\t\t/* 0x00d4 */\n+\tu32 reserved3;\n+\tu32 init3;\t\t/* 0x00dc */\n+\tu32 init4;\t\t/* 0x00e0 */\n+\tu32 init5;\t\t/* 0x00e4 */\n+\tu32 reserved4[0x03];\n+\tu32 rankctl;\t\t/* 0x00f4 */\n+\tu32 reserved5[0x02];\n+\tu32 dramtmg0;\t\t/* 0x0100 */\n+\tu32 dramtmg1;\t\t/* 0x0104 */\n+\tu32 dramtmg2;\t\t/* 0x0108 */\n+\tu32 dramtmg3;\t\t/* 0x010c */\n+\tu32 dramtmg4;\t\t/* 0x0110 */\n+\tu32 dramtmg5;\t\t/* 0x0114 */\n+\tu32 reserved6[0x02];\n+\tu32 dramtmg8;\t\t/* 0x0120 */\n+\tu32 reserved7[0x17];\n+\tu32 zqctl0;\t\t/* 0x0180 */\n+\tu32 reserved8[0x03];\n+\tu32 dfitmg0;\t\t/* 0x0190 */\n+\tu32 dfitmg1;\t\t/* 0x0194 */\n+\tu32 reserved9[0x02];\n+\tu32 dfiupd0;\t\t/* 0x01a0 */\n+\tu32 dfiupd1;\t\t/* 0x01a4 */\n+\tu32 dfiupd2;\t\t/* 0x01a8 */\n+\tu32 reserved10[0x15];\n+\tu32 addrmap0;\t\t/* 0x0200 */\n+\tu32 addrmap1;\t\t/* 0x0204 */\n+\tu32 addrmap2;\t\t/* 0x0208 */\n+\tu32 addrmap3;\t\t/* 0x020c */\n+\tu32 addrmap4;\t\t/* 0x0210 */\n+\tu32 addrmap5;\t\t/* 0x0214 */\n+\tu32 addrmap6;\t\t/* 0x0218 */\n+\tu32 reserved12[0x09];\n+\tu32 odtcfg;\t\t/* 0x0240 */\n+\tu32 odtmap;\t\t/* 0x0244 */\n+};\n+\n+/* DDRC_MSTR fields */\n+#define MSTR_DATA_BUS_WIDTH_MASK\t0x3 << 12\n+#define MSTR_DATA_BUS_WIDTH_SHIFT\t12\n+#define MSTR_DATA_ACTIVE_RANKS_MASK\t0xf << 24\n+#define MSTR_DATA_ACTIVE_RANKS_SHIFT\t24\n+/* DDRC_ADDRMAP1 fields */\n+#define ADDRMAP1_BANK_B0_MASK\t\t0x1f << 0\n+#define ADDRMAP1_BANK_B0_SHIFT\t\t0\n+#define ADDRMAP1_BANK_B1_MASK\t\t0x1f << 8\n+#define ADDRMAP1_BANK_B1_SHIFT\t\t8\n+#define ADDRMAP1_BANK_B2_MASK\t\t0x1f << 16\n+#define ADDRMAP1_BANK_B2_SHIFT\t\t16\n+/* DDRC_ADDRMAP2 fields */\n+#define ADDRMAP2_COL_B2_MASK\t\t0xF << 0\n+#define ADDRMAP2_COL_B2_SHIFT\t\t0\n+#define ADDRMAP2_COL_B3_MASK\t\t0xF << 8\n+#define ADDRMAP2_COL_B3_SHIFT\t\t8\n+#define ADDRMAP2_COL_B4_MASK\t\t0xF << 16\n+#define ADDRMAP2_COL_B4_SHIFT\t\t16\n+#define ADDRMAP2_COL_B5_MASK\t\t0xF << 24\n+#define ADDRMAP2_COL_B5_SHIFT\t\t24\n+/* DDRC_ADDRMAP3 fields */\n+#define ADDRMAP3_COL_B6_MASK\t\t0xF << 0\n+#define ADDRMAP3_COL_B6_SHIFT\t\t0\n+#define ADDRMAP3_COL_B7_MASK\t\t0xF << 8\n+#define ADDRMAP3_COL_B7_SHIFT\t\t8\n+#define ADDRMAP3_COL_B8_MASK\t\t0xF << 16\n+#define ADDRMAP3_COL_B8_SHIFT\t\t16\n+#define ADDRMAP3_COL_B9_MASK\t\t0xF << 24\n+#define ADDRMAP3_COL_B9_SHIFT\t\t24\n+/* DDRC_ADDRMAP4 fields */\n+#define ADDRMAP4_COL_B10_MASK\t\t0xF << 0\n+#define ADDRMAP4_COL_B10_SHIFT\t\t0\n+#define ADDRMAP4_COL_B11_MASK\t\t0xF << 8\n+#define ADDRMAP4_COL_B11_SHIFT\t\t8\n+/* DDRC_ADDRMAP5 fields */\n+#define ADDRMAP5_ROW_B0_MASK\t\t0xF << 0\n+#define ADDRMAP5_ROW_B0_SHIFT\t\t0\n+#define ADDRMAP5_ROW_B1_MASK\t\t0xF << 8\n+#define ADDRMAP5_ROW_B1_SHIFT\t\t8\n+#define ADDRMAP5_ROW_B2_10_MASK\t\t0xF << 16\n+#define ADDRMAP5_ROW_B2_10_SHIFT\t16\n+#define ADDRMAP5_ROW_B11_MASK\t\t0xF << 24\n+#define ADDRMAP5_ROW_B11_SHIFT\t\t24\n+/* DDRC_ADDRMAP6 fields */\n+#define ADDRMAP6_ROW_B12_MASK\t\t0xF << 0\n+#define ADDRMAP6_ROW_B12_SHIFT\t\t0\n+#define ADDRMAP6_ROW_B13_MASK\t\t0xF << 8\n+#define ADDRMAP6_ROW_B13_SHIFT\t\t8\n+#define ADDRMAP6_ROW_B14_MASK\t\t0xF << 16\n+#define ADDRMAP6_ROW_B14_SHIFT\t\t16\n+#define ADDRMAP6_ROW_B15_MASK\t\t0xF << 24\n+#define ADDRMAP6_ROW_B15_SHIFT\t\t24\n+\n+/* DDRC_MP Registers */\n+#define DDRC_MP_BASE_ADDR (DDRC_IPS_BASE_ADDR + 0x03fc)\n+struct ddrc_mp {\n+\tu32 reserved1[0x25];\n+\tu32 pctrl_0;\t\t/* 0x0094 */\n+};\n+\n+/* DDR_PHY registers */\n+struct ddr_phy {\n+\tu32 phy_con0;\t\t/* 0x0000 */\n+\tu32 phy_con1;\t\t/* 0x0004 */\n+\tu32 reserved1[0x02];\n+\tu32 phy_con4;\t\t/* 0x0010 */\n+\tu32 reserved2;\n+\tu32 offset_lp_con0;\t/* 0x0018 */\n+\tu32 reserved3;\n+\tu32 offset_rd_con0;\t/* 0x0020 */\n+\tu32 reserved4[0x03];\n+\tu32 offset_wr_con0;\t/* 0x0030 */\n+\tu32 reserved5[0x07];\n+\tu32 cmd_sdll_con0;\t/* 0x0050 */\n+\tu32 reserved6[0x12];\n+\tu32 drvds_con0;\t\t/* 0x009c */\n+\tu32 reserved7[0x04];\n+\tu32 mdll_con0;\t\t/* 0x00b0 */\n+\tu32 reserved8[0x03];\n+\tu32 zq_con0;\t\t/* 0x00c0 */\n+};\n+\n+#define DDR_PHY_CMD_SDLL_CON0_CTRL_RESYNC_MASK BIT(24)\n+\n+#define MX7_CAL_VAL_MAX 5\n+/* Calibration parameters */\n+struct mx7_calibration {\n+\tint num_val;\t\t\t/* Number of calibration values */\n+\tu32 values[MX7_CAL_VAL_MAX];\t/* calibration values */\n+};\n+\n+void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val,\n+\t\t struct ddr_phy *ddr_phy_regs_val,\n+\t\t struct mx7_calibration *calib_param);\n+\n+#endif\t/*__ASM_ARCH_MX7_DDR_H__ */\ndiff --git a/arch/arm/mach-imx/mx7/Makefile b/arch/arm/mach-imx/mx7/Makefile\nindex d21f87f..ce289c1 100644\n--- a/arch/arm/mach-imx/mx7/Makefile\n+++ b/arch/arm/mach-imx/mx7/Makefile\n@@ -5,7 +5,7 @@\n #\n #\n \n-obj-y\t:= soc.o clock.o clock_slice.o\n+obj-y\t:= soc.o clock.o clock_slice.o ddr.o\n \n ifdef CONFIG_ARMV7_PSCI\n obj-y += psci-mx7.o psci.o\ndiff --git a/arch/arm/mach-imx/mx7/ddr.c b/arch/arm/mach-imx/mx7/ddr.c\nnew file mode 100644\nindex 0000000..9268ad9\n--- /dev/null\n+++ b/arch/arm/mach-imx/mx7/ddr.c\n@@ -0,0 +1,201 @@\n+/*\n+ * DDR controller configuration for the i.MX7 architecture\n+ *\n+ * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com\n+ *\n+ * Author: Uri Mashiach <uri.mashiach@compulab.co.il>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <linux/types.h>\n+#include <asm/io.h>\n+#include <asm/arch/imx-regs.h>\n+#include <asm/arch/crm_regs.h>\n+#include <asm/arch/mx7-ddr.h>\n+#include <common.h>\n+\n+/*\n+ * Routine: mx7_dram_cfg\n+ * Description: DDR controller configuration\n+ *\n+ * @ddrc_regs_val: DDRC registers value\n+ * @ddrc_mp_val: DDRC_MP registers value\n+ * @ddr_phy_regs_val: DDR_PHY registers value\n+ * @calib_param: calibration parameters\n+ *\n+ */\n+void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val,\n+\t\t struct ddr_phy *ddr_phy_regs_val,\n+\t\t struct mx7_calibration *calib_param)\n+{\n+\tstruct src *const src_regs = (struct src *)SRC_BASE_ADDR;\n+\tstruct ddrc *const ddrc_regs = (struct ddrc *)DDRC_IPS_BASE_ADDR;\n+\tstruct ddrc_mp *const ddrc_mp_reg = (struct ddrc_mp *)DDRC_MP_BASE_ADDR;\n+\tstruct ddr_phy *const ddr_phy_regs =\n+\t\t(struct ddr_phy *)DDRPHY_IPS_BASE_ADDR;\n+\tstruct iomuxc_gpr_base_regs *const iomuxc_gpr_regs =\n+\t\t(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;\n+\tint i;\n+\n+\t/* Assert DDR Controller preset and DDR PHY reset */\n+\twritel(SRC_DDRC_RCR_DDRC_CORE_RST_MASK, &src_regs->ddrc_rcr);\n+\n+\t/* DDR controller configuration */\n+\twritel(ddrc_regs_val->mstr, &ddrc_regs->mstr);\n+\twritel(ddrc_regs_val->rfshtmg, &ddrc_regs->rfshtmg);\n+\twritel(ddrc_mp_val->pctrl_0, &ddrc_mp_reg->pctrl_0);\n+\twritel(ddrc_regs_val->init1, &ddrc_regs->init1);\n+\twritel(ddrc_regs_val->init0, &ddrc_regs->init0);\n+\twritel(ddrc_regs_val->init3, &ddrc_regs->init3);\n+\twritel(ddrc_regs_val->init4, &ddrc_regs->init4);\n+\twritel(ddrc_regs_val->init5, &ddrc_regs->init5);\n+\twritel(ddrc_regs_val->rankctl, &ddrc_regs->rankctl);\n+\twritel(ddrc_regs_val->dramtmg0, &ddrc_regs->dramtmg0);\n+\twritel(ddrc_regs_val->dramtmg1, &ddrc_regs->dramtmg1);\n+\twritel(ddrc_regs_val->dramtmg2, &ddrc_regs->dramtmg2);\n+\twritel(ddrc_regs_val->dramtmg3, &ddrc_regs->dramtmg3);\n+\twritel(ddrc_regs_val->dramtmg4, &ddrc_regs->dramtmg4);\n+\twritel(ddrc_regs_val->dramtmg5, &ddrc_regs->dramtmg5);\n+\twritel(ddrc_regs_val->dramtmg8, &ddrc_regs->dramtmg8);\n+\twritel(ddrc_regs_val->zqctl0, &ddrc_regs->zqctl0);\n+\twritel(ddrc_regs_val->dfitmg0, &ddrc_regs->dfitmg0);\n+\twritel(ddrc_regs_val->dfitmg1, &ddrc_regs->dfitmg1);\n+\twritel(ddrc_regs_val->dfiupd0, &ddrc_regs->dfiupd0);\n+\twritel(ddrc_regs_val->dfiupd1, &ddrc_regs->dfiupd1);\n+\twritel(ddrc_regs_val->dfiupd2, &ddrc_regs->dfiupd2);\n+\twritel(ddrc_regs_val->addrmap0, &ddrc_regs->addrmap0);\n+\twritel(ddrc_regs_val->addrmap1, &ddrc_regs->addrmap1);\n+\twritel(ddrc_regs_val->addrmap4, &ddrc_regs->addrmap4);\n+\twritel(ddrc_regs_val->addrmap5, &ddrc_regs->addrmap5);\n+\twritel(ddrc_regs_val->addrmap6, &ddrc_regs->addrmap6);\n+\twritel(ddrc_regs_val->odtcfg, &ddrc_regs->odtcfg);\n+\twritel(ddrc_regs_val->odtmap, &ddrc_regs->odtmap);\n+\n+\t/* De-assert DDR Controller preset and DDR PHY reset */\n+\tclrbits_le32(&src_regs->ddrc_rcr, SRC_DDRC_RCR_DDRC_CORE_RST_MASK);\n+\n+\t/* PHY configuration */\n+\twritel(ddr_phy_regs_val->phy_con0, &ddr_phy_regs->phy_con0);\n+\twritel(ddr_phy_regs_val->phy_con1, &ddr_phy_regs->phy_con1);\n+\twritel(ddr_phy_regs_val->phy_con4, &ddr_phy_regs->phy_con4);\n+\twritel(ddr_phy_regs_val->mdll_con0, &ddr_phy_regs->mdll_con0);\n+\twritel(ddr_phy_regs_val->drvds_con0, &ddr_phy_regs->drvds_con0);\n+\twritel(ddr_phy_regs_val->offset_wr_con0, &ddr_phy_regs->offset_wr_con0);\n+\twritel(ddr_phy_regs_val->offset_rd_con0, &ddr_phy_regs->offset_rd_con0);\n+\twritel(ddr_phy_regs_val->cmd_sdll_con0 |\n+\t DDR_PHY_CMD_SDLL_CON0_CTRL_RESYNC_MASK,\n+\t &ddr_phy_regs->cmd_sdll_con0);\n+\twritel(ddr_phy_regs_val->cmd_sdll_con0 &\n+\t ~DDR_PHY_CMD_SDLL_CON0_CTRL_RESYNC_MASK,\n+\t &ddr_phy_regs->cmd_sdll_con0);\n+\twritel(ddr_phy_regs_val->offset_lp_con0, &ddr_phy_regs->offset_lp_con0);\n+\n+\t/* calibration */\n+\tfor (i = 0; i < calib_param->num_val; i++)\n+\t\twritel(calib_param->values[i], &ddr_phy_regs->zq_con0);\n+\n+\t/* Wake_up DDR PHY */\n+\tHW_CCM_CCGR_WR(CCGR_IDX_DDR, CCM_CLK_ON_N_N);\n+\twritel(IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up(0xf) |\n+\t IOMUXC_GPR_GPR8_ddr_phy_dfi_init_start_MASK,\n+\t &iomuxc_gpr_regs->gpr[8]);\n+\tHW_CCM_CCGR_WR(CCGR_IDX_DDR, CCM_CLK_ON_R_W);\n+}\n+\n+/*\n+ * Routine: imx_ddr_size\n+ * Description: extract the current DRAM size from the DDRC registers\n+ *\n+ * @return: DRAM size\n+ */\n+unsigned int imx_ddr_size(void)\n+{\n+\tstruct ddrc *const ddrc_regs = (struct ddrc *)DDRC_IPS_BASE_ADDR;\n+\tu32 reg_val, field_val;\n+\tint bits = 0;/* Number of address bits */\n+\n+\t/* Count data bus width bits */\n+\treg_val = readl(&ddrc_regs->mstr);\n+\tfield_val = (reg_val & MSTR_DATA_BUS_WIDTH_MASK) >> MSTR_DATA_BUS_WIDTH_SHIFT;\n+\tbits += 2 - field_val;\n+\t/* Count rank address bits */\n+\tfield_val = (reg_val & MSTR_DATA_ACTIVE_RANKS_MASK) >> MSTR_DATA_ACTIVE_RANKS_SHIFT;\n+\tif (field_val > 1)\n+\t\tbits += field_val - 1;\n+\t/* Count column address bits */\n+\tbits += 2;/* Column address 0 and 1 are fixed mapped */\n+\treg_val = readl(&ddrc_regs->addrmap2);\n+\tfield_val = (reg_val & ADDRMAP2_COL_B2_MASK) >> ADDRMAP2_COL_B2_SHIFT;\n+\tif (field_val <= 7)\n+\t\tbits++;\n+\tfield_val = (reg_val & ADDRMAP2_COL_B3_MASK) >> ADDRMAP2_COL_B3_SHIFT;\n+\tif (field_val <= 7)\n+\t\tbits++;\n+\tfield_val = (reg_val & ADDRMAP2_COL_B4_MASK) >> ADDRMAP2_COL_B4_SHIFT;\n+\tif (field_val <= 7)\n+\t\tbits++;\n+\tfield_val = (reg_val & ADDRMAP2_COL_B5_MASK) >> ADDRMAP2_COL_B5_SHIFT;\n+\tif (field_val <= 7)\n+\t\tbits++;\n+\treg_val = readl(&ddrc_regs->addrmap3);\n+\tfield_val = (reg_val & ADDRMAP3_COL_B6_MASK) >> ADDRMAP3_COL_B6_SHIFT;\n+\tif (field_val <= 7)\n+\t\tbits++;\n+\tfield_val = (reg_val & ADDRMAP3_COL_B7_MASK) >> ADDRMAP3_COL_B7_SHIFT;\n+\tif (field_val <= 7)\n+\t\tbits++;\n+\tfield_val = (reg_val & ADDRMAP3_COL_B8_MASK) >> ADDRMAP3_COL_B8_SHIFT;\n+\tif (field_val <= 7)\n+\t\tbits++;\n+\tfield_val = (reg_val & ADDRMAP3_COL_B9_MASK) >> ADDRMAP3_COL_B9_SHIFT;\n+\tif (field_val <= 7)\n+\t\tbits++;\n+\treg_val = readl(&ddrc_regs->addrmap4);\n+\tfield_val = (reg_val & ADDRMAP4_COL_B10_MASK) >> ADDRMAP4_COL_B10_SHIFT;\n+\tif (field_val <= 7)\n+\t\tbits++;\n+\tfield_val = (reg_val & ADDRMAP4_COL_B11_MASK) >> ADDRMAP4_COL_B11_SHIFT;\n+\tif (field_val <= 7)\n+\t\tbits++;\n+\t/* Count row address bits */\n+\treg_val = readl(&ddrc_regs->addrmap5);\n+\tfield_val = (reg_val & ADDRMAP5_ROW_B0_MASK) >> ADDRMAP5_ROW_B0_SHIFT;\n+\tif (field_val <= 11)\n+\t\tbits++;\n+\tfield_val = (reg_val & ADDRMAP5_ROW_B1_MASK) >> ADDRMAP5_ROW_B1_SHIFT;\n+\tif (field_val <= 11)\n+\t\tbits++;\n+\tfield_val = (reg_val & ADDRMAP5_ROW_B2_10_MASK) >> ADDRMAP5_ROW_B2_10_SHIFT;\n+\tif (field_val <= 11)\n+\t\tbits += 9;\n+\tfield_val = (reg_val & ADDRMAP5_ROW_B11_MASK) >> ADDRMAP5_ROW_B11_SHIFT;\n+\tif (field_val <= 11)\n+\t\tbits++;\n+\treg_val = readl(&ddrc_regs->addrmap6);\n+\tfield_val = (reg_val & ADDRMAP6_ROW_B12_MASK) >> ADDRMAP6_ROW_B12_SHIFT;\n+\tif (field_val <= 11)\n+\t\tbits++;\n+\tfield_val = (reg_val & ADDRMAP6_ROW_B13_MASK) >> ADDRMAP6_ROW_B13_SHIFT;\n+\tif (field_val <= 11)\n+\t\tbits++;\n+\tfield_val = (reg_val & ADDRMAP6_ROW_B14_MASK) >> ADDRMAP6_ROW_B14_SHIFT;\n+\tif (field_val <= 11)\n+\t\tbits++;\n+\tfield_val = (reg_val & ADDRMAP6_ROW_B15_MASK) >> ADDRMAP6_ROW_B15_SHIFT;\n+\tif (field_val <= 11)\n+\t\tbits++;\n+\t/* Count bank bits */\n+\treg_val = readl(&ddrc_regs->addrmap1);\n+\tfield_val = (reg_val & ADDRMAP1_BANK_B0_MASK) >> ADDRMAP1_BANK_B0_SHIFT;\n+\tif (field_val <= 30)\n+\t\tbits++;\n+\tfield_val = (reg_val & ADDRMAP1_BANK_B1_MASK) >> ADDRMAP1_BANK_B1_SHIFT;\n+\tif (field_val <= 30)\n+\t\tbits++;\n+\tfield_val = (reg_val & ADDRMAP1_BANK_B2_MASK) >> ADDRMAP1_BANK_B2_SHIFT;\n+\tif (field_val <= 29)\n+\t\tbits++;\n+\n+\treturn 1 << bits;\n+}\n", "prefixes": [ "U-Boot", "2/4" ] }