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GET /api/patches/817651/?format=api
{ "id": 817651, "url": "http://patchwork.ozlabs.org/api/patches/817651/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170922171323.10348-6-f4bug@amsat.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170922171323.10348-6-f4bug@amsat.org>", "list_archive_url": null, "date": "2017-09-22T17:13:21", "name": "[v5,5/7] hw/mdio: Refactor bitbanging state machine", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "fae14cd5d52445c60acd3840ace26e918bea56cd", "submitter": { "id": 70924, "url": "http://patchwork.ozlabs.org/api/people/70924/?format=api", "name": "Philippe Mathieu-Daudé", "email": "f4bug@amsat.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170922171323.10348-6-f4bug@amsat.org/mbox/", "series": [ { "id": 4680, "url": "http://patchwork.ozlabs.org/api/series/4680/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=4680", "date": "2017-09-22T17:13:16", "name": "Generalize MDIO framework", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/4680/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/817651/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/817651/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"qFfaHUty\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xzKpv13vdz9s7h\n\tfor <incoming@patchwork.ozlabs.org>;\n\tSat, 23 Sep 2017 03:14:47 +1000 (AEST)", "from localhost ([::1]:60284 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dvRXJ-0003de-5H\n\tfor incoming@patchwork.ozlabs.org; Fri, 22 Sep 2017 13:14:45 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:59434)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <philippe.mathieu.daude@gmail.com>)\n\tid 1dvRWW-0003Zl-I7\n\tfor qemu-devel@nongnu.org; Fri, 22 Sep 2017 13:13:58 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <philippe.mathieu.daude@gmail.com>)\n\tid 1dvRWU-0003Xn-Lr\n\tfor qemu-devel@nongnu.org; Fri, 22 Sep 2017 13:13:56 -0400", "from mail-qk0-x244.google.com ([2607:f8b0:400d:c09::244]:36708)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <philippe.mathieu.daude@gmail.com>)\n\tid 1dvRWU-0003Wu-GZ\n\tfor qemu-devel@nongnu.org; Fri, 22 Sep 2017 13:13:54 -0400", "by mail-qk0-x244.google.com with SMTP id i14so1025392qke.3\n\tfor <qemu-devel@nongnu.org>; Fri, 22 Sep 2017 10:13:54 -0700 (PDT)", "from yoga.lan ([181.93.89.178]) by smtp.gmail.com with ESMTPSA id\n\tf69sm238468qke.27.2017.09.22.10.13.51\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tFri, 22 Sep 2017 10:13:53 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=sender:from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=RlV+UKksAkV+37i3nDePyzlUjXAz8TI33VoE13qtgXY=;\n\tb=qFfaHUtym48GrRLTLg887ESkgBlFF3fNHsp2EAY3WKUaPyLLm2Qt4I2ykn2XbqQMGV\n\tX7+KiC1suKxc8G2Ob80pZFVSUBwgo+CDHaC9/mEht64ek1UTYpFC1Mv3kWiymBQbxhv7\n\tMXd+ntcz7Zouf0+5lXX/ai7hBPdEhugzueqUYkyjjc9UxzIYSSr+N/RqydEMPNRTUGRN\n\tWlkSzGpHJSAbpmqiMepQp9Ysz5RhhAi0td49qdwDiEVv9vE4gBLvfLNA3hnwhzcQJZsk\n\tw4XcK/BjtAFKPpZ5NA0u2EA9DfXogBem1X9YYhCWAUqumTj1IK6fYcIz/CoFCSk0pm2L\n\tj8pg==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:sender:from:to:cc:subject:date:message-id\n\t:in-reply-to:references:mime-version:content-transfer-encoding;\n\tbh=RlV+UKksAkV+37i3nDePyzlUjXAz8TI33VoE13qtgXY=;\n\tb=ez1Zq79khX2O7AhbgIGDGamjnKsTdd5nbcpXMQE9IvPXTj/3foQX/CIZcoCpg4Dqwx\n\tr3Wkf090r31enApB9x5iti17EQsjZOs/V3XDkIvuNejXI+k5oiUnUj4cakAmXKcoT0Mn\n\toV2EP6EVsbnSfc3nv1Yi28DkAatdZi+b2etE6qKX24BKxbFHZqVkiT+9htWfO68Uo3IL\n\trVA6baL5aEu/0d9h0kk3wTdxjoV7pXWzRvxXkHWzB//7U1gJh/wuwBhJbQkA0yuuMtXW\n\tgUEyLTtzUp+4YBnv0u9CshTI3yRkZeLZp3rnz2QMViFwbJSz0Y7ZGkwWIs4RA5oV5zJb\n\ttkzg==", "X-Gm-Message-State": "AHPjjUgzSn898n6wMmDuCbNIzy/th/DXPfnxV72soWis4pphj7FjHFPp\n\t+HurRQAc4tedPF76tq4N3Fw=", "X-Google-Smtp-Source": "AOwi7QCrQadcZ75w8oIvsYc37Ii8SFU0MftGP5ZORh/tkKwjh8gm4/hN4OGMQFamrWxi/1UuOREAuQ==", "X-Received": "by 10.55.141.66 with SMTP id p63mr1625658qkd.314.1506100433928; \n\tFri, 22 Sep 2017 10:13:53 -0700 (PDT)", "From": "=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <f4bug@amsat.org>", "To": "Peter Maydell <peter.maydell@linaro.org>,\n\t\"Edgar E. Iglesias\" <edgar.iglesias@gmail.com>,\n\tGrant Likely <grant.likely@arm.com>, Jason Wang <jasowang@redhat.com>", "Date": "Fri, 22 Sep 2017 14:13:21 -0300", "Message-Id": "<20170922171323.10348-6-f4bug@amsat.org>", "X-Mailer": "git-send-email 2.14.1", "In-Reply-To": "<20170922171323.10348-1-f4bug@amsat.org>", "References": "<20170922171323.10348-1-f4bug@amsat.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400d:c09::244", "Subject": "[Qemu-devel] [PATCH v5 5/7] hw/mdio: Refactor bitbanging state\n\tmachine", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "qemu-devel@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?=\n\t<f4bug@amsat.org>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Grant Likely <grant.likely@arm.com>\n\nThe MDIO state machine has a moderate amount of duplicate code in the\nstate processing that can be consolidated. This patch does so and\nreorganizes it a bit so that far less code is required. Most of the\nstates simply stream a fixed number of bits in as a single integer and\ncan be handled by a common processing function that checks for\ncompletion of the state and returns the streamed in value.\n\nChanges include:\n- Move clock state change tracking into core code\n- Use a common shift register for clocking data in and out\n- Create separate mdc & mdio accessor functions\n - will be replaced with GPIO connection in a follow-on patch\n\nSigned-off-by: Grant Likely <grant.likely@arm.com>\nSigned-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>\n[PMD: just rebased]\n---\n include/hw/net/mdio.h | 41 ++++++++-------\n hw/net/etraxfs_eth.c | 11 ++--\n hw/net/mdio.c | 140 ++++++++++++++++++++++----------------------------\n 3 files changed, 87 insertions(+), 105 deletions(-)", "diff": "diff --git a/include/hw/net/mdio.h b/include/hw/net/mdio.h\nindex ed1879a728..7fca19784e 100644\n--- a/include/hw/net/mdio.h\n+++ b/include/hw/net/mdio.h\n@@ -52,37 +52,33 @@\n #define PHY_ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */\n \n struct qemu_phy {\n- uint32_t regs[NUM_PHY_REGS];\n+ uint16_t regs[NUM_PHY_REGS];\n const uint16_t *regs_readonly_mask; /* 0=writable, 1=read-only */\n \n- int link;\n+ bool link;\n \n- unsigned int (*read)(struct qemu_phy *phy, unsigned int req);\n- void (*write)(struct qemu_phy *phy, unsigned int req, unsigned int data);\n+ uint16_t (*read)(struct qemu_phy *phy, unsigned int req);\n+ void (*write)(struct qemu_phy *phy, unsigned int req, uint16_t data);\n };\n \n struct qemu_mdio {\n- /* bus. */\n- int mdc;\n- int mdio;\n-\n- /* decoder. */\n+ /* bitbanging state machine */\n+ bool mdc;\n+ bool mdio;\n enum {\n PREAMBLE,\n- SOF,\n OPC,\n ADDR,\n REQ,\n TURNAROUND,\n DATA\n } state;\n- unsigned int drive;\n \n- unsigned int cnt;\n- unsigned int addr;\n- unsigned int opc;\n- unsigned int req;\n- unsigned int data;\n+ uint16_t cnt; /* Bit count for current state */\n+ uint16_t addr; /* PHY Address; retrieved during ADDR state */\n+ uint16_t opc; /* Operation; 2:read */\n+ uint16_t req; /* Register address */\n+ uint32_t shiftreg; /* shift register; bits in to or out from PHY */\n \n struct qemu_phy *devs[32];\n };\n@@ -91,7 +87,16 @@ void mdio_phy_init(struct qemu_phy *phy, uint16_t id1, uint16_t id2);\n void mdio_attach(struct qemu_mdio *bus, struct qemu_phy *phy,\n unsigned int addr);\n uint16_t mdio_read_req(struct qemu_mdio *bus, uint8_t addr, uint8_t req);\n-void mdio_write_req(struct qemu_mdio *bus, uint8_t addr, uint8_t req, uint16_t data);\n-void mdio_cycle(struct qemu_mdio *bus);\n+void mdio_write_req(struct qemu_mdio *bus, uint8_t addr, uint8_t req,\n+ uint16_t data);\n+void mdio_bitbang_set_clk(struct qemu_mdio *bus, bool mdc);\n+static inline void mdio_bitbang_set_data(struct qemu_mdio *bus, bool mdio)\n+{\n+ bus->mdio = mdio;\n+}\n+static inline bool mdio_bitbang_get_data(struct qemu_mdio *bus)\n+{\n+ return bus->mdio;\n+}\n \n #endif\ndiff --git a/hw/net/etraxfs_eth.c b/hw/net/etraxfs_eth.c\nindex 4c5415771f..1b518ea16e 100644\n--- a/hw/net/etraxfs_eth.c\n+++ b/hw/net/etraxfs_eth.c\n@@ -119,7 +119,7 @@ eth_read(void *opaque, hwaddr addr, unsigned int size)\n \n switch (addr) {\n case R_STAT:\n- r = eth->mdio_bus.mdio & 1;\n+ r = mdio_bitbang_get_data(ð->mdio_bus);\n break;\n default:\n r = eth->regs[addr];\n@@ -177,13 +177,10 @@ eth_write(void *opaque, hwaddr addr,\n case RW_MGM_CTRL:\n /* Attach an MDIO/PHY abstraction. */\n if (value & 2) {\n- eth->mdio_bus.mdio = value & 1;\n+ mdio_bitbang_set_data(ð->mdio_bus, value & 1);\n }\n- if (eth->mdio_bus.mdc != (value & 4)) {\n- mdio_cycle(ð->mdio_bus);\n- eth_validate_duplex(eth);\n- }\n- eth->mdio_bus.mdc = !!(value & 4);\n+ mdio_bitbang_set_clk(ð->mdio_bus, value & 4);\n+ eth_validate_duplex(eth);\n eth->regs[addr] = value;\n break;\n \ndiff --git a/hw/net/mdio.c b/hw/net/mdio.c\nindex 89a6a3a590..96e10fada0 100644\n--- a/hw/net/mdio.c\n+++ b/hw/net/mdio.c\n@@ -43,7 +43,7 @@\n * linux driver (PHYID and Diagnostics reg).\n * TODO: Add friendly names for the register nums.\n */\n-static unsigned int mdio_phy_read(struct qemu_phy *phy, unsigned int req)\n+static uint16_t mdio_phy_read(struct qemu_phy *phy, unsigned int req)\n {\n int regnum;\n unsigned r = 0;\n@@ -107,7 +107,8 @@ static unsigned int mdio_phy_read(struct qemu_phy *phy, unsigned int req)\n return r;\n }\n \n-static void mdio_phy_write(struct qemu_phy *phy, unsigned int req, unsigned int data)\n+static void mdio_phy_write(struct qemu_phy *phy, unsigned int req,\n+ uint16_t data)\n {\n int regnum = req & 0x1f;\n uint16_t mask = phy->regs_readonly_mask[regnum];\n@@ -136,13 +137,14 @@ void mdio_phy_init(struct qemu_phy *phy, uint16_t id1, uint16_t id2)\n /* Autonegotiation advertisement reg. */\n phy->regs[PHY_AUTONEG_ADV] = 0x01e1;\n phy->regs_readonly_mask = default_readonly_mask;\n- phy->link = 1;\n+ phy->link = true;\n \n phy->read = mdio_phy_read;\n phy->write = mdio_phy_write;\n }\n \n-void mdio_attach(struct qemu_mdio *bus, struct qemu_phy *phy, unsigned int addr)\n+void mdio_attach(struct qemu_mdio *bus, struct qemu_phy *phy,\n+ unsigned int addr)\n {\n bus->devs[addr & 0x1f] = phy;\n }\n@@ -169,99 +171,77 @@ void mdio_write_req(struct qemu_mdio *bus, uint8_t addr, uint8_t req,\n }\n }\n \n-void mdio_cycle(struct qemu_mdio *bus)\n+/**\n+ * mdio_bitbang_update() - internal function to check how many clocks have\n+ * passed and move to the next state if necessary. Returns TRUE on state change.\n+ */\n+static bool mdio_bitbang_update(struct qemu_mdio *bus, int num_bits, int next,\n+ uint16_t *reg)\n {\n+ if (bus->cnt < num_bits) {\n+ return false;\n+ }\n+ if (reg) {\n+ *reg = bus->shiftreg;\n+ }\n+ bus->state = next;\n+ bus->cnt = 0;\n+ bus->shiftreg = 0;\n+ return true;\n+}\n+\n+/**\n+ * mdio_bitbang_set_clk() - set value of mdc signal and update state\n+ */\n+void mdio_bitbang_set_clk(struct qemu_mdio *bus, bool mdc)\n+{\n+ uint16_t tmp;\n+\n+ if (mdc == bus->mdc) {\n+ return; /* Clock state hasn't changed; do nothing */\n+ }\n+\n+ bus->mdc = mdc;\n+ if (bus->mdc) {\n+ /* Falling (inactive) clock edge */\n+ if ((bus->state == DATA) && (bus->opc == 2)) {\n+ bus->mdio = !!(bus->shiftreg & 0x8000);\n+ }\n+ return;\n+ }\n+\n+ /* Rising clock Edge */\n+ bus->shiftreg = (bus->shiftreg << 1) | bus->mdio;\n bus->cnt++;\n-\n D(printf(\"mdc=%d mdio=%d state=%d cnt=%d drv=%d\\n\",\n- bus->mdc, bus->mdio, bus->state, bus->cnt, bus->drive));\n+ bus->mdc, bus->mdio, bus->state, bus->cnt));\n switch (bus->state) {\n case PREAMBLE:\n- if (bus->mdc) {\n- if (bus->cnt >= (32 * 2) && !bus->mdio) {\n- bus->cnt = 0;\n- bus->state = SOF;\n- bus->data = 0;\n- }\n- }\n- break;\n- case SOF:\n- if (bus->mdc) {\n- if (bus->mdio != 1) {\n- printf(\"WARNING: no SOF\\n\");\n- }\n- if (bus->cnt == 1 * 2) {\n- bus->cnt = 0;\n- bus->opc = 0;\n- bus->state = OPC;\n- }\n+ /* MDIO must be 30 clocks high, 1 low, and 1 high to get out of\n+ preamble */\n+ if (bus->shiftreg == 0xfffffffd) {\n+ mdio_bitbang_update(bus, 0, OPC, NULL);\n }\n break;\n case OPC:\n- if (bus->mdc) {\n- bus->opc <<= 1;\n- bus->opc |= bus->mdio & 1;\n- if (bus->cnt == 2 * 2) {\n- bus->cnt = 0;\n- bus->addr = 0;\n- bus->state = ADDR;\n- }\n- }\n+ mdio_bitbang_update(bus, 2, ADDR, &bus->opc);\n break;\n case ADDR:\n- if (bus->mdc) {\n- bus->addr <<= 1;\n- bus->addr |= bus->mdio & 1;\n-\n- if (bus->cnt == 5 * 2) {\n- bus->cnt = 0;\n- bus->req = 0;\n- bus->state = REQ;\n- }\n- }\n+ mdio_bitbang_update(bus, 5, REQ, &bus->addr);\n break;\n case REQ:\n- if (bus->mdc) {\n- bus->req <<= 1;\n- bus->req |= bus->mdio & 1;\n- if (bus->cnt == 5 * 2) {\n- bus->cnt = 0;\n- bus->state = TURNAROUND;\n- }\n- }\n+ mdio_bitbang_update(bus, 5, TURNAROUND, &bus->req);\n break;\n case TURNAROUND:\n- if (bus->mdc && bus->cnt == 2 * 2) {\n- bus->mdio = 0;\n- bus->cnt = 0;\n-\n- if (bus->opc == 2) {\n- bus->drive = 1;\n- bus->data = mdio_read_req(bus, bus->addr, bus->req);\n- bus->mdio = bus->data & 1;\n- }\n- bus->state = DATA;\n+ /* If beginning of DATA READ cycle, then read PHY into shift register */\n+ if (mdio_bitbang_update(bus, 2, DATA, NULL) && (bus->opc == 2)) {\n+ bus->shiftreg = mdio_read_req(bus, bus->addr, bus->req);\n }\n break;\n case DATA:\n- if (!bus->mdc) {\n- if (bus->drive) {\n- bus->mdio = !!(bus->data & (1 << 15));\n- bus->data <<= 1;\n- }\n- } else {\n- if (!bus->drive) {\n- bus->data <<= 1;\n- bus->data |= bus->mdio;\n- }\n- if (bus->cnt == 16 * 2) {\n- bus->cnt = 0;\n- bus->state = PREAMBLE;\n- if (!bus->drive) {\n- mdio_write_req(bus, bus->addr, bus->req, bus->data);\n- }\n- bus->drive = 0;\n- }\n+ /* If end of DATA WRITE cycle, then write shift register to PHY */\n+ if (mdio_bitbang_update(bus, 16, PREAMBLE, &tmp) && (bus->opc == 1)) {\n+ mdio_write_req(bus, bus->addr, bus->req, tmp);\n }\n break;\n default:\n", "prefixes": [ "v5", "5/7" ] }