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GET /api/patches/817562/?format=api
{ "id": 817562, "url": "http://patchwork.ozlabs.org/api/patches/817562/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1506092407-26985-12-git-send-email-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1506092407-26985-12-git-send-email-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2017-09-22T14:59:58", "name": "[11/20] target/arm: Add support for restoring v8M additional state context", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "a4dcfd8838948f5970153ece71fff7af5bddede2", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1506092407-26985-12-git-send-email-peter.maydell@linaro.org/mbox/", "series": [ { "id": 4650, "url": "http://patchwork.ozlabs.org/api/series/4650/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=4650", "date": "2017-09-22T14:59:47", "name": "ARM v8M: exception entry, exit and security", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/4650/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/817562/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/817562/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xzGvw3Bn1z9sNr\n\tfor <incoming@patchwork.ozlabs.org>;\n\tSat, 23 Sep 2017 01:03:56 +1000 (AEST)", "from localhost ([::1]:59332 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dvPUg-0002UO-I6\n\tfor incoming@patchwork.ozlabs.org; Fri, 22 Sep 2017 11:03:54 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:47134)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1dvPQd-00081n-38\n\tfor qemu-devel@nongnu.org; Fri, 22 Sep 2017 10:59:44 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1dvPQc-0004CT-4Q\n\tfor qemu-devel@nongnu.org; Fri, 22 Sep 2017 10:59:43 -0400", "from orth.archaic.org.uk ([2001:8b0:1d0::2]:37556)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <pm215@archaic.org.uk>)\n\tid 1dvPQZ-00043B-Bp; Fri, 22 Sep 2017 10:59:39 -0400", "from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from <pm215@archaic.org.uk>)\n\tid 1dvPQX-0007Cf-AG; Fri, 22 Sep 2017 15:59:37 +0100" ], "From": "Peter Maydell <peter.maydell@linaro.org>", "To": "qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org", "Date": "Fri, 22 Sep 2017 15:59:58 +0100", "Message-Id": "<1506092407-26985-12-git-send-email-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1506092407-26985-1-git-send-email-peter.maydell@linaro.org>", "References": "<1506092407-26985-1-git-send-email-peter.maydell@linaro.org>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2001:8b0:1d0::2", "Subject": "[Qemu-devel] [PATCH 11/20] target/arm: Add support for restoring\n\tv8M additional state context", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "patches@linaro.org", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "For v8M, exceptions from Secure to Non-Secure state will save\ncallee-saved registers to the exception frame as well as the\ncaller-saved registers. Add support for unstacking these\nregisters in exception exit when necessary.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n target/arm/helper.c | 30 ++++++++++++++++++++++++++++++\n 1 file changed, 30 insertions(+)", "diff": "diff --git a/target/arm/helper.c b/target/arm/helper.c\nindex da3a36e..25f5675 100644\n--- a/target/arm/helper.c\n+++ b/target/arm/helper.c\n@@ -6453,6 +6453,36 @@ static void do_v7m_exception_exit(ARMCPU *cpu)\n \"for destination state is UNPREDICTABLE\\n\");\n }\n \n+ /* Do we need to pop callee-saved registers? */\n+ if (return_to_secure &&\n+ ((excret & R_V7M_EXCRET_ES_MASK) == 0 ||\n+ (excret & R_V7M_EXCRET_DCRS_MASK) == 0)) {\n+ uint32_t expected_sig = 0xfefa125b;\n+ uint32_t actual_sig = ldl_phys(cs->as, frameptr);\n+\n+ if (expected_sig != actual_sig) {\n+ /* Take a SecureFault on the current stack */\n+ env->v7m.sfsr |= R_V7M_SFSR_INVIS_MASK;\n+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false);\n+ v7m_exception_taken(cpu, excret);\n+ qemu_log_mask(CPU_LOG_INT, \"...taking SecureFault on existing \"\n+ \"stackframe: failed exception return integrity \"\n+ \"signature check\\n\");\n+ return;\n+ }\n+\n+ env->regs[4] = ldl_phys(cs->as, frameptr + 0x8);\n+ env->regs[5] = ldl_phys(cs->as, frameptr + 0xc);\n+ env->regs[6] = ldl_phys(cs->as, frameptr + 0x10);\n+ env->regs[7] = ldl_phys(cs->as, frameptr + 0x14);\n+ env->regs[8] = ldl_phys(cs->as, frameptr + 0x18);\n+ env->regs[9] = ldl_phys(cs->as, frameptr + 0x1c);\n+ env->regs[10] = ldl_phys(cs->as, frameptr + 0x20);\n+ env->regs[11] = ldl_phys(cs->as, frameptr + 0x24);\n+\n+ frameptr += 0x28;\n+ }\n+\n /* Pop registers. TODO: make these accesses use the correct\n * attributes and address space (S/NS, priv/unpriv) and handle\n * memory transaction failures.\n", "prefixes": [ "11/20" ] }