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{
    "id": 817361,
    "url": "http://patchwork.ozlabs.org/api/patches/817361/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20170922072522.36306-3-Zhiqiang.Hou@nxp.com/",
    "project": {
        "id": 28,
        "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api",
        "name": "Linux PCI development",
        "link_name": "linux-pci",
        "list_id": "linux-pci.vger.kernel.org",
        "list_email": "linux-pci@vger.kernel.org",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
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        "list_archive_url_format": "",
        "commit_url_format": ""
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    "msgid": "<20170922072522.36306-3-Zhiqiang.Hou@nxp.com>",
    "list_archive_url": null,
    "date": "2017-09-22T07:25:22",
    "name": "[2/2] pci/layerscape: change the default error response behavior",
    "commit_ref": null,
    "pull_url": null,
    "state": "not-applicable",
    "archived": false,
    "hash": "e70a24532b08d3efda9b87ddcd5fd98d3acf54d7",
    "submitter": {
        "id": 67929,
        "url": "http://patchwork.ozlabs.org/api/people/67929/?format=api",
        "name": "Z.Q. Hou",
        "email": "zhiqiang.hou@nxp.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20170922072522.36306-3-Zhiqiang.Hou@nxp.com/mbox/",
    "series": [
        {
            "id": 4558,
            "url": "http://patchwork.ozlabs.org/api/series/4558/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=4558",
            "date": "2017-09-22T07:25:22",
            "name": "PCI: layerscape: add fixes for layerscape-pcie errata",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/4558/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/817361/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/817361/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Zhiqiang Hou <Zhiqiang.Hou@nxp.com>",
        "To": "<linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>,\n\t<linux-pci@vger.kernel.org>, <bhelgaas@google.com>,\n\t<roy.zang@nxp.com>, <mingkai.hu@nxp.com>, <minghuan.lian@nxp.com>",
        "CC": "Minghuan Lian <Minghuan.Lian@nxp.com>,\n\tHou Zhiqiang <Zhiqiang.Hou@nxp.com>",
        "Subject": "[PATCH 2/2] pci/layerscape: change the default error response\n\tbehavior",
        "Date": "Fri, 22 Sep 2017 15:25:22 +0800",
        "Message-ID": "<20170922072522.36306-3-Zhiqiang.Hou@nxp.com>",
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        "References": "<20170922072522.36306-1-Zhiqiang.Hou@nxp.com>",
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        "Sender": "linux-pci-owner@vger.kernel.org",
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        "List-ID": "<linux-pci.vger.kernel.org>",
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    "content": "From: Minghuan Lian <Minghuan.Lian@nxp.com>\n\nBy default, when the PCIe controller experiences an erroneous\ncompletion from an external completer for its outbound non-posted\nrequest, it always sends an OKAY response to the device's internal\nAXI slave system interface. However, such default system error\nresponse behavior cannot be used for other types of outbound\nnon-posted requests. For example, the outbound memory read\ntransaction requires an actual ERROR response, like UR completion\nor completion timeout. The patch is to fix it by forwarding\nthe error response of the non-posted request.\n\nSigned-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>\nSigned-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>\n---\n drivers/pci/dwc/pci-layerscape.c | 25 +++++++++++++++++++++++++\n 1 file changed, 25 insertions(+)",
    "diff": "diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c\nindex 3b01e309a55e..a647090c140e 100644\n--- a/drivers/pci/dwc/pci-layerscape.c\n+++ b/drivers/pci/dwc/pci-layerscape.c\n@@ -33,6 +33,8 @@\n \n /* PEX Internal Configuration Registers */\n #define PCIE_STRFMR1\t\t0x71c /* Symbol Timer & Filter Mask Register1 */\n+#define PCIE_ABSERR\t\t0x8d0 /* Bridge Slave Error Response Register */\n+#define PCIE_ABSERR_SETTING\t0x9401 /* Forward error of non-posted request */\n \n #define PCIE_IATU_NUM\t\t6\n \n@@ -54,6 +56,19 @@ struct ls_pcie {\n \n #define to_ls_pcie(x)\tdev_get_drvdata((x)->dev)\n \n+static int err_response_flag = 1;\n+\n+static int __init ls_pcie_param(char *p)\n+{\n+\tif (p && strncmp(p, \"no-err-response\", 15) == 0)\n+\t\terr_response_flag = 0;\n+\telse\n+\t\terr_response_flag = 1;\n+\n+\treturn 0;\n+}\n+early_param(\"ls_pcie\", ls_pcie_param);\n+\n static bool ls_pcie_is_bridge(struct ls_pcie *pcie)\n {\n \tstruct dw_pcie *pci = pcie->pci;\n@@ -124,6 +139,14 @@ static int ls_pcie_link_up(struct dw_pcie *pci)\n \treturn 1;\n }\n \n+/* Forward error response of outbound non-posted requests */\n+static void ls_pcie_fix_error_response(struct ls_pcie *pcie)\n+{\n+\tstruct dw_pcie *pci = pcie->pci;\n+\n+\tiowrite32(PCIE_ABSERR_SETTING, pci->dbi_base + PCIE_ABSERR);\n+}\n+\n static int ls_pcie_host_init(struct pcie_port *pp)\n {\n \tstruct dw_pcie *pci = to_dw_pcie_from_pp(pp);\n@@ -135,6 +158,8 @@ static int ls_pcie_host_init(struct pcie_port *pp)\n \t * dw_pcie_setup_rc() will reconfigure the outbound windows.\n \t */\n \tls_pcie_disable_outbound_atus(pcie);\n+\tif (err_response_flag)\n+\t\tls_pcie_fix_error_response(pcie);\n \n \tdw_pcie_dbi_ro_wr_en(pci);\n \tls_pcie_clear_multifunction(pcie);\n",
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}