Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/817315/?format=api
{ "id": 817315, "url": "http://patchwork.ozlabs.org/api/patches/817315/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-mtd/patch/1506052009-8285-12-git-send-email-yamada.masahiro@socionext.com/", "project": { "id": 3, "url": "http://patchwork.ozlabs.org/api/projects/3/?format=api", "name": "Linux MTD development", "link_name": "linux-mtd", "list_id": "linux-mtd.lists.infradead.org", "list_email": "linux-mtd@lists.infradead.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1506052009-8285-12-git-send-email-yamada.masahiro@socionext.com>", "list_archive_url": null, "date": "2017-09-22T03:46:48", "name": "[v2,11/12] mtd: nand: denali: support direct addressing mode", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "93800fded26c1be567249777bb4ae050c7b85a7d", "submitter": { "id": 65882, "url": "http://patchwork.ozlabs.org/api/people/65882/?format=api", "name": "Masahiro Yamada", "email": "yamada.masahiro@socionext.com" }, "delegate": { "id": 58324, "url": "http://patchwork.ozlabs.org/api/users/58324/?format=api", "username": "bbrezillon", "first_name": "Boris", "last_name": "Brezillon", "email": "boris.brezillon@free-electrons.com" }, "mbox": "http://patchwork.ozlabs.org/project/linux-mtd/patch/1506052009-8285-12-git-send-email-yamada.masahiro@socionext.com/mbox/", "series": [ { "id": 4537, "url": "http://patchwork.ozlabs.org/api/series/4537/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-mtd/list/?series=4537", "date": "2017-09-22T03:46:37", "name": "mtd: nand: denali: more clean-ups", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/4537/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/817315/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/817315/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org; spf=none (mailfrom)\n\tsmtp.mailfrom=lists.infradead.org (client-ip=65.50.211.133;\n\thelo=bombadil.infradead.org;\n\tenvelope-from=linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"hP/QMgcr\"; \n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=nifty.com header.i=@nifty.com\n\theader.b=\"BC2Ue3oN\"; dkim-atps=neutral" ], "Received": [ "from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xz0126Y5gz9ryk\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 22 Sep 2017 13:52:22 +1000 (AEST)", "from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dvF0P-0008NQ-6a; Fri, 22 Sep 2017 03:51:57 +0000", "from conuserg-09.nifty.com ([210.131.2.76])\n\tby bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dvEwJ-0004Fc-3Q\n\tfor linux-mtd@lists.infradead.org; Fri, 22 Sep 2017 03:47:51 +0000", "from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp\n\t[153.142.97.92]) (authenticated)\n\tby conuserg-09.nifty.com with ESMTP id v8M3kwAU029389;\n\tFri, 22 Sep 2017 12:47:08 +0900" ], "DKIM-Signature": [ "v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe:\n\tList-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References:\n\tIn-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID:\n\tContent-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc\n\t:Resent-Message-ID:List-Owner;\n\tbh=kY38bvjN6V087HPeFDrjjBRuUZ/VF2Gjll8BuNnx46Y=;\n\tb=hP/QMgcrRKVZRyDMTNYuSismSL\n\t50J7hkU29sBQV45XVkY1FMNt99maOXETi1DkEKw9qY7J20EXGIKSp8/L7Vp5JUj9C+EngtU3p37ys\n\tjRQrtz/rH+5BxE66ozb0ORt2DguBcr3PuhC4x2fJh4Enhm2eaGh6swtobjaSQ3aV2Ri6hpUwRL2Fq\n\tWCjp2zYvRZOcP3T3Qu95OhN/aa08mMY+jJozvRzt/0umK1DlmPxZJxJY1IFMtLVhsETUqyhPZwdH6\n\taotoXN56f511DZ1UlSIixHgR5Kcc8Rn3X9hQ92GLoqSok+EMhPpAHeJ8jMViLAv3rgA7Wvhgow8Ha\n\tokxwak7g==;", "v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com;\n\ts=dec2015msa; t=1506052029;\n\tbh=/CFjeb58SmX5wca+i9MbQrGzEJUS5WnR+N8vlXmF7VY=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n\tb=BC2Ue3oNJRlYmegAc3T6H9lWll7sEePt+lhkd/IQmp6yL+P0Eese5JT8uNR5fHn9s\n\tjdlQS+eXdvq406Mc4umHxMTu9qPF0DowEIiuoAsLGsr9r+pundKX/XAUel5lTd0HBE\n\t7q0nVaAzCLKbG7WpRUgu6cQfTb0NQZf/eaprejN5yHiLmh2FBGaaKyQtzjOi/i2EZW\n\taq5R6BBECzbnWM1Vq2IKvnepnbBDo/Q8kdfTqo5H7aiPc7qm/dE+4sX8FWPmtYQ1tm\n\tfzudKQ2sMf6/mQCL0QqWxwy57+Tg8hwl6XbUGTFDgB7zjInMcpOMXGNZ5PaPNUu60h\n\tMeopNo7McPr/A==" ], "DKIM-Filter": "OpenDKIM Filter v2.10.3 conuserg-09.nifty.com v8M3kwAU029389", "X-Nifty-SrcIP": "[153.142.97.92]", "From": "Masahiro Yamada <yamada.masahiro@socionext.com>", "To": "linux-mtd@lists.infradead.org", "Subject": "[PATCH v2 11/12] mtd: nand: denali: support direct addressing mode", "Date": "Fri, 22 Sep 2017 12:46:48 +0900", "Message-Id": "<1506052009-8285-12-git-send-email-yamada.masahiro@socionext.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1506052009-8285-1-git-send-email-yamada.masahiro@socionext.com>", "References": "<1506052009-8285-1-git-send-email-yamada.masahiro@socionext.com>", "X-CRM114-Version": "20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ", "X-CRM114-CacheID": "sfid-20170921_204743_526931_4A3D9731 ", "X-CRM114-Status": "GOOD ( 17.64 )", "X-Spam-Score": "-1.2 (-)", "X-Spam-Report": "SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-1.2 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t0.7 SPF_SOFTFAIL SPF: sender does not match SPF record (softfail)\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid", "X-BeenThere": "linux-mtd@lists.infradead.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "Linux MTD discussion mailing list <linux-mtd.lists.infradead.org>", "List-Unsubscribe": "<http://lists.infradead.org/mailman/options/linux-mtd>,\n\t<mailto:linux-mtd-request@lists.infradead.org?subject=unsubscribe>", "List-Archive": "<http://lists.infradead.org/pipermail/linux-mtd/>", "List-Post": "<mailto:linux-mtd@lists.infradead.org>", "List-Help": "<mailto:linux-mtd-request@lists.infradead.org?subject=help>", "List-Subscribe": "<http://lists.infradead.org/mailman/listinfo/linux-mtd>,\n\t<mailto:linux-mtd-request@lists.infradead.org?subject=subscribe>", "Cc": "Boris Brezillon <boris.brezillon@free-electrons.com>,\n\tMarek Vasut <marek.vasut@gmail.com>,\n\tRichard Weinberger <richard@nod.at>, linux-kernel@vger.kernel.org,\n\tMasahiro Yamada <yamada.masahiro@socionext.com>, \n\tCyrille Pitchen <cyrille.pitchen@wedev4u.fr>,\n\tBrian Norris <computersforpeace@gmail.com>,\n\tDavid Woodhouse <dwmw2@infradead.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "\"linux-mtd\" <linux-mtd-bounces@lists.infradead.org>", "Errors-To": "linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org" }, "content": "The Denali NAND IP core decodes the lower 28 bits of the slave address\nto get the control information; bit[27:26]=mode, bit[25:24]=bank, etc.\nThis means 256MB address range must be allocated for this IP. (Direct\nAddressing)\n\nFor systems with address space limitation, the Denali IP provides an\noptional module that translates the addressing - address and data are\nlatched by the registers in the translation module. (Indexed Addressing)\n\nThe addressing mode can be selected when the delivered RTL is configured,\nand it can be read out from the FEATURES register.\n\nMost of SoC vendors would choose Indexed Addressing to save the address\nspace, but Direct Addressing is possible as well, and it can be easily\nsupported by adding ->host_{read,write} hooks.\n\nSigned-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>\n---\n\nChanges in v2:\n - Newly added\n\n drivers/mtd/nand/denali.c | 109 +++++++++++++++++++++++++++++-----------------\n drivers/mtd/nand/denali.h | 2 +\n 2 files changed, 70 insertions(+), 41 deletions(-)", "diff": "diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c\nindex ee688e0..7c24983 100644\n--- a/drivers/mtd/nand/denali.c\n+++ b/drivers/mtd/nand/denali.c\n@@ -29,9 +29,9 @@ MODULE_LICENSE(\"GPL\");\n \n #define DENALI_NAND_NAME \"denali-nand\"\n \n-/* Host Data/Command Interface */\n-#define DENALI_HOST_ADDR\t0x00\n-#define DENALI_HOST_DATA\t0x10\n+/* for Indexed Addressing */\n+#define DENALI_INDEXED_CTRL\t0x00\n+#define DENALI_INDEXED_DATA\t0x10\n \n #define DENALI_MAP00\t\t(0 << 26)\t/* direct access to buffer */\n #define DENALI_MAP01\t\t(1 << 26)\t/* read/write pages in PIO */\n@@ -64,11 +64,39 @@ static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd)\n \treturn container_of(mtd_to_nand(mtd), struct denali_nand_info, nand);\n }\n \n-static void denali_host_write(struct denali_nand_info *denali,\n-\t\t\t uint32_t addr, uint32_t data)\n+/*\n+ * Direct Addressing - the slave address forms the control information (command\n+ * type, bank, block, and page address). The slave data is the actual data to\n+ * be transferred. This mode requires 28 bits of address region allocated.\n+ */\n+static u32 denali_direct_read(struct denali_nand_info *denali, u32 addr)\n+{\n+\treturn ioread32(denali->host + addr);\n+}\n+\n+static void denali_direct_write(struct denali_nand_info *denali, u32 addr,\n+\t\t\t\tu32 data)\n+{\n+\tiowrite32(data, denali->host + addr);\n+}\n+\n+/*\n+ * Indexed Addressing - address translation module intervenes in passing the\n+ * control information. This mode reduces the required address range. The\n+ * control information and transferred data are latched by the registers in\n+ * the translation module.\n+ */\n+static u32 denali_indexed_read(struct denali_nand_info *denali, u32 addr)\n {\n-\tiowrite32(addr, denali->host + DENALI_HOST_ADDR);\n-\tiowrite32(data, denali->host + DENALI_HOST_DATA);\n+\tiowrite32(addr, denali->host + DENALI_INDEXED_CTRL);\n+\treturn ioread32(denali->host + DENALI_INDEXED_DATA);\n+}\n+\n+static void denali_indexed_write(struct denali_nand_info *denali, u32 addr,\n+\t\t\t\t u32 data)\n+{\n+\tiowrite32(addr, denali->host + DENALI_INDEXED_CTRL);\n+\tiowrite32(data, denali->host + DENALI_INDEXED_DATA);\n }\n \n /*\n@@ -205,52 +233,44 @@ static uint32_t denali_check_irq(struct denali_nand_info *denali)\n static void denali_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)\n {\n \tstruct denali_nand_info *denali = mtd_to_denali(mtd);\n+\tu32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);\n \tint i;\n \n-\tiowrite32(DENALI_MAP11_DATA | DENALI_BANK(denali),\n-\t\t denali->host + DENALI_HOST_ADDR);\n-\n \tfor (i = 0; i < len; i++)\n-\t\tbuf[i] = ioread32(denali->host + DENALI_HOST_DATA);\n+\t\tbuf[i] = denali->host_read(denali, addr);\n }\n \n static void denali_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)\n {\n \tstruct denali_nand_info *denali = mtd_to_denali(mtd);\n+\tu32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);\n \tint i;\n \n-\tiowrite32(DENALI_MAP11_DATA | DENALI_BANK(denali),\n-\t\t denali->host + DENALI_HOST_ADDR);\n-\n \tfor (i = 0; i < len; i++)\n-\t\tiowrite32(buf[i], denali->host + DENALI_HOST_DATA);\n+\t\tdenali->host_write(denali, addr, buf[i]);\n }\n \n static void denali_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)\n {\n \tstruct denali_nand_info *denali = mtd_to_denali(mtd);\n+\tu32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);\n \tuint16_t *buf16 = (uint16_t *)buf;\n \tint i;\n \n-\tiowrite32(DENALI_MAP11_DATA | DENALI_BANK(denali),\n-\t\t denali->host + DENALI_HOST_ADDR);\n-\n \tfor (i = 0; i < len / 2; i++)\n-\t\tbuf16[i] = ioread32(denali->host + DENALI_HOST_DATA);\n+\t\tbuf16[i] = denali->host_read(denali, addr);\n }\n \n static void denali_write_buf16(struct mtd_info *mtd, const uint8_t *buf,\n \t\t\t int len)\n {\n \tstruct denali_nand_info *denali = mtd_to_denali(mtd);\n+\tu32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);\n \tconst uint16_t *buf16 = (const uint16_t *)buf;\n \tint i;\n \n-\tiowrite32(DENALI_MAP11_DATA | DENALI_BANK(denali),\n-\t\t denali->host + DENALI_HOST_ADDR);\n-\n \tfor (i = 0; i < len / 2; i++)\n-\t\tiowrite32(buf16[i], denali->host + DENALI_HOST_DATA);\n+\t\tdenali->host_write(denali, addr, buf16[i]);\n }\n \n static uint8_t denali_read_byte(struct mtd_info *mtd)\n@@ -295,7 +315,7 @@ static void denali_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl)\n \tif (ctrl & NAND_CTRL_CHANGE)\n \t\tdenali_reset_irq(denali);\n \n-\tdenali_host_write(denali, DENALI_BANK(denali) | type, dat);\n+\tdenali->host_write(denali, DENALI_BANK(denali) | type, dat);\n }\n \n static int denali_dev_ready(struct mtd_info *mtd)\n@@ -465,14 +485,14 @@ static void denali_setup_dma64(struct denali_nand_info *denali,\n \t * 1. setup transfer type, interrupt when complete,\n \t * burst len = 64 bytes, the number of pages\n \t */\n-\tdenali_host_write(denali, mode,\n-\t\t\t 0x01002000 | (64 << 16) | (write << 8) | page_count);\n+\tdenali->host_write(denali, mode,\n+\t\t\t 0x01002000 | (64 << 16) | (write << 8) | page_count);\n \n \t/* 2. set memory low address */\n-\tdenali_host_write(denali, mode, lower_32_bits(dma_addr));\n+\tdenali->host_write(denali, mode, lower_32_bits(dma_addr));\n \n \t/* 3. set memory high address */\n-\tdenali_host_write(denali, mode, upper_32_bits(dma_addr));\n+\tdenali->host_write(denali, mode, upper_32_bits(dma_addr));\n }\n \n static void denali_setup_dma32(struct denali_nand_info *denali,\n@@ -486,17 +506,17 @@ static void denali_setup_dma32(struct denali_nand_info *denali,\n \t/* DMA is a four step process */\n \n \t/* 1. setup transfer type and # of pages */\n-\tdenali_host_write(denali, mode | page,\n-\t\t\t 0x2000 | (write << 8) | page_count);\n+\tdenali->host_write(denali, mode | page,\n+\t\t\t 0x2000 | (write << 8) | page_count);\n \n \t/* 2. set memory high address bits 23:8 */\n-\tdenali_host_write(denali, mode | ((dma_addr >> 16) << 8), 0x2200);\n+\tdenali->host_write(denali, mode | ((dma_addr >> 16) << 8), 0x2200);\n \n \t/* 3. set memory low address bits 23:8 */\n-\tdenali_host_write(denali, mode | ((dma_addr & 0xffff) << 8), 0x2300);\n+\tdenali->host_write(denali, mode | ((dma_addr & 0xffff) << 8), 0x2300);\n \n \t/* 4. interrupt when complete, burst len = 64 bytes */\n-\tdenali_host_write(denali, mode | 0x14000, 0x2400);\n+\tdenali->host_write(denali, mode | 0x14000, 0x2400);\n }\n \n static void denali_setup_dma(struct denali_nand_info *denali,\n@@ -511,7 +531,7 @@ static void denali_setup_dma(struct denali_nand_info *denali,\n static int denali_pio_read(struct denali_nand_info *denali, void *buf,\n \t\t\t size_t size, int page, int raw)\n {\n-\tuint32_t addr = DENALI_BANK(denali) | page;\n+\tu32 addr = DENALI_MAP01 | DENALI_BANK(denali) | page;\n \tuint32_t *buf32 = (uint32_t *)buf;\n \tuint32_t irq_status, ecc_err_mask;\n \tint i;\n@@ -523,9 +543,8 @@ static int denali_pio_read(struct denali_nand_info *denali, void *buf,\n \n \tdenali_reset_irq(denali);\n \n-\tiowrite32(DENALI_MAP01 | addr, denali->host + DENALI_HOST_ADDR);\n \tfor (i = 0; i < size / 4; i++)\n-\t\t*buf32++ = ioread32(denali->host + DENALI_HOST_DATA);\n+\t\t*buf32++ = denali->host_read(denali, addr);\n \n \tirq_status = denali_wait_for_irq(denali, INTR__PAGE_XFER_INC);\n \tif (!(irq_status & INTR__PAGE_XFER_INC))\n@@ -540,16 +559,15 @@ static int denali_pio_read(struct denali_nand_info *denali, void *buf,\n static int denali_pio_write(struct denali_nand_info *denali,\n \t\t\t const void *buf, size_t size, int page, int raw)\n {\n-\tuint32_t addr = DENALI_BANK(denali) | page;\n+\tu32 addr = DENALI_MAP01 | DENALI_BANK(denali) | page;\n \tconst uint32_t *buf32 = (uint32_t *)buf;\n \tuint32_t irq_status;\n \tint i;\n \n \tdenali_reset_irq(denali);\n \n-\tiowrite32(DENALI_MAP01 | addr, denali->host + DENALI_HOST_ADDR);\n \tfor (i = 0; i < size / 4; i++)\n-\t\tiowrite32(*buf32++, denali->host + DENALI_HOST_DATA);\n+\t\tdenali->host_write(denali, addr, *buf32++);\n \n \tirq_status = denali_wait_for_irq(denali,\n \t\t\t\tINTR__PROGRAM_COMP | INTR__PROGRAM_FAIL);\n@@ -935,8 +953,8 @@ static int denali_erase(struct mtd_info *mtd, int page)\n \n \tdenali_reset_irq(denali);\n \n-\tdenali_host_write(denali, DENALI_MAP10 | DENALI_BANK(denali) | page,\n-\t\t\t DENALI_ERASE);\n+\tdenali->host_write(denali, DENALI_MAP10 | DENALI_BANK(denali) | page,\n+\t\t\t DENALI_ERASE);\n \n \t/* wait for erase to complete or failure to occur */\n \tirq_status = denali_wait_for_irq(denali,\n@@ -1227,6 +1245,7 @@ int denali_init(struct denali_nand_info *denali)\n {\n \tstruct nand_chip *chip = &denali->nand;\n \tstruct mtd_info *mtd = nand_to_mtd(chip);\n+\tu32 features = ioread32(denali->reg + FEATURES);\n \tint ret;\n \n \tmtd->dev.parent = denali->dev;\n@@ -1262,6 +1281,14 @@ int denali_init(struct denali_nand_info *denali)\n \tchip->dev_ready = denali_dev_ready;\n \tchip->waitfunc = denali_waitfunc;\n \n+\tif (features & FEATURES__INDEX_ADDR) {\n+\t\tdenali->host_read = denali_indexed_read;\n+\t\tdenali->host_write = denali_indexed_write;\n+\t} else {\n+\t\tdenali->host_read = denali_direct_read;\n+\t\tdenali->host_write = denali_direct_write;\n+\t}\n+\n \t/* clk rate info is needed for setup_data_interface */\n \tif (denali->clk_x_rate)\n \t\tchip->setup_data_interface = denali_setup_data_interface;\ndiff --git a/drivers/mtd/nand/denali.h b/drivers/mtd/nand/denali.h\nindex f55ee10..3aeb272 100644\n--- a/drivers/mtd/nand/denali.h\n+++ b/drivers/mtd/nand/denali.h\n@@ -319,6 +319,8 @@ struct denali_nand_info {\n \tunsigned int revision;\t\t/* IP revision */\n \tunsigned int caps;\t\t/* IP capability (or quirk) */\n \tconst struct nand_ecc_caps *ecc_caps;\n+\tu32 (*host_read)(struct denali_nand_info *denali, u32 addr);\n+\tvoid (*host_write)(struct denali_nand_info *denali, u32 addr, u32 data);\n };\n \n #define DENALI_CAP_HW_ECC_FIXUP\t\t\tBIT(0)\n", "prefixes": [ "v2", "11/12" ] }