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GET /api/patches/816980/?format=api
{ "id": 816980, "url": "http://patchwork.ozlabs.org/api/patches/816980/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1506007346-10037-19-git-send-email-jjhiblot@ti.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1506007346-10037-19-git-send-email-jjhiblot@ti.com>", "list_archive_url": null, "date": "2017-09-21T15:22:21", "name": "[U-Boot,18/23] ARM: OMAP5: set mmc clock frequency to 192MHz", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "96630551d471a15d9a14782887d64ca1b846926e", "submitter": { "id": 70508, "url": "http://patchwork.ozlabs.org/api/people/70508/?format=api", "name": "Jean-Jacques Hiblot", "email": "jjhiblot@ti.com" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1506007346-10037-19-git-send-email-jjhiblot@ti.com/mbox/", "series": [ { "id": 4414, "url": "http://patchwork.ozlabs.org/api/series/4414/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=4414", "date": "2017-09-21T15:22:03", "name": "mmc: omap5: Add support for UHS and HS200 modes", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/4414/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/816980/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/816980/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=ti.com header.i=@ti.com header.b=\"vjqWAi0e\";\n\tdkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xyght34rrz9s06\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 22 Sep 2017 01:37:18 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 32152C220E1; Thu, 21 Sep 2017 15:32:16 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id E5E71C220D7;\n\tThu, 21 Sep 2017 15:32:14 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid B997AC220CD; Thu, 21 Sep 2017 15:24:13 +0000 (UTC)", "from fllnx209.ext.ti.com (fllnx209.ext.ti.com [198.47.19.16])\n\tby lists.denx.de (Postfix) with ESMTPS id 12D56C21E28\n\tfor <u-boot@lists.denx.de>; Thu, 21 Sep 2017 15:24:09 +0000 (UTC)", "from dflxv15.itg.ti.com ([128.247.5.124])\n\tby fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v8LFN7w5009167; \n\tThu, 21 Sep 2017 10:23:07 -0500", "from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23])\n\tby dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LFN2gi009860;\n\tThu, 21 Sep 2017 10:23:02 -0500", "from DFLE105.ent.ti.com (10.64.6.26) by DFLE102.ent.ti.com\n\t(10.64.6.23) with Microsoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34;\n\tThu, 21 Sep 2017 10:23:02 -0500", "from dflp32.itg.ti.com (10.64.6.15) by DFLE105.ent.ti.com\n\t(10.64.6.26) with Microsoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend\n\tTransport; Thu, 21 Sep 2017 10:23:02 -0500", "from localhost (ileax41-snat.itg.ti.com [10.172.224.153])\n\tby dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LFN1ni015099;\n\tThu, 21 Sep 2017 10:23:02 -0500" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE,\n\tT_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com;\n\ts=ti-com-17Q1; t=1506007387;\n\tbh=Bf1kAeT4yEpPcezYK2+RzwF+dxoz6wSXrGVeBn2s9ro=;\n\th=From:To:CC:Subject:Date:In-Reply-To:References;\n\tb=vjqWAi0etdowOHB8nMMEntPG4XtJTR9NRPCQ08tZHiz5HKnQN4VhmLWXsA8Gz7muK\n\tQ52iN3T+y63ddq9xM8CQNXmugJCqLrL1OhIPlf2P3nCsVAa9NL/L+m/ZjKzNyEW5Bs\n\tyuIpAqdWjB9ukCupS4F+a7l6lcjXy7NNK/jd9Lps=", "From": "Jean-Jacques Hiblot <jjhiblot@ti.com>", "To": "<jh80.chung@samsung.com>, <trini@konsulko.com>, <kishon@ti.com>,\n\t<sjg@chromium.org>, <lokeshvutla@ti.com>", "Date": "Thu, 21 Sep 2017 17:22:21 +0200", "Message-ID": "<1506007346-10037-19-git-send-email-jjhiblot@ti.com>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1506007346-10037-1-git-send-email-jjhiblot@ti.com>", "References": "<1506007346-10037-1-git-send-email-jjhiblot@ti.com>", "MIME-Version": "1.0", "X-EXCLAIMER-MD-CONFIG": "e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180", "Cc": "u-boot@lists.denx.de", "Subject": "[U-Boot] [PATCH 18/23] ARM: OMAP5: set mmc clock frequency to 192MHz", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "From: Kishon Vijay Abraham I <kishon@ti.com>\n\nNow that omap_hsmmc has support for hs200 mode, change the clock\nfrequency to 192MHz. Also change the REFERENCE CLOCK frequency to\n192MHz based on which the internal mmc clock divider is calculated.\n\nSigned-off-by: Kishon Vijay Abraham I <kishon@ti.com>\nSigned-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>\n---\n arch/arm/include/asm/arch-omap5/clock.h | 2 +-\n arch/arm/include/asm/omap_mmc.h | 4 ++++\n arch/arm/mach-omap2/omap5/hw_data.c | 10 +++++-----\n 3 files changed, 10 insertions(+), 6 deletions(-)", "diff": "diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h\nindex ee2e78b..3d718c0 100644\n--- a/arch/arm/include/asm/arch-omap5/clock.h\n+++ b/arch/arm/include/asm/arch-omap5/clock.h\n@@ -135,7 +135,7 @@\n \n /* CM_L3INIT_HSMMCn_CLKCTRL */\n #define HSMMC_CLKCTRL_CLKSEL_MASK\t\t(1 << 24)\n-#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK\t\t(1 << 25)\n+#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK\t\t(3 << 25)\n \n /* CM_L3INIT_SATA_CLKCTRL */\n #define SATA_CLKCTRL_OPTFCLKEN_MASK\t\t(1 << 8)\ndiff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h\nindex 6871f54..d604b79 100644\n--- a/arch/arm/include/asm/omap_mmc.h\n+++ b/arch/arm/include/asm/omap_mmc.h\n@@ -199,7 +199,11 @@ struct omap_hsmmc_plat {\n #define MMC_CMD0\t(INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)\n \n /* Clock Configurations and Macros */\n+#ifdef CONFIG_OMAP54XX\n+#define MMC_CLOCK_REFERENCE\t192 /* MHz */\n+#else\n #define MMC_CLOCK_REFERENCE\t96 /* MHz */\n+#endif\n \n /* DLL */\n #define DLL_SWT\t\t\t(1 << 20)\ndiff --git a/arch/arm/mach-omap2/omap5/hw_data.c b/arch/arm/mach-omap2/omap5/hw_data.c\nindex 3bdb114..30e3b68 100644\n--- a/arch/arm/mach-omap2/omap5/hw_data.c\n+++ b/arch/arm/mach-omap2/omap5/hw_data.c\n@@ -438,17 +438,17 @@ void enable_basic_clocks(void)\n \tsetbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,\n \t\t\tGPIO4_CLKCTRL_OPTFCLKEN_MASK);\n \n-\t/* Enable 96 MHz clock for MMC1 & MMC2 */\n+\t/* Enable 192 MHz clock for MMC1 & MMC2 */\n \tsetbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,\n \t\t\tHSMMC_CLKCTRL_CLKSEL_MASK);\n \tsetbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,\n \t\t\tHSMMC_CLKCTRL_CLKSEL_MASK);\n \n \t/* Set the correct clock dividers for mmc */\n-\tsetbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,\n-\t\t\tHSMMC_CLKCTRL_CLKSEL_DIV_MASK);\n-\tsetbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,\n-\t\t\tHSMMC_CLKCTRL_CLKSEL_DIV_MASK);\n+\tclrbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,\n+\t\t HSMMC_CLKCTRL_CLKSEL_DIV_MASK);\n+\tclrbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,\n+\t\t HSMMC_CLKCTRL_CLKSEL_DIV_MASK);\n \n \t/* Select 32KHz clock as the source of GPTIMER1 */\n \tsetbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,\n", "prefixes": [ "U-Boot", "18/23" ] }