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GET /api/patches/816975/?format=api
{ "id": 816975, "url": "http://patchwork.ozlabs.org/api/patches/816975/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1506007346-10037-8-git-send-email-jjhiblot@ti.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1506007346-10037-8-git-send-email-jjhiblot@ti.com>", "list_archive_url": null, "date": "2017-09-21T15:22:10", "name": "[U-Boot,07/23] mmc: omap_hsmmc: Workaround for errata id i802", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "6ece56ccf512df33dfa3e825da8504010ba514be", "submitter": { "id": 70508, "url": "http://patchwork.ozlabs.org/api/people/70508/?format=api", "name": "Jean-Jacques Hiblot", "email": "jjhiblot@ti.com" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1506007346-10037-8-git-send-email-jjhiblot@ti.com/mbox/", "series": [ { "id": 4414, "url": "http://patchwork.ozlabs.org/api/series/4414/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=4414", "date": "2017-09-21T15:22:03", "name": "mmc: omap5: Add support for UHS and HS200 modes", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/4414/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/816975/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/816975/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=ti.com header.i=@ti.com header.b=\"DmvdPdg+\";\n\tdkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xygfw6KBmz9s06\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 22 Sep 2017 01:35:36 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 9C502C22112; Thu, 21 Sep 2017 15:33:48 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 9B90EC220C2;\n\tThu, 21 Sep 2017 15:33:45 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid B86CFC220BE; Thu, 21 Sep 2017 15:24:00 +0000 (UTC)", "from fllnx209.ext.ti.com (fllnx209.ext.ti.com [198.47.19.16])\n\tby lists.denx.de (Postfix) with ESMTPS id 56A35C2203D\n\tfor <u-boot@lists.denx.de>; Thu, 21 Sep 2017 15:23:56 +0000 (UTC)", "from dlelxv90.itg.ti.com ([172.17.2.17])\n\tby fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v8LFMrZf009137; \n\tThu, 21 Sep 2017 10:22:53 -0500", "from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24])\n\tby dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LFMm5o000326; \n\tThu, 21 Sep 2017 10:22:48 -0500", "from DFLE112.ent.ti.com (10.64.6.33) by DFLE103.ent.ti.com\n\t(10.64.6.24) with Microsoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34;\n\tThu, 21 Sep 2017 10:22:48 -0500", "from dlep33.itg.ti.com (157.170.170.75) by DFLE112.ent.ti.com\n\t(10.64.6.33) with Microsoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend\n\tTransport; Thu, 21 Sep 2017 10:22:48 -0500", "from localhost (ileax41-snat.itg.ti.com [10.172.224.153])\n\tby dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LFMllK001053;\n\tThu, 21 Sep 2017 10:22:48 -0500" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE,\n\tT_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com;\n\ts=ti-com-17Q1; t=1506007373;\n\tbh=DZcVRjVwQzmUyTgLDhVKFenjVJKeZrWFN43MF0d2RSs=;\n\th=From:To:CC:Subject:Date:In-Reply-To:References;\n\tb=DmvdPdg+AY+nAcaU+dRyfJuBYZJmyCSHiQsL2RDERd003M3WO+zsrUCh+sVyFQfWA\n\tiKj4127+1Msph5PybcMC/d9dFeDF1IsND9Inhbm3fNJ4ohQdTrp6uK12+13Opxsg+Z\n\t3iwQ3Rx3DATA8CVVFo5ErwuI7iHOeNKEKhqvg4dI=", "From": "Jean-Jacques Hiblot <jjhiblot@ti.com>", "To": "<jh80.chung@samsung.com>, <trini@konsulko.com>, <kishon@ti.com>,\n\t<sjg@chromium.org>, <lokeshvutla@ti.com>", "Date": "Thu, 21 Sep 2017 17:22:10 +0200", "Message-ID": "<1506007346-10037-8-git-send-email-jjhiblot@ti.com>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1506007346-10037-1-git-send-email-jjhiblot@ti.com>", "References": "<1506007346-10037-1-git-send-email-jjhiblot@ti.com>", "MIME-Version": "1.0", "X-EXCLAIMER-MD-CONFIG": "e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180", "Cc": "u-boot@lists.denx.de", "Subject": "[U-Boot] [PATCH 07/23] mmc: omap_hsmmc: Workaround for errata id\n\ti802", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "From: Kishon Vijay Abraham I <kishon@ti.com>\n\nAccording to errata i802, DCRC error interrupts\n(MMCHS_STAT[21] DCRC=0x1) can occur during the tuning procedure.\n\nThe DCRC interrupt, occurs when the last tuning block fails\n(the last ratio tested). The delay from CRC check until the\ninterrupt is asserted is bigger than the delay until assertion\nof the tuning end flag. Assertion of tuning end flag is what\nmasks the interrupts. Because of this race, an erroneous DCRC\ninterrupt occurs.\n\nThe suggested workaround is to disable DCRC interrupts during\nthe tuning procedure which is implemented here.\n\nSigned-off-by: Kishon Vijay Abraham I <kishon@ti.com>\nSigned-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>\n---\n arch/arm/include/asm/omap_mmc.h | 4 ++++\n drivers/mmc/omap_hsmmc.c | 26 ++++++++++++++++++++++----\n 2 files changed, 26 insertions(+), 4 deletions(-)", "diff": "diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h\nindex 0293281..0893844 100644\n--- a/arch/arm/include/asm/omap_mmc.h\n+++ b/arch/arm/include/asm/omap_mmc.h\n@@ -219,6 +219,10 @@ struct omap_hsmmc_plat {\n #define mmc_reg_out(addr, mask, val)\\\n \twritel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))\n \n+#define INT_EN_MASK (IE_BADA | IE_CERR | IE_DEB | IE_DCRC |\\\n+\t\tIE_DTO | IE_CIE | IE_CEB | IE_CCRC | IE_ADMAE | IE_CTO |\\\n+\t\tIE_BRR | IE_BWR | IE_TC | IE_CC)\n+\n int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,\n \t\tint wp_gpio);\n \ndiff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c\nindex 321a091..8e42410 100644\n--- a/drivers/mmc/omap_hsmmc.c\n+++ b/drivers/mmc/omap_hsmmc.c\n@@ -474,6 +474,25 @@ tuning_error:\n }\n #endif\n \n+static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd)\n+{\n+\tstruct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);\n+\tstruct hsmmc *mmc_base = priv->base_addr;\n+\tu32 irq_mask = INT_EN_MASK;\n+\n+\t/*\n+\t * TODO: Errata i802 indicates only DCRC interrupts can occur during\n+\t * tuning procedure and DCRC should be disabled. But see occurences\n+\t * of DEB, CIE, CEB, CCRC interupts during tuning procedure. These\n+\t * interrupts occur along with BRR, so the data is actually in the\n+\t * buffer. It has to be debugged why these interrutps occur\n+\t */\n+\tif (cmd && mmc_is_tuning_cmd(cmd->cmdidx))\n+\t\tirq_mask &= ~(IE_DEB | IE_DCRC | IE_CIE | IE_CEB | IE_CCRC);\n+\n+\twritel(irq_mask, &mmc_base->ie);\n+}\n+\n static int omap_hsmmc_init_setup(struct mmc *mmc)\n {\n \tstruct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);\n@@ -540,10 +559,7 @@ static int omap_hsmmc_init_setup(struct mmc *mmc)\n \n \twritel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);\n \n-\twritel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |\n-\t\tIE_CEB | IE_CCRC | IE_ADMAE | IE_CTO | IE_BRR | IE_BWR | IE_TC |\n-\t\tIE_CC, &mmc_base->ie);\n-\n+\tmmc_enable_irq(mmc, NULL);\n \tmmc_init_stream(mmc_base);\n \n \treturn 0;\n@@ -806,6 +822,8 @@ static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,\n #endif\n \t}\n \n+\tmmc_enable_irq(mmc, cmd);\n+\n \twritel(cmd->cmdarg, &mmc_base->arg);\n \tudelay(20);\t\t/* To fix \"No status update\" error on eMMC */\n \twritel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);\n", "prefixes": [ "U-Boot", "07/23" ] }